CN117439596A - Receiving circuit, deserializing circuit chip, electronic equipment and vehicle - Google Patents

Abstract

The present disclosure relates to the field of electronic and electrical technology, and provides a receiving circuit, a deserializing circuit chip, electronic equipment and a vehicle. The receiving circuit includes at least two-stage receiving modules and a gain module spaced apart from the receiving module; the first end of the receiving module at the front stage is connected to the first end of the gain module, and the second end of the receiving module at the front stage is connected to the gain module. The second end of the gain module, the third end of the gain module is connected to the first end of the receiving module in the subsequent stage, and the fourth end of the gain module is connected to the second end of the receiving module in the subsequent stage; the receiving module in the front stage is configured to push down The low-frequency gain of the received signal; the gain module is configured to compensate the low-frequency gain to the receiving module in the subsequent stage; the receiving module in the subsequent stage is configured to equalize the low-frequency gain and high-frequency gain of the received signal. Using the receiving circuit of the present disclosure, not only can a wide range of equalization be achieved, but the chip occupied area can also be reduced, and the cost is low.

Description

A receiving circuit, deserializing circuit chip, electronic equipment and vehicle

Technical field

The present disclosure relates to the field of electronic and electrical technology, and in particular to a receiving circuit, a deserializing circuit chip, electronic equipment and a vehicle.

Background technique

SERDES (Serializer-Deserializer) is a device that converts multiple low-speed parallel signals into high-speed serial signals at the transmitting end, and then converts the high-speed serial signals into low-speed parallel signals at the receiving end after passing through the transmission medium. communication technology. With the continuous popularization and development of high-definition video, the requirements for SERDES circuits have also increased, which is mainly reflected in the video transmission speed.

As the technology becomes more and more advanced, the video transmission speed has been improved. However, the transmission medium has not improved well. At the same time, the internal voltage of the chip is getting lower and lower, and the voltage margin left for the receiving circuit will also decrease. Therefore, it is increasingly difficult for traditional receiving circuits to meet actual needs, and it will be more difficult to compensate for higher wire attenuation. In order to achieve low-frequency and high-frequency gain balance, related technologies usually use inductors to perform gain compensation for high frequencies. However, in this method, the inductor occupies a large chip area and the process cost is higher, which has limitations.

Contents of the invention

Based on this, it is necessary to provide a receiving circuit, a deserializing circuit chip, an electronic device and a vehicle to address the above defects or deficiencies, which can not only achieve a wide range of equalization, but also reduce the chip area and be low-cost.

In a first aspect, an embodiment of the present disclosure provides a receiving circuit, which includes at least two-stage receiving modules and a gain module spaced apart from the receiving modules;

The first end of the receiving module at the front stage is connected to the first end of the gain module, the second end of the receiving module at the front stage is connected to the second end of the gain module, and the third end of the gain module The first end of the receiving module in the subsequent stage is connected, and the fourth end of the gain module is connected to the second end of the receiving module in the subsequent stage;

The receiving module at the front stage is configured to suppress the low-frequency gain of the received signal; the gain module is configured to compensate the low-frequency gain to the receiving module at the rear stage; the receiving module at the rear stage is configured to The low-frequency gain and high-frequency gain of the received signal are equalized.

Optionally, in some embodiments of the present disclosure, the gain module includes a first field effect transistor, a second field effect transistor, a first current source, a first resistor and a second resistor;

The first end of the first field effect transistor is connected to the first end of the receiving module at the front stage, and the second end of the first field effect transistor is connected to the first end of the first current source. The second end of the first current source is grounded, and the third end of the first field effect transistor is connected to the first end of the first resistor and the first end of the receiving module at the rear stage respectively. The second end of the first resistor is connected to the power supply, the first end of the second field effect transistor is connected to the second end of the receiving module at the front stage, and the second end of the second field effect transistor is connected to the first The first end of a current source and the third end of the second field effect transistor are respectively connected to the first end of the second resistor and the second end of the subsequent receiving module. The second resistor The second end is connected to the power supply.

Optionally, in some embodiments of the present disclosure, both the first field effect transistor and the second field effect transistor are NMOS transistors;

The first end of the first field effect transistor is the gate of the NMOS transistor, the second end of the first field effect transistor is the source of the NMOS transistor, and the third end of the first field effect transistor is the NMOS transistor. The drain of the second field effect transistor, the first terminal of the second field effect transistor is the gate of the NMOS tube, the second terminal of the second field effect transistor is the source of the NMOS tube, and the third terminal of the second field effect transistor is The terminal is the drain of the NMOS tube.

Optionally, in some embodiments of the present disclosure, each receiving module is based on a continuous-time linear equalization architecture.

Optionally, in some embodiments of the present disclosure, the receiving module at the front stage includes a third field effect transistor, a fourth field effect transistor, a capacitor, a third resistor, a second current source, a third current source, and a third field effect transistor. four resistors and a fifth resistor;

The first end of the third field effect transistor is connected to a signal, and the second end of the third field effect transistor is connected to the first end of the capacitor, the first end of the third resistor and the first end of the third field effect transistor respectively. The first ends of the two current sources are connected, and the third end of the third field effect transistor is connected to the first end of the fourth resistor and the first end of the gain module respectively. The second current source The second end of the fourth resistor is connected to the ground, the second end of the fourth resistor is connected to the power supply, the first end of the fourth field effect transistor is connected to another signal, and the second end of the fourth field effect transistor is connected to the The second end of the capacitor, the second end of the third resistor and the first end of the third current source are connected, and the third end of the fourth field effect transistor is respectively connected to the first end of the fifth resistor. The second end of the fifth resistor is connected to the second end of the gain module, and the second end of the fifth resistor is connected to the power supply.

Optionally, in some embodiments of the present disclosure, the third field effect transistor and the fourth field effect transistor are both NMOS transistors;

The first end of the third field effect transistor is the gate of the NMOS transistor, the second end of the third field effect transistor is the source of the NMOS transistor, and the third end of the third field effect transistor is the NMOS transistor. The drain of the fourth field effect transistor is the gate of the NMOS tube, the second terminal of the fourth field effect transistor is the source of the NMOS tube, and the third terminal of the fourth field effect transistor is the source of the NMOS tube. The terminal is the drain of the NMOS tube.

Optionally, in some embodiments of the present disclosure, the receiving module includes a first-level receiving module and a second-level receiving module, and the gain module includes a first gain module and a gain module disposed after the first-level receiving module. A second gain module is provided after the second-stage receiving module.

In a second aspect, embodiments of the present disclosure provide a deserialization circuit chip, which includes the receiving circuit described in any one of the first aspects.

In a third aspect, embodiments of the present disclosure provide an electronic device. The electronic device includes a serial circuit chip, a transmission medium, and the deserialization circuit chip described in the second aspect, wherein the transmission medium is disposed on the serial circuit chip. between the circuit chip and the deserialization circuit chip.

In a fourth aspect, an embodiment of the present disclosure provides a vehicle, which includes the electronic device described in the third aspect.

It can be seen from the above technical solutions that the embodiments of the present disclosure have the following advantages:

In the receiving circuit, deserializing circuit chip, electronic equipment and vehicle provided by the embodiments of the present disclosure, the receiving circuit can increase the low-frequency gain by setting gain modules between the receiving modules, so that the receiving module in the later stage has more low-frequency The gain space can be used to expand the equalization range, and if the bandwidth allows, it can continue to be cascaded to achieve a wider range of equalization. At the same time, no inductor is needed, which reduces the chip area and greatly reduces the cost.

Description of the drawings

Other features, objects and advantages of the present disclosure will become more apparent upon reading the detailed description of the non-limiting embodiments with reference to the following drawings:

Figure 1 is a schematic structural diagram of a receiving circuit provided by an embodiment of the present disclosure;

Figure 2 is a structural block diagram of a receiving circuit provided by an embodiment of the present disclosure;

Figure 3 is a schematic structural diagram of another receiving circuit provided by an embodiment of the present disclosure;

Figure 4 is a structural block diagram of a deserialization circuit chip provided by an embodiment of the present disclosure;

Figure 5 is a structural block diagram of an electronic device provided by an embodiment of the present disclosure;

Figure 6 is a structural block diagram of a vehicle provided by an embodiment of the present disclosure.

Detailed ways

In order to enable those skilled in the art to better understand the present disclosure, the following will clearly and completely describe the technical solutions in the present disclosure embodiments in conjunction with the accompanying drawings. Obviously, the described embodiments are only These are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of this disclosure.

The terms "first", "second", "third", "fourth", etc. (if present) in the description and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects without necessarily using Used to describe a specific order or sequence. It is to be understood that the figures so used are interchangeable under appropriate circumstances so that the described embodiments of the present disclosure can be practiced in sequences other than those illustrated or described herein.

In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or modules and need not be limited to those explicitly listed. Those steps or modules may instead include other steps or modules not expressly listed or inherent to the processes, methods, products or devices.

In order to facilitate a better understanding of the present disclosure, description will now be made in conjunction with the receiving circuit shown in FIG. 1 . For example, the receiving circuit provided by the embodiment of the present disclosure is based on the Continuous Time Linear Equalizer (CTLE) architecture. As can be seen from Figure 1, two levels of CTLE are directly cascaded, and the CTLE reduces the low-frequency gain to increase the high-frequency gain. to achieve equilibrium. Since the received signal of CTLE is usually a high-speed signal transmitted through a long transmission line, the high-frequency signal is greatly attenuated at this time, and the low-frequency signal is also attenuated to a certain extent. In this case, the low-frequency gain space left for CTLE to be reduced is Extremely limited. If the low-frequency voltage of the first-stage CTLE is too low, the swing of the low-frequency signal will be very small. If the two-stage CTLEs are directly cascaded, the performance of the second-stage CTLE will be greatly limited, seriously affecting the overall equalization effect.

To this end, embodiments of the present disclosure provide a receiving circuit, a deserializing circuit chip, an electronic device, and a vehicle. Please refer to Figure 2, which is a structural block diagram of a receiving circuit provided by an embodiment of the present disclosure. The receiving circuit 10 includes at least two-stage receiving modules 11 and gain modules 12 spaced apart from the receiving modules 11. Each receiving module 11 can be Based on continuous time linear equalization architecture. Among them, the first end of the receiving module 11 at the front stage is connected to the first end of the gain module 12, the second end of the receiving module 11 at the front stage is connected to the second end of the gain module 12, and the third end of the gain module 12 The first end of the receiving module 11 in the subsequent stage is connected, and the fourth end of the gain module 12 is connected to the second end of the receiving module 11 in the subsequent stage.

Illustratively, in the receiving circuit 10 of the embodiment of the present disclosure, the receiving module 11 at the front stage can reduce the low-frequency gain of the received signal, and at the same time, the gain module 12 can compensate the low-frequency gain to the receiving module 11 at the rear stage, and then the gain module 11 at the rear stage can reduce the low-frequency gain. The receiving module 11 can equalize the low-frequency gain and high-frequency gain of the received signal. The advantage of this arrangement is that by arranging the gain module 12 between the receiving modules 11, the low-frequency gain can be increased. Therefore, the receiving module 11 at the later stage has more low-frequency gain space to use, which expands the equalization range and allows the In this case, the cascade can be continued to achieve a wider range of equilibrium.

The specific circuit structure of each component module in the receiving circuit 10 will be described in detail below with reference to FIG. 3 . For example, the gain module 12 includes but is not limited to a first field effect transistor Q1, a second field effect transistor Q2, a first current source A1, a first resistor R1 and a second resistor R2, wherein the first terminal of the first field effect transistor Q1 (corresponding to the first end of the gain module 12) is connected to the first end of the receiving module 11 in the front stage, and the second end of the first field effect transistor Q1 is connected to the first end of the first current source A1. The first current source A1 The second end of the first field effect transistor Q1 is connected to the ground, and the third end of the first field effect transistor Q1 (corresponding to the third end of the gain module 12) is in phase with the first end of the first resistor R1 and the first end of the receiving module 11 at the rear stage respectively. connection, the second end of the first resistor R1 is connected to the power supply (VDD), the first end of the second field effect transistor Q2 (corresponding to the second end of the gain module 12) is connected to the second end of the receiving module 11 in the front stage, The second terminal of the second field effect transistor Q2 is connected to the first terminal of the first current source A1, and the third terminal of the second field effect transistor Q2 (corresponding to the fourth terminal of the gain module 12) is respectively connected to the third terminal of the second resistor R2. One end is connected to the second end of the subsequent receiving module 11, and the second end of the second resistor R2 is connected to the power supply (VDD).

Optionally, in some embodiments of the present disclosure, the first field effect transistor Q1 and the second field effect transistor Q2 may both be NMOS transistors, where the first end of the first field effect transistor Q1 is the gate of the NMOS transistor, and the first field effect transistor Q1 is the gate of the NMOS transistor. The second terminal of the effect transistor Q1 is the source of the NMOS tube, the third terminal of the first field effect transistor Q1 is the drain of the NMOS tube, and the first terminal of the second field effect transistor Q2 is the gate of the NMOS tube. The second terminal of the second field effect transistor Q2 is the source of the NMOS tube, and the third terminal of the second field effect transistor Q2 is the drain of the NMOS tube.

For another example, the receiving module 11 at the front stage includes but is not limited to the third field effect transistor Q3, the fourth field effect transistor Q4, the capacitor C1, the third resistor R3, the second current source A2, the third current source A3, the fourth Resistor R4 and fifth resistor R5, the first end of the third field effect transistor Q3 (corresponding to RX_P) is connected to a signal, and the second end of the third field effect transistor Q3 is connected to the first end of the capacitor C1 and the third resistor respectively. The first end of R3 is connected to the first end of the second current source A2, and the third end of the third field effect transistor Q3 (corresponding to the first end of the receiving module 11 at the front stage) is respectively connected to the third end of the fourth resistor R4. One end is connected to the first end of the gain module 12, the second end of the second current source A2 is connected to ground, the second end of the fourth resistor R4 is connected to the power supply (VDD), and the first end of the fourth field effect transistor Q4 (corresponding to RX_N) is connected to another signal. The second end of the fourth field effect transistor Q4 is connected to the second end of the capacitor C1, the second end of the third resistor R3 and the first end of the third current source A3. The fourth The third end of the field effect transistor Q4 (corresponding to the second end of the receiving module 11 in the front stage) is connected to the first end of the fifth resistor R5 and the second end of the gain module 12 respectively. The second end of the fifth resistor R5 The terminal is connected to the power supply (VDD).

Optionally, in some embodiments of the present disclosure, the third field effect transistor Q3 and the fourth field effect transistor Q4 may both be NMOS tubes, where the first end of the third field effect transistor Q3 is the gate of the NMOS tube, and the third field effect transistor Q3 is the gate electrode of the NMOS tube. The second terminal of the effect transistor Q3 is the source of the NMOS tube, the third terminal of the third field effect transistor Q3 is the drain of the NMOS tube, and the first terminal of the fourth field effect transistor Q4 is the gate of the NMOS tube. The second terminal of the fourth field effect transistor Q4 is the source of the NMOS tube, and the third terminal of the fourth field effect transistor Q4 is the drain of the NMOS tube.

Optionally, in some embodiments of the present disclosure, the receiving module 11 includes, but is not limited to, the first-stage receiving module 111 and the second-stage receiving module 112, and the gain module 12 includes, but is not limited to, the third-stage receiving module 111 provided after the first-stage receiving module 111. A gain module 121 and a second gain module 122 arranged after the second-stage receiving module 112.

As another aspect, embodiments of the present disclosure also provide a deserialization circuit chip. As shown in FIG. 4 , the deserialization circuit chip 20 may include but is not limited to the receiving circuit 10 in the corresponding embodiment of FIG. 2 to FIG. 3 .

As yet another aspect, embodiments of the present disclosure also provide an electronic device. As shown in FIG. 5 , the electronic device 30 may include a serial circuit chip 31 , a transmission medium 32 and a deserialization circuit chip 20 in the corresponding embodiment of FIG. 4 . Among them, the transmission medium 32 is provided between the serial circuit chip 31 and the deserialization circuit chip 20. For example, the transmission medium 32 can be a shielded twisted pair (Shielded Twisted Pair, STP) or a coaxial cable (Coaxial cable, COAX), etc. .

As yet another aspect, embodiments of the present disclosure also provide a vehicle. As shown in FIG. 6 , the vehicle 40 may include the electronic device 30 in the corresponding embodiment of FIG. 5 .

Embodiments of the present disclosure provide a receiving circuit, a deserializing circuit chip, an electronic device and a vehicle. The receiving circuit can increase the low-frequency gain by arranging gain modules between receiving modules, so that the receiving module in the later stage has more The low-frequency gain space can be used to expand the equalization range, and if the bandwidth allows, it can continue to be cascaded to achieve a wider range of equalization. At the same time, no inductor is needed, which reduces the chip area and greatly reduces the cost.

The technical features of the above embodiments can be combined in any way. To simplify the description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, all possible combinations should be used. It is considered to be within the scope of this manual.

The above embodiments only express several implementation modes of the present disclosure, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention. It should be noted that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these all fall within the protection scope of the present disclosure.

Claims (10)

1. A receiving circuit, characterized in that the receiving circuit comprises at least two stages of receiving modules and gain modules arranged at intervals with the receiving modules;

the first end of the receiving module at the front stage is connected with the first end of the gain module, the second end of the receiving module at the front stage is connected with the second end of the gain module, the third end of the gain module is connected with the first end of the receiving module at the rear stage, and the fourth end of the gain module is connected with the second end of the receiving module at the rear stage;

the receiving module at the front stage is configured to suppress the low-frequency gain of the received signal; the gain module is configured to compensate low-frequency gain to the receiving module at the subsequent stage; the receiving module at the subsequent stage is configured to equalize a low-frequency gain and a high-frequency gain of the received signal.

2. The receive circuit of claim 1, wherein the gain module comprises a first field effect transistor, a second field effect transistor, a first current source, a first resistor, and a second resistor;

the first end of the first field effect tube is connected with the first end of the receiving module at the front stage, the second end of the first field effect tube is connected with the first end of the first current source, the second end of the first current source is grounded, the third end of the first field effect tube is respectively connected with the first end of the first resistor and the first end of the receiving module at the rear stage, the second end of the first resistor is connected with a power supply, the first end of the second field effect tube is connected with the second end of the receiving module at the front stage, the second end of the second field effect tube is connected with the first end of the first current source, the third end of the second field effect tube is respectively connected with the first end of the second resistor and the second end of the receiving module at the rear stage, and the second end of the second resistor is connected with the power supply.

3. The receiving circuit of claim 2, wherein the first field effect transistor and the second field effect transistor are NMOS transistors;

the first end of the first field effect tube is a grid electrode of the NMOS tube, the second end of the first field effect tube is a source electrode of the NMOS tube, the third end of the first field effect tube is a drain electrode of the NMOS tube, the first end of the second field effect tube is a grid electrode of the NMOS tube, the second end of the second field effect tube is a source electrode of the NMOS tube, and the third end of the second field effect tube is a drain electrode of the NMOS tube.

4. A receiving circuit according to any one of claims 1 to 3, wherein each of the receiving modules is based on a continuous time linear equalization architecture.

5. The receiving circuit of claim 4, wherein the receiving module at the front stage comprises a third fet, a fourth fet, a capacitor, a third resistor, a second current source, a third current source, a fourth resistor, and a fifth resistor;

the first end of the third field effect tube is connected with one path of signal, the second end of the third field effect tube is respectively connected with the first end of the capacitor, the first end of the third resistor and the first end of the second current source, the third end of the third field effect tube is respectively connected with the first end of the fourth resistor and the first end of the gain module, the second end of the second current source is grounded, the second end of the fourth resistor is connected with a power supply, the first end of the fourth field effect tube is connected with another path of signal, the second end of the fourth field effect tube is respectively connected with the second end of the capacitor, the second end of the third resistor and the first end of the third current source, the third end of the fourth field effect tube is respectively connected with the first end of the fifth resistor and the second end of the gain module, and the second end of the fifth resistor is connected with the power supply.

6. The receiving circuit of claim 5, wherein the third fet and the fourth fet are NMOS transistors;

the first end of the third field effect tube is a grid electrode of the NMOS tube, the second end of the third field effect tube is a source electrode of the NMOS tube, the third end of the third field effect tube is a drain electrode of the NMOS tube, the first end of the fourth field effect tube is a grid electrode of the NMOS tube, the second end of the fourth field effect tube is a source electrode of the NMOS tube, and the third end of the fourth field effect tube is a drain electrode of the NMOS tube.

7. The receive circuit of claim 6, wherein the receive modules comprise a first stage receive module and a second stage receive module, and wherein the gain module comprises a first gain module disposed after the first stage receive module and a second gain module disposed after the second stage receive module.

8. A deserializing circuit chip, characterized in that it comprises the receiving circuit of any one of claims 1 to 7.

9. An electronic device comprising a serial circuit chip, a transmission medium, and the deserializing circuit chip of claim 8, wherein the transmission medium is disposed between the serial circuit chip and the deserializing circuit chip.

10. A vehicle, characterized in that it comprises the electronic device of claim 9.