CN117438395A - Semiconductor device having pad structure for resisting plasma damage and method of manufacturing the same - Google Patents

Abstract

A semiconductor device having a bonding pad structure resistant to plasma damage and a method of fabricating the same. The semiconductor device having a pad structure resistant to plasma damage includes: a main pad portion including a plurality of main conductor units and a plurality of main interlayer connection units; a sub-pad portion including a plurality of sub-conductor units and a plurality of sub-interlayer connection units; a pad bonding unit in direct contact with and connected to the top main conductive unit, wherein the top main conductive unit is a main conductive unit formed in the uppermost metal layer; and a bridge pad unit in direct contact with and connected to the top sub-conductor unit, wherein the top sub-conductor unit is a sub-conductor unit formed in the uppermost metal layer; wherein the bridging bonding pad unit is directly contacted and connected with the bonding pad bonding unit; the main bonding pad part and the sub bonding pad part are respectively positioned below the bonding pad bonding unit and the bridging bonding pad unit, and are not directly connected with each other.

Description

Semiconductor component with pad structure resistant to plasma damage and manufacturing method thereof

Technical field

The present invention relates to a semiconductor element with a pad structure that is resistant to plasma damage and a manufacturing method thereof. In particular, it relates to a semiconductor element with a pad structure that is resistant to plasma damage, and particularly relates to a device that has a pad structure that is resistant to plasma damage and connects a main pad portion and a sub-pad portion to a pad bonding unit only through a bridge pad unit. Semiconductor components with pad structures and manufacturing methods thereof.

Background technique

Please refer to FIG. 1 , which is a schematic cross-sectional view showing a bonding pad structure of a known semiconductor device. As shown in Figure 1, the metal layers M13, M23, M33, M43 of each layer in the known pad structure of the semiconductor component, and the connection unit Via4 connecting the metal layers M13, M23, M33, M43 of each layer , and each dielectric layer has a severe plasma damage effect (or antenna effect) on the gate of the metal oxide semiconductor device below. This will make the gate of the metal oxide semiconductor device below easily broken down and damaged.

In view of this, the present invention proposes a semiconductor component with a pad structure resistant to plasma damage and a manufacturing method thereof, which can effectively reduce the plasma damage effect.

Contents of the invention

In one aspect, the present invention provides a semiconductor device with a bonding pad structure that is resistant to plasma damage, including: a main pad portion including a plurality of main pads formed in a plurality of metal layers. a main conductor unit and a plurality of main interlayer connection units (main viaunits) correspondingly formed in a plurality of dielectric layers, wherein a plurality of the main interlayer connection units are electrically connected to a plurality of the main conductor units, and A plurality of the main conductor units are electrically connected to each other; a sub-pad portion includes a plurality of sub-conductor units (sub-conductor units) correspondingly formed in a plurality of the metal layers and a plurality of corresponding sub-conductor units formed in the plurality of metal layers. a plurality of inter-layer connection units (sub-via units) in the dielectric layer, wherein a plurality of the sub-layer connection units are electrically connected to a plurality of the sub-conductor units, so that a plurality of the sub-conductor units are electrically connected to each other, And the sub-pad portion is electrically connected to the gate of at least one metal oxide semiconductor (MOS) component; a pad bonding unit is in direct contact with and connected to a top main conductor unit, wherein the top main conductor unit It is the main conductor unit formed in the uppermost metal layer; and a bridge pad unit directly contacts and connects to a top sub-conductor unit, wherein the top sub-conductor unit is formed in the top The sub-conductor unit in the metal layer; wherein the bridge pad unit is in direct contact with and connected to the pad joining unit; wherein the main pad part and the sub-pad part are respectively located between the pad joining unit and the bridge Below the bonding pad unit, the main bonding pad part and the sub-bonding pad part are not directly connected to each other.

In another aspect, the present invention provides a method for manufacturing a semiconductor component with a bonding pad structure that is resistant to plasma damage, including: using a patterning process step to form a main bonding pad portion and a sub-bonding pad portion, The main pad portion includes a plurality of main conductor units correspondingly formed in a plurality of metal layers and a plurality of main inter-layer connection units correspondingly formed in a plurality of dielectric layers, wherein the plurality of main inter-layer connection units correspond to The plurality of main conductor units are electrically connected to each other, wherein the sub-pad portion includes a plurality of sub-conductor units correspondingly formed in a plurality of the metal layers and a plurality of correspondingly formed in the plurality of vias. A plurality of sub-layer connection units in the electrical layer, wherein a plurality of the sub-layer connection units are electrically connected to a plurality of the sub-conductor units, so that the plurality of sub-conductor units are electrically connected to each other, and the sub-bonding pad portion is electrically connected The gate of at least one MOS device; forming a pad bonding unit so that the pad bonding unit directly contacts and connects to a top main conductor unit, wherein the top main conductor unit is formed on the top The main conductor unit in the metal layer; and forming a bridge pad unit so that the bridge pad unit is in direct contact and connected with a top sub-conductor unit, wherein the top sub-conductor unit is formed on the top The sub-conductor unit in the metal layer; wherein the bridge pad unit is in direct contact with and connected to the pad joining unit; wherein the main pad part and the sub-pad part are respectively located between the pad joining unit and the bridge Below the bonding pad unit, the main bonding pad part and the sub-bonding pad part are not directly connected to each other.

In one embodiment, the sub-conductor unit surrounds the corresponding main conductor unit formed in the same metal layer.

In one embodiment, the sub-conductor unit does not surround the corresponding main conductor unit formed in the same metal layer, but is located outside the corresponding main conductor unit formed in the same metal layer and has a point shape structure.

In one embodiment, the surface area of each main conductor unit is greater than the surface area of each sub-conductor unit.

In one embodiment, the ratio between the surface area of the plurality of sub-conductor units and the surface area of the gate is lower than a predetermined antenna design specification ratio.

In one embodiment, the pad bonding unit and the bridge pad unit are formed in a redistribution layer (RDL) located on the main pad part and the sub-pad part, and the redistribution layer Directly connected to the top metal layer.

In one embodiment, the main conductor unit and the sub-conductor unit are made of copper or aluminum.

In one embodiment, the pad joining unit and the bridging pad unit are made of aluminum.

In one embodiment, the bridge pad unit and the pad joining unit are formed using electroplating process steps.

The advantage of the present invention is that the present invention uses electroplating process steps to form the pad joining unit and the bridge pad unit, and the main pad part and the sub-pad part are connected only through the pad joining unit and the bridge pad unit, which can significantly Reduce plasma damage.

It will be easier to understand the purpose, technical content, characteristics and achieved effects of the present invention through detailed description below through specific embodiments.

Description of the drawings

FIG. 1 is a schematic cross-sectional view showing a bonding pad structure of a known semiconductor device.

FIG. 2 is a schematic cross-sectional view showing a semiconductor device having a bonding pad structure that resists plasma damage according to an embodiment of the present invention.

3 is a schematic top view showing a semiconductor device having a bonding pad structure that resists plasma damage according to an embodiment of the present invention.

4 is a schematic top view showing a semiconductor device having a bonding pad structure that resists plasma damage according to another embodiment of the present invention.

5A-5Q illustrate a schematic cross-sectional view of a manufacturing method of a semiconductor device having a bonding pad structure resistant to plasma damage according to an embodiment of the present invention.

Explanation of symbols in the figure

20: Semiconductor components with pad structures resistant to plasma damage

201: Main soldering pad part

2011: Main Conductor Unit

2011a, 2021a: Wide vias

2012: Main inter-floor connection unit

2012a, 2022a: Narrow vias

202: Sub-soldering pad part

2021: Subconductor Unit

2022: Inter-sublayer connection unit

203, M13, M23, M33, M43: metal layer

204: Dielectric layer

205: Pad bonding unit

206: Bridge Pad Unit

207: Protective layer

208: Polymer layer

209: Gate

210: Conductive plug

Via4: connection unit

Detailed ways

The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings. The drawings in the present invention are all schematic, and are mainly intended to represent the process steps and the upper and lower order relationships between the layers. As for the shape, thickness and width, they are not drawn to scale.

FIG. 2 is a schematic cross-sectional view showing a semiconductor device having a bonding pad structure that resists plasma damage according to an embodiment of the present invention. As shown in FIG. 2 , the semiconductor component 20 with a pad structure resistant to plasma damage of the present invention includes a main pad portion 201 , a sub-pad portion 202 , and a pad bonding unit. (padbonding unit) 205 and bridge pad unit (bridge pad unit) 206. The main pad portion 201 includes a plurality of main conductor units 2011 correspondingly formed in a plurality of metal layers 203 and a plurality of main interlayer connection units (main via units) correspondingly formed in a plurality of dielectric layers 204 )2012. The plurality of main interlayer connection units 2012 are electrically connected to the plurality of main conductor units 2011 correspondingly, so that the plurality of main conductor units 2011 are electrically connected to each other. The sub-pad portion 202 includes a plurality of sub-conductor units 2021 formed in a plurality of metal layers 203 and a plurality of sub-via units formed in a plurality of dielectric layers 204 . )2022. The plurality of sub-layer connection units 2022 are electrically connected to the plurality of sub-conductor units 2021 correspondingly, so that the plurality of sub-conductor units 2021 are electrically connected to each other. The sub-pad portion 202 is electrically connected to the gate 209 of at least one metal oxide semiconductor (MOS) device, for example, through a conductive plug 210 .

The pad bonding unit 205 is in direct contact with and connected to the top main conductor unit. The top main conductor unit is the main conductor unit 2011 formed in the uppermost metal layer 203 . The bridge pad unit 206 is in direct contact with and connected to the top sub-conductor unit. The top sub-conductor unit is the sub-conductor unit 2021 formed in the uppermost metal layer 203 . The bridge pad unit 206 is in direct contact with and connected to the pad bonding unit 205 . The main pad part 201 and the sub-pad part 202 are respectively located under the pad joining unit 205 and the bridge pad unit 206, and the main pad part 201 and the sub-pad part 202 are not directly connected to each other. A passivation layer 207 is formed on the upper surface of the dielectric layer 204, and part of the passivation layer 207 is formed on part of the top main conductor unit and part of the top sub-conductor unit. Optionally, a polymer layer 208 is formed on the protective layer 207 , and part of the polymer layer 208 is formed on part of the pad bonding unit 205 and the bridge pad unit 206 . As shown in FIG. 2 , the opening range of the protective layer 207 on the main bonding pad portion 201 is larger than the opening range of the protective layer 207 on the sub-bonding pad portion 202 , thereby making the plasma density generated at the sub-bonding pad portion 202 smaller. Low, so that the object under test connected to it, such as the gate 209 of the MOS device, is less damaged by the plasma.

In one embodiment, the surface area of each main conductor unit 2011 is larger than the surface area of each sub-conductor unit 2021. In one embodiment, the ratio between the surface area of the plurality of sub-conductor units 2021 and the surface area of the gate 209 is lower than a predetermined antenna design rule ratio. In one embodiment, the pad bonding unit 205 and the bridge pad unit 206 are formed in a redistribution layer (RDL) located on the main pad part 201 and the sub-pad part 202, and the redistribution layer and The uppermost metal layer 203 is directly connected. In one embodiment, the main conductor unit 2011 and the sub-conductor unit 2021 are made of materials such as, but not limited to, copper or aluminum. In one embodiment, the material of the pad bonding unit 205 and the bridge pad unit 206 is, for example but not limited to, aluminum.

It should be noted that in the process steps of forming the bonding pad structure of the semiconductor element, if the gate of the metal oxide semiconductor element in the semiconductor substrate and part of the bonding pad structure are electrically connected in the corresponding process step, then The preset antenna design specification limits the area ratio of the antenna to the gate formed by the portion of the bonding pad structure formed in this process step, so as to avoid excessive plasma damage to the gate.

3 is a schematic top view showing a semiconductor device having a bonding pad structure that resists plasma damage according to an embodiment of the present invention. In one embodiment, as shown in FIG. 3 , the sub-conductor units 2021 surround the corresponding main conductor unit 2011 formed in the same metal layer 203 . 4 is a schematic top view showing a semiconductor device having a bonding pad structure that resists plasma damage according to another embodiment of the present invention. In another embodiment, as shown in FIG. 4 , the sub-conductor unit 2021 does not surround the corresponding main conductor unit 2011 formed in the same metal layer 203 , but is located in the corresponding main conductor formed in the same metal layer 203 . Outside unit 2011, and has a point-like structure.

5A-5Q illustrate a schematic cross-sectional view of a manufacturing method of a semiconductor device having a bonding pad structure resistant to plasma damage according to an embodiment of the present invention. First, as shown in FIG. 5A , a metal oxide semiconductor device is formed and a dielectric layer 204 is formed using, for example, deposition process steps, and conductive plugs are formed using patterning process steps, such as but not limited to photolithography and etching process steps and deposition process steps. 210 to be coupled to the gate 209 of the MOS device. Next, as shown in FIG. 5B , the dielectric layer 204 is formed using, for example, deposition process steps. Thereafter, as shown in FIG. 5C , patterning process steps such as but not limited to lithography and etching process steps, deposition process steps or electroplating process steps are used to form the main conductor unit 2011 in the metal layer 203 and to form the sub-conductor unit 2021 in the metal layer. 203 in. Next, as shown in FIG. 5D , the dielectric layer 204 is formed using, for example, deposition process steps.

Next, as shown in FIG. 5E , in one embodiment, patterning process steps such as but not limited to photolithography and etching process steps are first used to form narrow via holes 2012a for accommodating the main inter-layer connection unit and the sub-inter-layer connection unit. and 2022a, and then as shown in FIG. 5G, patterning process steps such as but not limited to lithography and etching process steps are used to form wide through holes 2011a and 2021a to accommodate the main conductor unit and the sub-conductor unit. In an alternative embodiment, as shown in FIG. 5F , patterning process steps such as but not limited to lithography and etching process steps may also be used to form wide through holes 2011a and 2021a for accommodating the main conductor unit and the sub-conductor unit. , and then as shown in FIG. 5G , patterning process steps such as but not limited to lithography and etching process steps are used to form narrow through holes 2012a and 2022a for accommodating the main interlayer connection unit and the sub-interlayer connection unit.

Next, as shown in FIG. 5H , the main interlayer connection unit 2012 and the sub-interlayer connection unit 2022 are respectively formed in the narrow through holes 2012a and 2022a using, for example, a deposition process step or an electroplating process step. The body unit 2011 and the sub-conductor unit 2021 are formed in the wide through holes 2011a and 2021a to respectively form the main conductor unit 2011 and the sub-conductor unit 2021 in the metal layer 203, and use chemical mechanical polishing process steps to form main inter-layer connection units respectively. 2012 and sub-layer connection unit 2022 in the dielectric layer 204 . Thereafter, as shown in FIG. 5I , the dielectric layer 204 is formed using, for example, deposition process steps.

Next, as shown in FIG. 5J , in one embodiment, patterning process steps such as but not limited to photolithography and etching process steps are first used to form narrow via holes 2012a for accommodating the main inter-layer connection unit and the sub-inter-layer connection unit. and 2022a, and then as shown in FIG. 5L , patterning process steps such as but not limited to lithography and etching process steps are used to form wide through holes 2011a and 2021a for accommodating the main conductor unit and the sub-conductor unit. In an alternative embodiment, as shown in FIG. 5K , patterning process steps such as but not limited to lithography and etching process steps may also be used to form wide through holes 2011a and 2021a for accommodating the main conductor unit and the sub-conductor unit. , and then as shown in FIG. 5L , patterning process steps such as but not limited to lithography and etching process steps are used to form narrow through holes 2012a and 2022a for accommodating the main interlayer connection unit and the sub-interlayer connection unit.

Next, as shown in FIG. 5M , the main interlayer connection unit 2012 and the sub-interlayer connection unit 2022 are formed in the narrow through holes 2012a and 2022a using, for example, deposition process steps and chemical mechanical polishing process steps, and use, for example, deposition process steps or electroplating. The process steps are to form the main conductor unit 2011 and the sub-conductor unit 2021 in the wide through holes 2011a and 2021a respectively, so as to form the main conductor unit 2011 and the sub-conductor unit 2021 in the metal layer 203 respectively, and to form the main inter-layer connection unit 2012 and the sub-conductor unit 2021 respectively. The inter-sub-layer connection unit 2022 is in the dielectric layer 204 .

Thereafter, the above-mentioned steps of FIGS. 5I to 5M are repeated, and as shown in FIG. 5N , the main bonding pad portion 201 and the sub-bonding pad portion 202 are formed. The main bonding pad portion 201 includes a plurality of corresponding metal layers 203 formed in the metal layers 203 . A main conductor unit 2011 and a plurality of main interlayer connection units 2012 correspondingly formed in a plurality of dielectric layers 204, wherein the plurality of main interlayer connection units 2012 are electrically connected to the plurality of main conductor units 2011, so that the plurality of main conductor units 2011 are electrically connected to each other. The body units 2011 are electrically connected to each other, wherein the sub-pad portion 202 includes a plurality of sub-conductor units 2021 correspondingly formed in a plurality of metal layers 203 and a plurality of sub-layer connection units 2022 correspondingly formed in a plurality of dielectric layers 204, wherein The plurality of inter-layer connection units 2022 are electrically connected to the plurality of sub-conductor units 2021 correspondingly, so that the plurality of sub-conductor units 2021 are electrically connected to each other, and the sub-pad portion 202 is electrically connected to the gate 209 of at least one MOS device.

Next, as shown in FIG. 5O , a protective layer 207 is formed on the dielectric layer 204 and partially on the top main conductor unit and the top sub-conductor unit using, for example, deposition process steps. Next, as shown in FIG. 5P , a pad bonding unit 205 is formed on the protective layer 207 and partially formed on the top main conductor unit, and a bridge pad unit 206 is formed on the protective layer 207 and partially formed on the top sub-conductor unit. , so that the pad bonding unit 205 is in direct contact with and connected to the top main conductor unit, where the top main conductor unit is the main conductor unit 2011 formed in the uppermost metal layer 203, and to bridge the pad unit 206 with the top sub-conductor unit Direct contact and connection, wherein the top sub-conductor unit is the sub-conductor unit 2021 formed in the uppermost metal layer 203.

The bridge pad unit 206 is in direct contact with and connected to the pad bonding unit 205 . The main pad part 201 and the sub-pad part 202 are respectively located under the pad joining unit 205 and the bridge pad unit 206, and the main pad part 201 and the sub-pad part 202 are not directly connected to each other. In one embodiment, the pad bonding unit 205 and the bridge pad unit 206 are formed in a redistribution layer (RDL) located on the main pad part 201 and the sub-pad part 202, and the redistribution layer and The uppermost metal layer 203 is directly connected. In one embodiment, the main conductor unit 2011 and the sub-conductor unit 2021 are made of materials such as, but not limited to, copper or aluminum. In one embodiment, the material of the pad bonding unit 205 and the bridge pad unit 206 is, for example but not limited to, aluminum. In one embodiment, the pad bonding unit 205 and the bridge pad unit 206 may be formed using electroplating process steps and lithography process steps. Therefore, plasma damage can be significantly reduced by utilizing electroplating process steps and connecting the main pad portion 201 and the sub-pad portion 202 only through the pad bonding unit 205 and the bridge pad unit 206 .

Thereafter, as shown in FIG. 5Q , a polymer layer 208 is selectively formed on the protective layer 207 using, for example, a deposition process step, and is partially formed on a portion of the pad bonding unit 205 and the bridge pad unit 206 .

As mentioned above, the present invention uses electroplating process steps to form the pad bonding unit 205 and the bridge pad unit 206, and the main pad part 201 and the sub-pad part 202 are only connected by the pad bonding unit 205 and the bridge pad unit. 206 joint, which can significantly reduce plasma damage.

The present invention has been described above with reference to the preferred embodiments. However, the above description is only to make it easy for those skilled in the art to understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Within the same spirit of the present invention, various equivalent changes may be conceived by those skilled in the art. For example, without affecting the main characteristics of the component, other process steps or structures can be added, such as lightly doped drain regions; for another example, lithography technology is not limited to photomask technology, but can also include electron beam lithography technology. All these can be derived by analogy based on the teachings of the present invention. In addition, each of the described embodiments is not limited to being used alone, but can also be used in combination, for example, but not limited to, the two embodiments are used together. Accordingly, the scope of the present invention is intended to cover the above and all other equivalent changes. In addition, any implementation form of the present invention may not necessarily achieve all the objects or advantages, and therefore, any of the claims shall not be limited thereto.

Claims (18)

1. A semiconductor component with a pad structure that resists plasma damage, including: A main bonding pad portion includes a plurality of main conductor units correspondingly formed in a plurality of metal layers and a plurality of main interlayer connection units correspondingly formed in a plurality of dielectric layers, wherein a plurality of the main interlayer connection units corresponds to electrically connecting a plurality of the main conductor units, so that a plurality of the main conductor units are electrically connected to each other; A sub-pad part includes a plurality of sub-conductor units correspondingly formed in a plurality of the metal layers and a plurality of sub-layer connection units correspondingly formed in a plurality of the dielectric layers, wherein the plurality of the sub-layer connection units correspond to Electrically connect a plurality of the sub-conductor units so that the plurality of sub-conductor units are electrically connected to each other, and the sub-pad portion is electrically connected to the gate of at least one metal oxide semiconductor device; A pad bonding unit is in direct contact with and connected to a top main conductor unit, wherein the top main conductor unit is the main conductor unit formed in the uppermost metal layer; and A bridge pad unit is in direct contact with and connected to a top sub-conductor unit, wherein the top sub-conductor unit is the sub-conductor unit formed in the uppermost metal layer; The bridging pad unit is in direct contact with and connected to the pad joining unit; The main bonding pad portion and the sub-bonding pad portion are respectively located under the bonding pad joining unit and the bridge bonding pad unit, and the main bonding pad portion and the sub-bonding pad portion are not directly connected to each other. 2. The semiconductor device with a bonding pad structure resistant to plasma damage as claimed in claim 1, wherein the sub-conductor unit surrounds the corresponding main conductor unit formed in the same metal layer. 3. The semiconductor component with a bonding pad structure that resists plasma damage as claimed in claim 1, wherein the sub-conductor unit does not surround the corresponding main conductor unit formed in the same metal layer, but is formed on Outside the corresponding main conductor unit in the same metal layer, it has a point-like structure. 4. The semiconductor device with a bonding pad structure resistant to plasma damage as claimed in claim 1, wherein the surface area of each main conductor unit is greater than the surface area of each sub-conductor unit. 5. The semiconductor component with a pad structure resistant to plasma damage as claimed in claim 1, wherein the ratio between the surface area of the sub-conductor units and the surface area of the gate is lower than a preset antenna design specification Proportion. 6. The semiconductor component with a bonding pad structure resistant to plasma damage as claimed in claim 1, wherein the bonding pad joining unit and the bridge bonding pad unit are formed between the main bonding pad portion and the sub-bonding pad portion. in a redistribution layer on the top, and the redistribution layer is directly connected to the uppermost metal layer. 7. The semiconductor component with a bonding pad structure resistant to plasma damage as claimed in claim 1, wherein the main conductor unit and the sub-conductor unit are made of copper or aluminum. 8. The semiconductor component with a bonding pad structure resistant to plasma damage as claimed in claim 1, wherein the bonding pad joining unit and the bridge bonding pad unit are made of aluminum. 9. The semiconductor component with a bonding pad structure resistant to plasma damage as claimed in claim 1, wherein the bridge bonding pad unit and the bonding pad joining unit are formed using electroplating process steps. 10. A method of manufacturing a semiconductor component with a bonding pad structure that is resistant to plasma damage, including: A patterning process step is used to form a main pad portion and a sub-pad portion, wherein the main pad portion includes a plurality of main conductor units correspondingly formed in a plurality of metal layers and a corresponding plurality of dielectric layers. a plurality of main inter-layer connection units, wherein a plurality of the main inter-layer connection units are electrically connected to a plurality of the main conductor units, so that the plurality of main conductor units are electrically connected to each other, wherein the sub-bonding pad portion includes a correspondingly formed A plurality of sub-conductor units in a plurality of the metal layers and a plurality of inter-layer connection units formed in a plurality of the dielectric layers, wherein the plurality of the sub-layer connection units are electrically connected to a plurality of the sub-conductor units, A plurality of the sub-conductor units are electrically connected to each other, and the sub-pad portion is electrically connected to the gate of at least one MOS element; Forming a pad bonding unit such that the bonding pad bonding unit directly contacts and connects with a top main conductor unit, wherein the top main conductor unit is the main conductor unit formed in the uppermost metal layer; and Forming a bridge pad unit such that the bridge pad unit is in direct contact with and connected to a top sub-conductor unit, wherein the top sub-conductor unit is the sub-conductor unit formed in the uppermost metal layer; The bridging pad unit is in direct contact with and connected to the pad joining unit; The main bonding pad portion and the sub-bonding pad portion are respectively located under the bonding pad joining unit and the bridge bonding pad unit, and the main bonding pad portion and the sub-bonding pad portion are not directly connected to each other. 11. The method of manufacturing a semiconductor component with a bonding pad structure resistant to plasma damage as claimed in claim 10, wherein the sub-conductor unit surrounds the corresponding main conductor unit formed in the same metal layer. 12. The manufacturing method of a semiconductor component with a bonding pad structure resistant to plasma damage as claimed in claim 10, wherein the sub-conductor unit does not surround the corresponding main conductor unit formed in the same metal layer, but It is located outside the corresponding main conductor unit formed in the same metal layer and has a point-like structure. 13. The method of manufacturing a semiconductor component with a bonding pad structure resistant to plasma damage as claimed in claim 10, wherein the surface area of each main conductor unit is greater than the surface area of each sub-conductor unit. 14. The method for manufacturing a semiconductor device with a bonding pad structure that is resistant to plasma damage as claimed in claim 10, wherein the ratio between the surface area of the plurality of sub-conductor units and the surface area of the gate electrode is lower than a preset value. Antenna design specification proportions. 15. The method of manufacturing a semiconductor component with a bonding pad structure resistant to plasma damage as claimed in claim 10, wherein the bonding pad bonding unit and the bridge bonding pad unit are formed between the main bonding pad portion and the sub-bonding pad. In a redistribution layer on the solder pad part, and the redistribution layer is directly connected to the uppermost metal layer. 16. The method of manufacturing a semiconductor component with a bonding pad structure resistant to plasma damage as claimed in claim 10, wherein the main conductor unit and the sub-conductor unit are made of copper or aluminum. 17. The method of manufacturing a semiconductor component with a bonding pad structure resistant to plasma damage as claimed in claim 10, wherein the bonding pad joining unit and the bridge bonding pad unit are made of aluminum. 18. The method of manufacturing a semiconductor component with a bonding pad structure resistant to plasma damage as claimed in claim 10, wherein the bridge bonding pad unit and the bonding pad joining unit are formed using electroplating process steps.