CN117410306A - High-voltage light-emitting chip and manufacturing method thereof, display device - Google Patents

Abstract

Embodiments of the present application provide a high-voltage light-emitting chip, a manufacturing method thereof, and a display device. The high-voltage light-emitting chip includes: a substrate; a plurality of sub-chip structures, which are arranged on the substrate at intervals in sequence. Between adjacent sub-chip structures, An isolation channel is formed between them; an insulating layer is provided on the substrate, the insulating layer covers the multiple sub-chip structures and fills the isolation channel, and the side of the insulating layer away from the substrate A plurality of first via holes are provided on the surface; a series electrode layer is provided on the side surface of the insulating layer away from the substrate, the series electrode layer includes at least one series electrode structure, and two adjacent sub-chip structures pass through One of the series electrode structures is connected in series, and the series electrode structure is electrically connected to the sub-chip structure through the first via hole; a reflective layer is provided on the substrate, and the reflective layer covers the insulating layer and The series electrode layer.

Description

High-voltage light-emitting chip and manufacturing method thereof, display device

Technical field

The present application relates to the field of optoelectronic display technology, and specifically to a high-voltage light-emitting chip, a manufacturing method thereof, and a display device.

Background technique

A high-voltage LED chip is a light-emitting chip that uses a light-emitting diode (LED) as a light source and is suitable for direct high-voltage driving. In related technologies, a flip-chip high-voltage LED chip is provided with a reflective layer on its surface; however, the reflective layer is prone to cracks, and water vapor in the environment may invade along the cracks, causing chip leakage and shortening the service life of the chip.

Contents of the invention

Embodiments of the present application provide a high-voltage light-emitting chip, a manufacturing method thereof, and a display device, which can eliminate or at least reduce the risk of cracks in the reflective layer, improve the reliability of the chip, and ensure the service life of the chip.

In a first aspect, embodiments of the present application provide a high-voltage light-emitting chip, including: a substrate; a plurality of sub-chip structures, which are arranged on the substrate at intervals, and isolation channels are formed between adjacent sub-chip structures; and an insulating layer. , disposed on the substrate, the insulating layer covers the plurality of sub-chip structures and fills the isolation trench, and a plurality of first passes are provided on a surface of the insulating layer away from the substrate. hole; a series electrode layer, which is provided on a side surface of the insulating layer away from the substrate, the series electrode layer includes at least one series electrode structure, and two adjacent sub-chip structures are connected in series through one of the series electrode structures, The series electrode structure is electrically connected to the sub-chip structure through the first via hole; a reflective layer is provided on the substrate, and the reflective layer covers the insulating layer and the series electrode layer.

In some embodiments, the reflective layer is provided with a plurality of second via holes, the insulating layer is provided with a plurality of third via holes, the plurality of second via holes and the plurality of third via holes are The number of holes is equal and connected in a one-to-one correspondence; the high-voltage light-emitting chip includes a plurality of external electrodes, the plurality of external electrodes are respectively provided on the reflective layer, and the external electrodes pass through the second via holes in sequence and the third via hole to be electrically connected to the sub-chip structure.

In some embodiments, the reflective layer is a planarization layer, and the plurality of external electrodes are respectively disposed on a side surface of the reflective layer away from the substrate.

In some embodiments, the high-voltage light-emitting chip includes an ohmic contact layer, the ohmic contact layer is disposed between the sub-chip structure and the insulating layer, and is disposed corresponding to the third via hole, and the external connection layer The electrode is in contact with the ohmic contact layer through the second via hole and the third via hole.

In some embodiments, the sub-chip structure includes an N-type semiconductor layer, an active layer and a P-type semiconductor layer that are stacked in sequence, the N-type semiconductor layer is in contact with the substrate, and the P-type semiconductor layer is in contact with the substrate. contact with the insulation layer.

In some embodiments, an isolation channel is formed between two adjacent sub-chip structures, and an orthographic projection of a series electrode structure connecting the two adjacent sub-chip structures on the substrate covers the isolation channel.

In some embodiments, the orthographic projection of the series electrode layer on the substrate partially overlaps the orthographic projection of the sub-chip structure connected in series on the substrate.

In a second aspect, embodiments of the present application provide a method for manufacturing a high-voltage light-emitting chip, which includes: forming a plurality of sub-chip structures at intervals on a substrate, and forming isolation channels between adjacent sub-chip structures; An insulating layer is formed on the side on which the plurality of sub-chip structures are arranged. The insulating layer covers the plurality of sub-chip structures and fills the isolation trench. The side surface of the insulating layer away from the substrate A plurality of first via holes are provided; a series electrode layer is formed on a side surface of the insulating layer away from the substrate, the series electrode layer includes at least one series electrode structure, and the series electrode structure passes through the third A via hole is electrically connected to the sub-chip structure; a reflective layer is formed on the side of the substrate where the insulating layer is provided, and the reflective layer covers the insulating layer and the series electrode layer.

In some embodiments, forming an insulating layer on the side of the substrate on which the plurality of sub-chip structures are provided includes: forming a third layer on the side of the substrate on which the plurality of sub-chip structures are provided. An insulating dielectric layer, the first insulating dielectric layer covers the plurality of sub-chip structures; the first insulating dielectric layer is planarized and drilled to form the insulating layer.

In a third aspect, embodiments of the present application provide a display device, including the high-voltage light-emitting chip provided in any of the above embodiments.

In the embodiment of the present application, an insulating layer is provided between multiple sub-chip structures and the series electrode layer, so that the surface on the side of the series electrode structure away from the insulating layer is a planar area, so that the part of the reflective layer formed on the surface of the series electrode structure is not A step difference will be formed, which can eliminate or at least reduce the risk of cracks in the reflective layer, improve the reliability of the high-voltage light-emitting chip and ensure the service life of the high-voltage light-emitting chip.

Description of the drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

Figure 1 is a cross-sectional structural view of a high-voltage light-emitting chip provided by some embodiments of the present application;

Figure 2 is another cross-sectional structural view of a high-voltage light-emitting chip provided by some embodiments of the present application;

Figure 3 is a first process diagram of forming multiple sub-chip structures in the high-voltage light-emitting chip manufacturing method provided by some embodiments of the present application;

Figure 4 is a second process diagram of forming multiple sub-chip structures in the high-voltage light-emitting chip manufacturing method provided by some embodiments of the present application;

Figure 5 is a third process diagram of forming multiple sub-chip structures in the high-voltage light-emitting chip manufacturing method provided by some embodiments of the present application;

Figure 6 is a first process diagram of forming an insulating layer in the manufacturing method of a high-voltage light-emitting chip provided by some embodiments of the present application;

Figure 7 is a second process diagram of forming an insulating layer in the manufacturing method of a high-voltage light-emitting chip provided by some embodiments of the present application;

Figure 8 is a third process diagram of forming an insulating layer in the manufacturing method of a high-voltage light-emitting chip provided by some embodiments of the present application;

FIG. 9 is a process diagram of forming a series electrode layer in the manufacturing method of a high-voltage light-emitting chip provided by some embodiments of the present application.

Description of main component symbols:

10-Substrate, 20-Sub-chip structure, 21-N-type semiconductor layer, 22-Active layer, 23-P-type semiconductor layer, 20'-Epitaxial layer, 30-Insulating layer, 31-First via hole, 32- The third via hole, 30'-first insulating dielectric layer, 301'-filling part, 40-series electrode layer, 41-series electrode structure, 50-reflective layer, 51-second via hole, 60-ohm contact layer, 70-Isolation channel, 80-External electrode.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of protection of this application.

In the description of this application, it needs to be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " The directions or positional relationships indicated by "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are based on the directions shown in the accompanying drawings or positional relationship is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, features defined as “first” and “second” may explicitly or implicitly include one or more of the described features. In the description of this application, "plurality" means two or more than two, unless otherwise explicitly and specifically limited.

"A and/or B" includes the following three combinations: A only, B only, and a combination of A and B.

The use of "suitable for" or "configured to" in this application means open and inclusive language that does not exclude devices that are suitable for or configured to perform additional tasks or steps. Additionally, the use of "based on" is meant to be open and inclusive in that a process, step, calculation or other action "based on" one or more stated conditions or values may in practice be based on additional conditions or beyond the stated values.

In this application, the word "exemplary" is used to mean "serving as an example, illustration, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the present application. In the following description, details are set forth for the purpose of explanation. It will be understood that one of ordinary skill in the art will recognize that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been described in detail to avoid obscuring the description of the application with unnecessary detail. Thus, this application is not intended to be limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and features disclosed herein.

In the related art, a reflective layer is provided on the surface of a flip-chip high-voltage LED chip. However, cracks are prone to occur in the area above the series electrodes in the reflective layer. Water vapor in the environment may invade along the cracks and cause chip leakage, shortening the service life of the chip.

As shown in FIGS. 1 to 2 , firstly, embodiments of the present application provide a high-voltage light-emitting chip that can eliminate or at least reduce the risk of cracks in the reflective layer 50 , improve the reliability of the high-voltage light-emitting chip, and ensure the reliability of the high-voltage light-emitting chip. service life.

The high-voltage light-emitting chip includes a substrate 10, a plurality of sub-chip structures 20, an insulating layer 30, a series electrode layer 40 and a reflective layer 50. The type of the substrate 10 can be determined according to actual needs, and types such as glass substrates, flexible substrates, etc. can be used, which are not limited in the embodiments of the present application. In some embodiments, the substrate 10 may be a sapphire substrate made of sapphire substrate.

The plurality of sub-chip structures 20 are arranged on the substrate 10 in sequence, so that any two sub-chip structures 20 do not contact each other, and an isolation channel 70 is formed between adjacent sub-chip structures 20 . Here, an epitaxial layer 20' can be grown and deposited on the substrate 10, and then a patterning process is used to divide the epitaxial layer 20' to form the plurality of sub-chip structures 20 mentioned above. The number of sub-chip structures 20 can be determined according to actual needs, and can be any number of more than two, which is not limited in the embodiment of the present application. The type of the sub-chip structure 20 can be determined according to actual needs, and can be, for example, an LED light-emitting structure, which is not limited in the embodiments of the present application.

The insulating layer 30 is disposed on the substrate 10 , covers the plurality of sub-chip structures 20 , and fills the isolation trench 70 . A plurality of first via holes 31 are provided on the side surface of the insulating layer 30 away from the substrate 10 . The first via holes 31 penetrate the insulating layer 30 and extend to the surface of the sub-chip structure 20 . Since the isolation trench 70 is filled flat by the insulating layer 30 , the area corresponding to the isolation trench 70 on the upper surface of the insulating layer 30 has no step difference and is a flat area. Correspondingly, the area above the sub-chip structure 20 and the isolation trench are eliminated. The height difference of the area above the track 70; accordingly, a plurality of first via holes 31 can be disposed in the above-mentioned planar area.

Here, the insulating layer 30 may be made of an insulating medium such as silicon oxide or silicon nitride. In some embodiments, the insulating layer 30 may be a planarized layer that has been leveled through planarization or local planarization; based on its planarized structure, naturally, the insulating layer 30 also fills and covers adjacent sub-chips. The isolation channel 70 between the structures 20 makes the surface of the insulating layer 30 farthest away from the substrate 10 be a flat surface. Here, the plurality of first via holes 31 may be opened on the flat surface of the insulating layer 30 .

The series electrode layer 40 is disposed on a side surface of the insulating layer 30 away from the substrate 10. The plurality of sub-chip structures 20 are connected in series through the series electrode layer 40; the series electrode layer 40 is connected to the plurality of first via holes 31 respectively. The sub-chip structures 20 are in contact for electrical connection, that is, the series electrode layers 40 are filled with each first via hole 31 together. The material of the series electrode layer 40 can be determined according to actual needs, and can be formed of conductive materials such as metal, which is not limited in the embodiments of the present application. Since the series electrode layer 40 is formed in the planar area on the upper surface of the insulating layer 30 , different areas of the series electrode layer 40 have consistent height positions, which can eliminate height differences in different areas of the series electrode layer 40 , thereby making the series electrodes The side surface of the layer 40 away from the insulating layer 30 is also a planar area.

Here, the series electrode layer 40 includes at least one series electrode structure 41, and two adjacent sub-chip structures 20 are connected in series through one series electrode structure 41; the series electrode structure 41 is connected to the two connected in series through the two first via holes 31. The sub-chip structures 20 are electrically connected, that is, the series electrode structures 41 fill the two first via holes 31 respectively. As shown in FIG. 2 , when the high-voltage light-emitting chip includes at least three sub-chip structures 20 , the series electrode layer 40 may include at least two series electrode structures 41 . The at least two series electrode structures 41 are spaced apart to maintain isolation. Each series electrode structure 41 is spaced apart to maintain isolation. The electrode structure 41 is used to connect two adjacent sub-chip structures 20 in series; here, the above-mentioned at least two series electrode structures 41 have the same layer arrangement relationship, and can be formed by processing the base material of the series electrode layer 40 using, for example, a patterning process. . Since the side surface of the series electrode layer 40 away from the insulating layer 30 is a planar area, the side surface of the series electrode structure 41 away from the insulating layer 30 is also a planar area, and there is no height difference.

As shown in FIGS. 1 to 2 , the reflective layer 50 is disposed on the substrate 10 and covers the insulating layer 30 and the series electrode layer 40 . In other words, the reflective layer 50 covers the area on the insulating layer 30 that is not blocked by the series electrode structures 41 and the outer surface of each series electrode structure 41 . The reflective layer 50 can be made of a material that has a higher reflectivity for the luminescence of the sub-chip structure 20 and has a better reflection effect for the luminescence of the sub-chip structure 20, correspondingly improving the light utilization rate and luminous brightness of the high-voltage light-emitting chip; The structure of the reflective layer 50 can be determined according to actual needs, and can be of a type such as a distributed Bragg reflection (distributed Bragg reflection, DBR for short), metal mirror layer, etc., which are not limited in the embodiments of the present application.

Since the surface of the series electrode structure 41 away from the insulating layer 30 is a planar area and there is no step difference in the planar area, there will be no step difference in the portion of the reflective layer 50 formed on the surface of the series electrode structure 41 . In this way, it is possible to avoid stress concentration in the reflective layer 50 due to step differences and the resulting cracks in the area of the reflective layer 50 above the series electrode structure 41 , thereby avoiding the risk of exposure and leakage of the series electrode structure 41 due to cracks. Compared with related technologies, the high-voltage light-emitting chip provided by the embodiments of the present application can eliminate or at least reduce the risk of cracks in the reflective layer 50 , improve the reliability of the high-voltage light-emitting chip, and ensure the service life of the high-voltage light-emitting chip.

In some embodiments, the reflective layer 50 may be provided with a plurality of second via holes 51 , and the insulating layer 30 may be provided with a plurality of third via holes 32 ; a plurality of second via holes 51 and a plurality of third via holes 32 The number of holes 32 is equal and connected in a one-to-one correspondence, so that each second via hole 51 and a third via hole 32 are connected to form an integral via hole, and the integral via hole penetrates the reflective layer 50 and the insulating layer 30 in sequence. Here, the high-voltage light-emitting chip may include a plurality of external electrodes 80. The plurality of external electrodes 80 are respectively disposed on the reflective layer 50; each external electrode 80 is connected to the sub-chip structure through a second via hole 51 and a third via hole 32 in turn. 20 is electrically connected, that is, the external electrode 80 is filled with a second via hole 51 and a third via hole 32 that are connected in sequence. The number of external electrodes 80 can be determined according to actual needs. More commonly, there can be two, serving as external positive electrodes and external negative electrodes respectively. This is not limited in the embodiment of the present application. By providing the external electrode 80, the high-voltage light-emitting chip can be electrically connected to an external circuit, thereby increasing the driving voltage required by the high-voltage light-emitting chip.

The structural shape of the reflective layer 50 can be determined according to actual needs, and is not limited in the embodiments of the present application. In some examples, the reflective layer 50 may be a planarization layer, and a plurality of external electrodes 80 are respectively disposed on a side surface of the reflective layer 50 away from the substrate 10 . Here, the reflective layer 50 can be made of an insulating material, which has a high reflectivity for the light emitted by the sub-chip structure 20; and the reflective layer 50 has been planarized or partially planarized to become a leveled planarization layer. Based on its planarized structure, when the series electrode layer 40 includes a plurality of series electrode structures 41 arranged at intervals to maintain isolation, the reflective layer 50 also fills and covers the trenches between adjacent sub-chip structures 20 so that the reflective layer The side surface of 50 that is farthest from the substrate 10 is a planar area with no height difference. In this way, a plurality of external electrodes 80 can be formed on the planar area without forming step differences, so that the high-voltage light-emitting chip has a relatively neat and consistent appearance structure.

In some examples, the high-voltage light-emitting chip may include an ohmic contact layer 60 disposed between the sub-chip structure 20 and the insulating layer 30; here, the ohmic contact layer 60 and the third via hole 32 are disposed correspondingly, and the external electrode 80 It is electrically connected to the ohmic contact layer 60 through the second via hole 51 and the third via hole 32 . By providing the ohmic contact layer 60 , the external electrode 80 can be better conductively connected to the electrode terminal of the corresponding sub-chip structure 20 . The material of the ohmic contact layer 60 can be determined according to actual needs, and can be made of a transparent conductive medium such as indium tin oxide (ITO), which is not limited in the embodiments of the present application.

The structure of the sub-chip structure 20 can be determined according to actual needs, and is not limited in this embodiment of the present application. In some embodiments, the sub-chip structure 20 may include an N-type semiconductor layer 21, an active layer 22 and a P-type semiconductor layer 23 that are stacked in sequence. The N-type semiconductor layer 21 is in contact with the substrate 10 , and the P-type semiconductor layer 23 is in contact with the insulating layer 30 . The materials of the N-type semiconductor layer 21 and the P-type semiconductor layer 23 can be determined according to actual needs, and semiconductor material types such as gallium nitride (GaN) can be used, which is not limited in the embodiments of the present application. In some examples, in two sub-chip structures 20 arranged adjacently and connected in series, one end of the series electrode structure 41 can pass through a first via hole 31 and then be electrically connected to the N-type semiconductor layer 21 of one of the sub-chip structures 20 . The other end can pass through another first via hole 31 and then be electrically connected to the P-type semiconductor layer 23 of another sub-chip structure 20 .

In some embodiments, the orthographic projection of the series electrode layer 40 on the substrate 10 can cover the corresponding isolation channel 70 , so that the series electrode layer 40 can better extend to contact the two sub-chips located on both sides of the isolation channel 70 structure 20, thereby achieving the purpose of series connection between the two sub-chip structures 20.

In some embodiments, the orthographic projection of the series electrode layer 40 on the substrate 10 may partially overlap with the orthographic projection of the sub-chip structure 20 connected in series by the series electrode layer 40 on the substrate 10 . Through the above arrangement, the series electrode layer 40 can be extended to the area where the sub-chip structures 20 that need to be connected in series are located, so as to make contact connections through the first via holes 31 .

In a second aspect, embodiments of the present application provide a method for manufacturing a high-voltage light-emitting chip. The manufacturing method includes S10 to S40 for manufacturing the high-voltage light-emitting chip provided in the above embodiment.

S10: As shown in FIGS. 3 to 5 , multiple sub-chip structures 20 are formed on the substrate 10 at intervals, and isolation channels 70 are formed between adjacent sub-chip structures 20 .

In some embodiments, an epitaxial layer 20' can be formed on the substrate 10 as shown in Figure 3, and then patterned as shown in Figures 4 to 5 to form multiple sub-chips arranged at intervals. Structure 20. Here, the epitaxial layer 20' of a desired thickness may be formed on the substrate 10 through a semiconductor process such as growth deposition. Here, the epitaxial layer 20' can be divided through material removal processes such as film etching, laser removal, etc. to obtain multiple sub-chip structures 20 to achieve the purpose of patterning the epitaxial layer 20'; in this process, adjacent The material in the area between the two sub-chip structures 20 is removed, and the area on the substrate 10 between the two adjacent sub-chip structures 20 is exposed, so that an isolation channel 70 is formed between the adjacent sub-chip structures 20 .

S20: As shown in FIGS. 6 to 8 , an insulating layer 30 is formed on the side of the substrate 10 on which multiple sub-chip structures 20 are provided. The insulating layer 30 covers the multiple sub-chip structures 20 and fills the isolation trench 70. The insulating layer A plurality of first via holes 31 are provided on the side surface of 30 away from the substrate 10 .

In some embodiments, the insulating layer 30 may be a planarized layer that has been leveled through planarization or local planarization; based on its planarized structure, naturally, the insulating layer 30 also fills and covers adjacent sub-chips. The isolation channel 70 between the structures 20 makes the surface of the insulating layer 30 farthest away from the substrate 10 be a flat surface.

S30: As shown in FIG. 9 , a series electrode layer 40 is formed on the surface of the insulating layer 30 away from the substrate 10 . The series electrode layer 40 includes at least one series electrode structure 41 , and the series electrode structure 41 is electrically connected to the sub-chip structure 20 through the first via hole 31 .

S40: As shown in FIG. 1 or 2 , a reflective layer 50 is formed on the side of the substrate 10 on which the insulating layer 30 is provided. The reflective layer 50 covers the insulating layer 30 and the series electrode layer 40 .

Compared with related technologies, the risk of cracks in the reflective layer 50 of the high-voltage light-emitting chip produced by the manufacturing method provided by the embodiment of the present application is lower, which can improve the reliability of the high-voltage light-emitting chip and ensure the service life of the high-voltage light-emitting chip. .

In some embodiments, S20 may include S201˜S202.

S201: As shown in FIG. 6 , a first insulating dielectric layer 30 ′ is formed on the side of the substrate 10 on which the plurality of sub-chip structures 20 are disposed. The first insulating dielectric layer 30 ′ covers the plurality of sub-chip structures 20 . Naturally, the first insulating dielectric layer 30' also fills and covers the isolation trenches 70 between adjacent sub-chip structures 20; the area in the first insulating dielectric layer 30' that is filled and covers the isolation trenches 70 is called a filling portion 301 ', then the side surface of the filling portion 301' away from the substrate 10 is located on the side of the sub-chip structure 20 away from the substrate 10, so that the filling portion 301' is filled to a level higher than the top surface of the sub-chip structure 20. Here, the first insulating dielectric layer 30' may be an insulating dielectric such as silicon oxide or silicon nitride. In some examples, the first insulating dielectric layer 30' may be deposited on the entire side of the substrate 10 on which the plurality of sub-chip structures 20 are provided.

S202: As shown in FIGS. 7 to 8 , the first insulating dielectric layer 30 ′ is planarized and hole-opened to form an insulating layer 30 . FIG. 7 shows the planarization process of the first insulating dielectric layer 30 ′, and FIG. 8 shows the hole opening process of the first insulating dielectric layer 30 ′. Here, the planarization may be an entire surface planarization or a local planarization process, which is not limited in the embodiments of the present application. Specifically, material removal processes such as film etching and laser removal can be used to eliminate the surface height difference of the first insulating dielectric layer 30 ′, so that the surface on the side of the first insulating dielectric layer 30 ′ away from the substrate 10 has a consistent height. and then open a plurality of first via holes 31 on the planarized first insulating dielectric layer 30', thereby obtaining the insulating layer 30.

In a third aspect, embodiments of the present application provide a display device, which includes the high-voltage light-emitting chip provided in any of the above embodiments. The type of the display device can be determined according to actual needs, and can be, for example, a television, a monitor, a smart terminal, or other products with display functions or components thereof, which are not limited in the embodiments of the present application.

The high-voltage light-emitting chip, its manufacturing method, and the display device provided by the embodiments of the present application have been introduced in detail. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only for assistance. Understand the methods and core ideas of this application; at the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the ideas of this application. In summary, the contents of this specification should not understood as a limitation on this application.

Claims (10)

1. A high-voltage light-emitting chip, characterized by including: substrate; A plurality of sub-chip structures are arranged on the substrate at intervals in sequence, and isolation channels are formed between adjacent sub-chip structures; An insulating layer is provided on the substrate. The insulating layer covers the plurality of sub-chip structures and fills the isolation trench. A plurality of third insulating layers are provided on a surface of the insulating layer away from the substrate. a via hole; A series electrode layer is provided on a side surface of the insulating layer away from the substrate. The series electrode layer includes at least one series electrode structure. Two adjacent sub-chip structures are connected in series through one of the series electrode structures. The series electrode structure is electrically connected to the sub-chip structure through the first via hole; A reflective layer is provided on the substrate, and the reflective layer covers the insulating layer and the series electrode layer. 2. The high-voltage light-emitting chip according to claim 1, wherein the reflective layer is provided with a plurality of second via holes, the insulating layer is provided with a plurality of third via holes, and the plurality of third via holes are provided on the reflective layer. The number of the two via holes and the plurality of third via holes are equal and are connected in a one-to-one correspondence; The high-voltage light-emitting chip includes a plurality of external electrodes, the plurality of external electrodes are respectively arranged on the reflective layer, and the external electrodes are connected to the sub-assembly through the second via hole and the third via hole in sequence. Chip structure electrical connections. 3. The high-voltage light-emitting chip according to claim 2, wherein the reflective layer is a planarization layer, and the plurality of external electrodes are respectively disposed on a side surface of the reflective layer away from the substrate. 4. The high-voltage light-emitting chip according to claim 2, characterized in that the high-voltage light-emitting chip includes an ohmic contact layer, the ohmic contact layer is disposed between the sub-chip structure and the insulating layer, and is in contact with the insulating layer. The third via holes are provided correspondingly, and the external electrode is electrically connected to the ohmic contact layer through the second via hole and the third via hole. 5. The high-voltage light-emitting chip according to claim 1, wherein the sub-chip structure includes an N-type semiconductor layer, an active layer and a P-type semiconductor layer that are stacked in sequence, and the N-type semiconductor layer and the liner are Bottom contact, the P-type semiconductor layer and the insulating layer are in contact. 6. The high-voltage light-emitting chip according to claim 1, characterized in that an isolation channel is formed between two adjacent sub-chip structures, and a series electrode structure connecting the two adjacent sub-chip structures in series is on the substrate. Orthographic projection covers the isolation channel. 7. The high-voltage light-emitting chip according to claim 1, characterized in that the orthographic projection of the series electrode layer on the substrate and the sub-chip structure connected in series by the series electrode layer on the substrate Orthographic projections partially overlap. 8. A method for manufacturing a high-voltage light-emitting chip, which is characterized by comprising: Multiple sub-chip structures are formed on the substrate at intervals, and isolation channels are formed between adjacent sub-chip structures; An insulating layer is formed on one side of the substrate where the plurality of sub-chip structures are provided. The insulating layer covers the plurality of sub-chip structures and fills the isolation trench. The insulating layer is located away from the liner. One side surface of the bottom is provided with a plurality of first via holes; A series electrode layer is formed on a side surface of the insulating layer away from the substrate. The series electrode layer includes at least one series electrode structure. The series electrode structure passes through the first via hole and the sub-chip structure. electrical connection; A reflective layer is formed on the side of the substrate where the insulating layer is provided, and the reflective layer covers the insulating layer and the series electrode layer. 9. The manufacturing method according to claim 8, characterized in that forming an insulating layer on the side of the substrate on which the plurality of sub-chip structures are arranged includes: A first insulating dielectric layer is formed on the side of the substrate on which the plurality of sub-chip structures are disposed, and the first insulating dielectric layer covers the plurality of sub-chip structures; The first insulating dielectric layer is planarized and hole-opened to form the insulating layer. 10. A display device, characterized by comprising the high-voltage light-emitting chip according to any one of claims 1 to 7.