CN117407321A - Read-write request processing method and related device for chip cache - Google Patents
Read-write request processing method and related device for chip cache Download PDFInfo
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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Abstract
The embodiment of the application provides a read-write request processing method and a related device for chip cache. And latching the plurality of write requests, comparing the operation addresses of the first read request with the operation addresses of the latched plurality of write requests, generating a first read response after the target write request which is the same as the operation address of the first read request exists, and triggering a read-write request initiating unit to initiate a new read request. At this time, even if the time intervals of the read request and the write request of the same address are adjacent, the read-write request initiating unit can initiate a new read request. Therefore, the embodiment of the application solves the problem of invalidation of the read request and the write request caused by adjacent time intervals of the read request and the write request of the same address, and is beneficial to improving the operation frequency of the cache of the chip and improving the overall operation frequency of the chip.
Description
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a method and an apparatus for processing a read-write request of a chip cache.
Background
Currently, the chip needs to cache read requests and write requests. However, when the cache bank in the chip caches the write request and the read request of the same address, the time intervals required to satisfy the write request and the read request of the same address cannot be adjacent. If the time intervals of the write request and the read request of the same address are adjacent, the write request and the read request can fail. If the time intervals of the write request and the read request of the same address cannot be adjacent, the operation frequency of the cache chip is affected, and the operation frequency of the chip is further affected.
Disclosure of Invention
The application provides a read-write request processing method and a related device for a chip cache, which are used for realizing that when the time intervals of a write request and a read request of the same address are adjacent, the write request and the read request cannot be invalid, and improving the operation frequency of a cache body and the operation frequency of a chip.
In a first aspect, an embodiment of the present application provides a method for processing a read-write request of a chip cache, where the method includes:
responding to N write requests initiated by a read-write request initiating unit in the chip, and latching the N write requests; each of the N write requests includes an operation address, where N is an integer greater than 2;
in response to receiving a first read request initiated by the read-write request initiating unit, determining a target write request from the N write requests based on an operation address in the first read request and operation addresses in the N write requests, wherein the operation address in the target write request is the same as the operation address in the first read request;
generating a first read response based on the first read request after determining the target write request, the first read response being used to indicate initiation of a second read request;
and sending the first read response to the read-write request initiating unit so that the read-write request initiating unit initiates the second read request.
Optionally, the latching the N write requests includes:
according to the number of the beats and the initiation time of the N write requests, sequentially latching the N write requests, wherein the initiation time of the latched 1 st beat write request is the latest, and the initiation time of the latched N beat write request is the earliest; the latch beats and the operating frequency of the chip are in positive correlation.
Optionally, the determining, in response to receiving the first read request initiated by the read-write request initiating unit, a target write request from the N write requests based on an operation address in the first read request and an operation address in the N write requests includes:
and in response to receiving a first read request initiated by the read-write request initiating unit, comparing the first read request with the N latched write requests in turn, and determining the target write request from the N write requests.
Optionally, the determining the target write request from the N write requests includes:
when the N latched write requests have the same write request with the operation address of the first read request, and the difference value between the initiation time of the write request and the initiation time of the first read request is within a preset difference threshold range, determining the target write request.
Optionally, the determining the target write request from the N write requests includes:
the target write request is matched from among the unlatched write requests and the latched N write requests.
Optionally, the method further comprises:
and when the target write request is not determined, outputting the first read request to a cache body of the chip, and receiving a second read response returned by the cache body, so that the read-write request initiating unit initiates the first read request according to the second read response.
In a second aspect, an embodiment of the present application provides a read-write request processing apparatus for a chip cache, where the apparatus includes:
the write request latching unit is used for latching N write requests initiated by the read-write request initiating unit in response to receiving the N write requests; each of the N write requests includes an operation address, where N is an integer greater than 2;
a read-write request address comparing unit, configured to determine, in response to receiving a first read request initiated by the read-write request initiating unit, a target write request from the N write requests based on an operation address in the first read request and operation addresses in the N write requests, where the operation address in the target write request is the same as the operation address in the first read request;
a write-read request output unit, configured to generate a first read response based on the first read request after determining the target write request, where the first read response is used to indicate to initiate a second read request;
and the read response output unit is used for sending the first read response to the read-write request initiating unit so as to enable the read-write request initiating unit to initiate the second read request.
Optionally, the write request latching unit is specifically configured to:
according to the number of the beats and the initiation time of the N write requests, sequentially latching the N write requests, wherein the initiation time of the latched 1 st beat write request is the latest, and the initiation time of the latched N beat write request is the earliest; the latch beats and the operating frequency of the chip are in positive correlation.
In a third aspect, embodiments of the present application provide a chip including a memory and a processor;
the memory is coupled with the processor;
the memory stores program instructions that, when executed by the processor, cause the chip to perform the method of any of the first aspects.
In a fourth aspect, embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored, which program, when being executed by a processor, implements a method according to any of the first aspects.
The embodiment of the application provides a read-write request processing method and a related device for chip cache. And latching the plurality of write requests, comparing the operation addresses of the first read request and the latched plurality of write requests, and generating a first read response to trigger the read-write request initiating unit to initiate a new read request after the target request with the same operation address as the first read request exists. At this time, even if the time intervals of the read request and the write request of the same address are adjacent, the read-write request initiating unit can initiate a new read request. Therefore, the embodiment of the application does not need to have adjacent time intervals of the cache read request and the write request, solves the problem of invalidation of the read request and the write request caused by adjacent time intervals of the read request and the write request of the same address, and is beneficial to improving the operation frequency of the cache of the chip and the overall operation frequency of the chip.
Drawings
Fig. 1 is an application scenario diagram of a read-write request processing method for a chip cache provided in an embodiment of the present application;
fig. 2 is a flowchart of a method for processing a read-write request of a chip cache according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a latch method according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a comparison method according to an embodiment of the present application;
FIG. 5A is a flowchart of another method for processing a read/write request of a chip cache according to an embodiment of the present application;
fig. 5B is a schematic structural diagram of a cache timing optimization unit in a chip according to an embodiment of the present application;
fig. 6 is a schematic diagram of a read-write request address comparing unit 502 according to an embodiment of the present application;
fig. 7 is a schematic diagram of the write-read request output unit 503;
FIG. 8 is a schematic diagram of the logic structure of the read response output unit 504;
fig. 9 is a schematic structural diagram of a read-write request processing device for chip cache according to an embodiment of the present application.
Detailed Description
At present, the requirements of various fields on the operating frequency of the chip are higher and higher, and the requirements on the operating frequency of the logic unit in the chip and the operating frequency of the cache in the chip are also increased gradually. In order to meet the requirements of various fields on the operating frequency of the chip, the overall operating frequency of the chip needs to be improved.
Currently, the chip needs to cache read requests and write requests. However, when the cache bank in the chip caches the write request and the read request of the same address, the time intervals required to satisfy the write request and the read request of the same address cannot be adjacent. If the time intervals of the write request and the read request of the same address are adjacent, the write request and the read request can fail. If the time intervals of the write request and the read request of the same address cannot be adjacent, the operation frequency of the cache chip is affected, and the overall operation frequency of the chip is further affected.
In view of the above problems, embodiments of the present application provide a method for processing a read-write request of a chip cache. And latching the plurality of write requests, comparing the operation addresses of the first read request and the latched plurality of write requests, and generating a first read response after the target request which is the same as the operation address of the first read request exists, and triggering a read-write request initiating unit to initiate a new read request. At this time, even if the time intervals of the read request and the write request of the same address are adjacent, the read-write request initiating unit can initiate a new read request. Therefore, the embodiment of the application does not need the requirement that the time intervals of the read request and the write request of the cache body are adjacent, solves the problem of invalidation of the read request and the write request caused by the adjacent time intervals of the read request and the write request of the same address, and is beneficial to improving the operation frequency of the cache of the chip and the overall operation frequency of the chip.
In order to better explain the read-write request processing method of the chip cache provided by the embodiment of the application, the following detailed and complete description is made by referring to the accompanying drawings.
First, an application scenario of the embodiment of the present application is described.
Referring to fig. 1, an application scenario diagram of a read-write request processing method for a chip cache is provided in an embodiment of the present application. The chip comprises a read-write request initiating unit, a read-write request processing unit (also called a cache time sequence optimizing unit) cached by the chip and a cache body.
Wherein the read-write request initiating unit initiates the write request and the read request according to a preset time interval. The buffer time sequence optimizing unit processes the write request and the read request initiated by the read-write request unit, and writes the write request and the read request meeting the requirements into the buffer body. And after receiving the write request and the read request, the cache body generates a read response, and returns the read response to the read-write request initiating unit. The read-write request initiating unit initiates the read request received by the cache body to the application needing the read request.
Referring to fig. 2, a flowchart of a method for processing a read-write request of a chip cache according to an embodiment of the present application is provided, where the method applies a cache timing optimization unit in an application scenario shown in fig. 1. The method specifically comprises the following steps:
s21: and latching N write requests initiated by a read-write request initiating unit in the chip in response to receiving the N write requests.
A read-write request initiating unit of the chip initiates a write request based on a preset time interval. In this embodiment of the present application, after receiving a write request initiated by a read-write request initiating unit based on a preset time interval, a cache timing optimization unit of the chip sequentially latches N write requests as W1, W2, … …, and WN, respectively. Wherein N is an integer greater than 2. W1, W2, … …, WN are used to represent consecutive write requests of different time intervals, i.e., W1 and W2 are different write requests of adjacent time intervals, and W2 and W3 are different write requests of adjacent time intervals, … …. Thus, N is also known as the latch beats.
Alternatively, the user may configure the value of N.
However, it is considered that if the number N is too large, the latched write requests will affect the memory resources of the chip, and if the number N is too small, the latched write requests cannot acquire the correct relationship of the read-write requests. Based on the above, the method can enable N to have positive correlation with the chip operation frequency, and the higher the chip operation frequency is, the larger the value of N is.
Furthermore, in addition to the chip operating frequency, the clock frequency may also be considered. The clock frequency refers to the frequency at which the read-write request initiating unit initiates a read request. The higher the operating frequency of the chip, and the higher the clock frequency, the greater the value of N.
In one possible implementation, the N write requests may be latched according to the data flow direction. Referring to fig. 3, a schematic diagram of a latch method according to an embodiment of the present application is provided, in which, according to a method of writing request data stream, a write request_1 beat is latched in a latch unit 1, a write request_2 beat is latched in a latch unit 2, and a write request_n beat is latched in a latch unit N. Specifically, W1 is latched as write request_1 beat, W1 is latched as write request_2 beat, … …, and WN is latched as write request_n beat.
In addition, the N write requests latched by the embodiment of the present application include operation addresses, 1 write request includes 1 operation address, and N write requests include N operation addresses. Thus, the read request need only be compared to the latched write request's operating address to determine if the addresses are the same.
S22: a target write request is determined from the N write requests.
In this embodiment of the present application, if the read/write request initiating unit initiates the first read request R1, the target write request is determined from the latched N write requests based on comparing the operation address in R1 with the operation address in the N write requests.
The target write request refers to a write request with the same operation address as that of R1 in the latched write requests.
Referring to fig. 4, a schematic diagram of a comparison method is provided in an embodiment of the present application. Fig. 4 (a) shows a schematic diagram of an operation address comparison of R1 with N write requests latched.
The first read request R1 is in turn compared to the latches W1, W2, … …, WN for operation address consistency. Wherein, R1 and the latch W1 are subjected to address consistency comparison 1 stage, the latch W2 is subjected to address consistency comparison 2 stage, … …, and the latch WN is subjected to address consistency comparison N stage. If there is a write request identical to the operation address of R1, it is assumed that the write request Wi is written, N.gtoreq.i.gtoreq.1, and i is an integer, the write request Wi is taken as a target write request.
If the read-write request does not exist, the read-write request is not in the same address, the time intervals are not adjacent, and the read-write request can be directly cached in the cache body.
Fig. 4 (b) shows another schematic diagram of comparing R1 with the operation addresses of the N latched write requests. Wherein, R1 sequentially compares the address consistency with the write request W0 which is not stored by 0 level, compares the address consistency with the latch W1 by 1 level, compares the address consistency with the latch W2 by 2 levels, … …, and compares the address consistency with the latch WN by N levels. As long as there is a write request identical to the operation address of R1, this write request is the target write request. The target write request may be an unlatched write request, or may be at least one write request of the latched M write requests. In this way, the effect of an unlatched write request on the first read request is avoided.
Alternatively, there may be a plurality of write requests identical to the operation address of the first read request, and at this time, the target write request may be determined according to whether or not the difference between the initiation time of the write request and the initiation time of the first read request is within a preset difference threshold. If the difference value is within the preset difference value threshold value range, determining the target write request, otherwise, determining the target write request. The cache timing optimization unit caches the first read request to the cache bank.
S23: when the target write request is determined, a first read response is generated based on the first read request.
In the embodiment of the application, after determining the target write request, the first read request is discarded, and a first read response is generated. The first read response is used for indicating the read-write request initiating unit to initiate a second read request. Wherein the second read request is a read request different from the first read request.
S24: and sending the first read response to the read-write request initiating unit.
After the buffer sequence optimizing unit generates the first read request, the first read response is sent to the read-write request initiating unit. The read-write request initiating unit initiates a second read request according to the first read response.
In this way, the embodiment of the application compares the operation addresses of the first read request and the latched write requests by latching the write requests, and generates the first read response to trigger the read-write request initiating unit to initiate a new read request after the target request with the same operation address as the first read request exists. At this time, even if the time intervals of the read request and the write request of the same address are adjacent, the read-write request initiating unit can initiate a new read request. Therefore, according to the embodiment of the application, the requirement that the time intervals of the read request and the write request cached by the cache body are adjacent is not needed, the problem of invalidation of the read request and the write request caused by the fact that the time intervals of the read request and the write request of the same address are adjacent is solved, and the operation frequency of the cache of the chip is improved, and the overall operation frequency of the chip is improved.
In addition, the embodiment of the application also provides another read-write request processing method of the chip cache. Referring to fig. 5A, a flowchart of another method for processing a read-write request of a chip cache according to an embodiment of the present application is provided. The method comprises the following steps:
s51: and latching N write requests initiated by a read-write request initiating unit in the chip in response to receiving the N write requests.
S52: a target write request is determined from the N write requests.
S53: when the target write request is determined, a first read response is generated based on the first read request.
S54: and sending the first read response to a read-write request initiating unit.
S55: the read-write request initiating unit sends a second read request to the application.
Step S51 to step S55 are the same as step S31 to step S34, and are not discussed here.
S56: and after the target write request is not determined, caching the first read request into a cache body.
Exemplary description: assuming that the write request W0 is not latched, the same write request as the operation address of the first read request does not exist as the operation address of the latched write requests W1, … … WN. At this point, it indicates that the target write request is not determined. That is, the first read request does not have a case where it coincides with the write request operation address, and there is no case where the read request and the write request of the same address are adjacent in time interval. Thus, the first read request may be cached in the cache bank.
In addition, when the same operation address exists between the first read request and the write request, comparing the difference between the initiation time of the first read request and the initiation time of the write request, and if the difference is not within the preset difference range, indicating that the first read request and the write request are not in adjacent time intervals. At this point, it indicates that the target write request is not determined.
The cache timing optimization unit caches the first read request to the cache bank.
S57: and receiving a second read response initiated by the cache body and sending the second read response to the read-write request initiating unit.
After the buffer receives the first read request, a second read response is generated. The second read response is used for indicating the read-write request initiating unit to initiate the first read request.
The buffer body sends the received second read response to the read request initiating unit.
S58: the read-write request initiating unit sends a first read request to the application.
The read-write request initiating unit sends the first read request to the application based on receiving the second read response.
Therefore, the embodiment of the application optimizes the time sequence of the cache write request and the read request, reduces the requirement on the interval of the cache read write request, ensures the correctness of the cache under the higher frequency requirement, and reduces the development difficulty of the cache.
Referring to fig. 5B, a schematic diagram of a cache timing optimization unit in a chip according to an embodiment of the present application is provided. In practical application, the buffer sequence optimizing unit in the chip comprises a write request latching unit 501, a read/write request address comparing unit 502, a write/read request outputting unit 503 and a read response outputting unit 504.
The write request latching unit 501 is configured to include N latching units, where each latching unit latches N write requests initiated by the read/write request initiating unit according to a data stream manner, and sends the latched N write requests to the read/write request address comparing unit 502 for processing.
Referring to fig. 6, a schematic diagram of a read-write request address comparing unit 502 is provided in an embodiment of the present application. The read-write request address comparing unit 502 sequentially compares the first read request with the unlatched write requests and the latched N write requests for address consistency, wherein the first read request compares the first read request with the unlatched write requests for address consistency by 0 level, and the latched N write requests sequentially compares the first read request with the latched N write requests for address consistency by 1 level, address consistency by 2 level, … …, and address consistency by N level. And writing the write request of which each stage is the same as the operation address of the first read request into the write-read address proximity judgment module. The write-read address proximity judgment module determines a difference value between the written write request initiation time and the first read request initiation time, and determines that the target write request is not matched when the difference value is larger than a preset difference value threshold range. Otherwise, determining that the target write request is matched.
The write-read-address proximity judgment module sends the write-read-address proximity judgment result to the write-read-address proximity processing unit of the write-read request output unit 503. Referring to fig. 7, a schematic diagram of the write-read request output unit 503 is shown. The write-read-address proximity judgment result is output to the write-read-address proximity processing of the write-read-request output unit 503. If a target write request exists, the target write request is converted into a first read response, namely read response 1. When the target write request does not exist, the first read request is sent to the cache bank, and the second read response sent by the cache bank, namely the read response 2, is received.
Referring to fig. 8, in order to schematically illustrate the logic structure of the read response output unit 504, the judgment result, the read response 1, and the read response 2 sent from the write-read request output unit 503 are received. The read response output unit 504 includes a read response selection module, and outputs a first read response to the read-write request initiating unit when the determination result is that the same address of the read-write request is close. Otherwise, outputting the second read response to the read-write request initiating unit.
In addition, the embodiment of the application also provides a read-write request processing device of the chip cache. Referring to fig. 9, a schematic structural diagram of a read-write request processing device for a chip cache according to an embodiment of the present application is provided. Comprising the following steps: a write request latch unit 501, a read-write request address comparing unit 502, a write-read request output unit 503, and a read response output unit 504.
A write request latching unit 501, configured to latch N write requests initiated by a read/write request initiating unit in the chip in response to receiving the N write requests; n write requests include operation addresses, wherein N is an integer greater than 2;
a read-write request address comparing unit 502, configured to determine, in response to receiving a first read request initiated by a read-write request initiating unit, a target write request from the N write requests based on an operation address in the first read request and operation addresses in the N write requests, where the operation address in the target write request is the same as the operation address in the first read request;
a write-read-request output unit 503, configured to generate a first read response based on the first read request after determining the target write request, where the first read response is used to indicate that a second read request is initiated;
and a read response output unit 504, configured to send the first read response to the read-write request initiating unit, so that the read-write request initiating unit initiates the second read request.
Alternatively, the write request latch unit 501 is specifically applied:
according to the number of the beats and the initiation time of the N write requests, sequentially latching the N write requests, wherein the initiation time of the latched 1 st beat write request is the latest, and the initiation time of the latched N beat write request is the earliest; the latch beats and the operating frequency of the chip are in positive correlation.
Optionally, the read-write request address comparing unit 502 is specifically configured to:
and in response to receiving the first read request, matching the target write request from among the unlatched write requests and the latched N write requests.
Optionally, the apparatus further comprises: and the initiating unit is used for outputting the first read request to the cache body of the chip after the target write request is not determined, and receiving a second read response returned by the cache body so that the read-write request initiating unit initiates the first read request according to the second read response.
In this way, the embodiment of the application compares the operation addresses of the first read request and the latched write requests by latching the write requests, and generates the first read response to trigger the read-write request initiating unit to initiate a new read request after the target request with the same operation address as the first read request exists. At this time, even if the time intervals of the read request and the write request of the same address are adjacent, the read-write request initiating unit can initiate a new read request. Therefore, the embodiment of the application does not need the requirement that the time intervals of the read request and the write request of the cache body are adjacent, solves the problem of invalidation of the read request and the write request caused by the adjacent time intervals of the read request and the write request of the same address, and is beneficial to improving the operation frequency of the cache of the chip and the overall operation frequency of the chip.
Furthermore, embodiments of the present application provide a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the method according to any of the first aspects.
From the foregoing description of the embodiments, it will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of functional modules is illustrated, and in practical application, the above-described functional allocation may be implemented by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to implement all or part of the functions described above. The specific working processes of the above-described systems, devices and units may refer to the corresponding processes in the foregoing method embodiments, which are not described herein.
In the several embodiments provided in this embodiment, it should be understood that the disclosed system and method may be implemented in other ways. For example, the embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present embodiment may be integrated in one processing unit, each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units described above may be implemented in hardware.
The integrated unit may be implemented as a switching chip and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present embodiment may be essentially or a part contributing to the prior art or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the method described in the respective embodiments. And the aforementioned storage medium includes: flash memory, removable hard disk, read-only memory, random access memory, magnetic or optical disk, and the like.
The foregoing is merely a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A read-write request processing method of a chip cache is characterized by comprising the following steps:
responding to N write requests initiated by a read-write request initiating unit in the chip, and latching the N write requests; each of the N write requests includes an operation address, where N is an integer greater than 2;
in response to receiving a first read request initiated by the read-write request initiating unit, determining a target write request from the N write requests based on an operation address in the first read request and operation addresses in the N write requests, wherein the operation address in the target write request is the same as the operation address in the first read request;
generating a first read response based on the first read request after determining the target write request, the first read response being used to indicate initiation of a second read request;
and sending the first read response to the read-write request initiating unit so that the read-write request initiating unit initiates the second read request.
2. The method of claim 1, wherein said latching said N write requests comprises:
according to the number of the beats and the initiation time of the N write requests, sequentially latching the N write requests, wherein the initiation time of the latched 1 st beat write request is the latest, and the initiation time of the latched N beat write request is the earliest; the latch beats and the operating frequency of the chip are in positive correlation.
3. The method of claim 2, wherein the determining, in response to receiving the first read request initiated by the read-write request initiation unit, a target write request from the N write requests based on an operation address in the first read request and an operation address in the N write requests, comprises:
and in response to receiving a first read request initiated by the read-write request initiating unit, comparing the first read request with the N latched write requests in turn, and determining the target write request from the N write requests.
4. The method of claim 3, wherein the determining the target write request from the N write requests comprises:
when the N latched write requests have the same write request with the operation address of the first read request, and the difference value between the initiation time of the write request and the initiation time of the first read request is within a preset difference threshold range, determining the target write request.
5. The method of any of claims 1-4, wherein the determining a target write request from the N write requests comprises:
the target write request is matched from among the unlatched write requests and the latched N write requests.
6. The method according to claim 1, wherein the method further comprises:
and when the target write request is not determined, outputting the first read request to a cache body of the chip, and receiving a second read response returned by the cache body, so that the read-write request initiating unit initiates the first read request according to the second read response.
7. A read-write request processing apparatus for a chip cache, the apparatus comprising:
the write request latching unit is used for latching N write requests initiated by the read-write request initiating unit in response to receiving the N write requests; each of the N write requests includes an operation address, where N is an integer greater than 2;
a read-write request address comparing unit, configured to determine, in response to receiving a first read request initiated by the read-write request initiating unit, a target write request from the N write requests based on an operation address in the first read request and operation addresses in the N write requests, where the operation address in the target write request is the same as the operation address in the first read request;
a write-read request output unit, configured to generate a first read response based on the first read request after determining the target write request, where the first read response is used to indicate to initiate a second read request;
and the read response output unit is used for sending the first read response to the read-write request initiating unit so as to enable the read-write request initiating unit to initiate the second read request.
8. The apparatus of claim 7, wherein the write request latching unit is specifically configured to:
according to the number of the beats and the initiation time of the N write requests, sequentially latching the N write requests, wherein the initiation time of the latched 1 st beat write request is the latest, and the initiation time of the latched N beat write request is the earliest; the latch beats and the operating frequency of the chip are in positive correlation.
9. A chip, which is characterized by comprising a memory and a processor;
the memory is coupled with the processor;
the memory stores program instructions that, when executed by the processor, cause the chip to perform the method of any of claims 1-6.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the method of any of claims 1-6.
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