CN117388662A - A method for extracting tunneling field effect transistor parameters - Google Patents

Abstract

The invention discloses a method for extracting parameters of a tunneling field effect transistor, and belongs to the technical field of semiconductors. The method uses a semiconductor parameter analyzer to measure N-type or P-type DL _und The gate capacitance of the TFET device, thereby obtaining the N-type or P-type DL _und The outer edge gate capacitance areal density C of the device source end when the channel surface of the TFET device is in a depletion state _OFS0 And the outer edge gate capacitance areal density C of the device drain _OFD0 The method comprises the steps of carrying out a first treatment on the surface of the According to the formulaObtaining the parameter L of the tunneling field effect transistor _und . The invention can be completed only by means of a semiconductor analyzer and MATLAB software, and has the advantages of rapidness and low cost.

Description

A method for extracting tunneling field effect transistor parameters

Technical field

The invention belongs to the field of semiconductor technology, and specifically relates to a method for extracting parameters of tunneling field effect transistors.

Background technique

The development of artificial intelligence Internet of Things (AIoT) technology has put forward higher requirements for semiconductor power consumption, and tunneling field effect transistors (TFETs) are considered to be one of the most potential low-power devices. There are tunnel junctions at both the source and drain ends of a tunneling field effect transistor. The tunnel junction at the source end is used to provide the on-state current of the device, while the tunnel junction at the drain end will cause the device to increase the off-state current. Generally, methods such as reducing the impurity doping concentration of the drain end or preparing an undercovered area of the drain end are often used to increase the tunneling width of the drain end tunnel junction and reduce the band-to-band tunneling of the drain end tunnel junction of the tunneling field effect transistor. current.

The drain undercoverage refers to the electrical length from the gate edge of the tunneling field effect transistor close to the drain to the drain tunnel junction. Regarding the method of preparing the drain end undercoverage area, it is necessary to know the length of the device drain end undercoverage area to isolate the device fluctuation source, adjust the device electrical performance, etc. However, existing physical characterization methods can only obtain the physical length of the drain end undercoverage of a single device, and the cost of physical characterization of each device is high. Therefore, there is a need to invent a method for extracting the length of the under-covered area of the drain end of a tunneling field-effect transistor, which can extract the electrical length of the under-covered area of the drain end only through electrical characterization.

Contents of the invention

The purpose of the present invention is to propose a method for extracting tunneling field effect transistor parameters, which can extract the average drain undercover of tunneling field effect transistors with drain undercoverage (DL _und -TFET) through electrical characterization only. Coverage area electrical length L _und .

The technical solutions provided by the invention are as follows:

A method of extracting the average electrical length L _und of the drain undercoverage of a tunneling field effect transistor (DL _und -TFET) with a drain undercoverage, which is characterized by:

Use a semiconductor parameter analyzer to measure the gate capacitance of the N-type DL _und -TFET device (or P-type), and then obtain the external capacitance of the source end of the device when the channel surface of the N-type DL _und -TFET device (or P-type) is in a depleted state. The edge gate capacitance areal density C _OFS0 and the outer edge gate capacitance areal density C _OFD0 at the drain end of the device. Calculate the value of L _und according to formula (1) and complete the extraction of L _und .

In formula (1), ε _OFF and ε _ON are the dielectric constant of the source gate sidewall and the drain side gate sidewall of the DL _und -TFET device respectively, L _G is the gate length of the DL _und -TFET device, and EOT is the effective gate oxide thickness of the DL _und -TFET device, ε ₀ is the permittivity in vacuum, and π is the pi. Among them, ε ₀ and π are constants known to professionals in the field and can be found in textbooks or on the Internet. ε _OFF , ε _ON , _LG and EOT are all material and structural parameters of the measured DL _und -TFET device, which can only be known by extracting parameters of the measured device.

Furthermore, the method to obtain the ε _OFF , ε _ON , _LG and EOT parameters of DL _und -TFET devices has the following characteristics:

Use a semiconductor parameter analyzer to measure the gate capacitance of the N-type DL _und -TFET device (or P-type), and then obtain the time when the channel surface of the N-type DL _und -TFET device (or P-type) is in an accumulation state (or inversion state) The outer edge gate capacitance areal density C _OFS1 at the source end of the device, the outer edge gate capacitance areal density C _OFD2 at the drain end of the device when the channel surface of the N-type DL _und -TFET device (or P-type) is in the inversion state (or accumulation state) and DL _und -The equivalent gate oxide capacitance areal density C _OX of the TFET device. Obtain the value of the gate length _LG according to the layout of the tested DL _und -TFET device. Calculate the values of EOT, ε _OFF and ε _ON according to formulas (2), (3) and (4) to complete the analysis of the DL _und -TFET device. ε _OFF , ε _ON , _LG and EOT parameter extraction work.

In formula (2), ε _OX refers to the dielectric constant of silicon dioxide, which is a constant known to professionals in the field and can be found in textbooks or on the Internet. H _G in formula (3) and formula (4) are both the height of the gate conductive layer of the DL _und -TFET device, which can be obtained by checking the process preparation parameters of the DL _und -TFET device, that is, checking the deposition of the gate conductive layer material The thickness is H _G .

Normally, the gate capacitance of DL _und -TFET devices measured by a semiconductor analyzer refers to the gate-source capacitance that changes with the gate voltage and the gate-drain capacitance that changes with the gate voltage. Their physical components include equivalent gate oxide layer capacitance, outer edge gate capacitance at the source end, outer edge gate capacitance at the drain end, depletion layer capacitance, etc. These physical components need to be obtained by analyzing test data and cannot be directly measured by a semiconductor analyzer. .

Further, use a semiconductor parameter analyzer to measure the gate-source capacitance and gate-drain capacitance of the N-type DL _und -TFET device (or P-type) corresponding to different gate voltages V _G. The source voltage V _S and the drain voltage V _D are both 0V, and the gate The scanning range of voltage V _G is from -VDD to VDD. VDD is the power supply voltage corresponding to the circuit composed of DL _und -TFET devices. N DL _und -TFET devices of each gate length are tested, and a total of M gate length devices are tested. The size of N can be a positive integer greater than or equal to 1, and the size of M can be a positive integer greater than or equal to 1.

For each gate length DL _und -TFET device, calculate the average value of the gate-source capacitance and gate-drain capacitance of N devices, and divide it by the gate area of the device to obtain the average gate-source capacitance area density C _GS and the average gate-drain capacitance area. Density C _GD , adding C _GS and C _GD gives the average gate capacitance areal density C _GG . The gate area of the device refers to the product of the gate length L _G and the gate width W _G of the DL _und -TFET device under test, which can be obtained by measuring the layout.

Draw the variation curves of the average gate-source capacitance surface density C _GS , the average gate-drain capacitance surface density C _GD and the average gate capacitance surface density C _GG relative to the gate voltage V _G to assist subsequent data processing. It can be found that the unique electrical characteristics of DL _und -TFET devices, that is, its “C _GS -V _G ” and “ _CGD -V _G ” curves have gate length dependence and secondary turn-on phenomena. The “C _GG -V _G ” curve has gate length dependence and three saturation regions. Define a certain gate voltage in the saturation area in the middle section of the "C _GG -V _G " curve as V ₀ , and define a certain gate in the saturation area after the second turn-on of the "C _GS -V _G " curve of the DL _und -TFET device. The voltage is V ₁ , and a gate voltage in the saturation region after the second turn-on of the " _CGD -V _G " curve of the DL _und -TFET device is defined as V ₂ .

From the average gate capacitance areal density C _GG of DL _und -TFET devices with M gate lengths, the values C _GG1 when V _G = V ₁ are extracted, M in total. From the average gate capacitance areal density C _GG of DL _und -TFET devices with M gate lengths, the values C _GG2 when V _G = V ₂ are extracted, M in total. From the average gate-source capacitance surface density C _GS of DL _und -TFET devices with M gate lengths, the value C _GS1 when V _G = V ₁ is extracted, M in total. From the average gate-source capacitance areal density C _GS of DL _und -TFET devices with M gate lengths, the value C _GS0 when V _G = V ₀ is extracted, M in total. From the average gate-source capacitance areal density _CGD of DL _und -TFET devices with M gate lengths, the value _CGD0 when V _G =V ₀ is extracted, M in total.

Use MATLAB or other data processing software to linearly fit the M C _GG1 extracted above and the corresponding M 1/L _G to obtain the fitting formula C _GG1 =P ₁ +Q ₁ *(1/L _G ), where P ₁ refers to C _OX , which is the value on the left side of formula (2). Using the same method, perform linear fitting on the M C _GG2 extracted above and their corresponding M 1/L _G , and obtain the fitting formula C _GG2 =P ₂ +Q ₂ *(1/L _G ), where Q ₂ refers to C _OFD2 * _LG , which is the value on the left side of formula (4). Using the same method, perform linear fitting on the M C _GS1 extracted above and its corresponding M 1/L _G , and obtain the fitting formula C _GS1 =P ₃ +Q ₃ *(1/L _G ), where Q ₃ refers to C _OFS1 *L _G , which is the value on the left side of formula (3). Using the same method, perform linear fitting on the M C _GS0 extracted above and its corresponding M 1/L _G , and obtain the fitting formula C _GS0 =P ₄ +Q ₄ *(1/L _G ), where Q ₄ refers to C _OFS0 *L _G , which is used to bring the corresponding part on the left side of formula (1) for calculation. Use the same method to linearly fit the M C _GD0 extracted above and the corresponding M 1/L _G to obtain the fitting formula C _GD0 =P ₅ +Q ₅ *(1/L _G ), where Q ₅ refers to C _OFD0 *L _G , which is used to bring the corresponding part on the left side of formula (1) for calculation.

The beneficial effects of the present invention are as follows:

The above-mentioned method proposed by the present invention can extract and obtain the electrical length L _und of the average drain end undercoverage area of the DL _und -TFET device only by conducting electrical testing and data analysis on the gate capacitance of the DL _und -TFET device. All work can be completed with the help of a semiconductor parameter analyzer and MATLAB, which has the advantages of speed and low cost.

Description of the drawings

Figure 1 is a flow chart for extracting the electrical length of the average drain under-coverage area of DL _und -TFET devices proposed by the present invention;

Figure 2 is an intermediate result diagram of extracting the average electrical length of the drain end under-coverage area of a certain DL _und -TFET device according to the method proposed by the present invention. Specifically

(a) is the variation curve of the average gate-source capacitance area density (C _GS ) relative to the gate voltage (V _G );

(b) is the variation curve of the average gate-to-drain capacitance areal density (C _GD ) relative to the gate voltage (V _G );

(c) is the variation curve of the average gate capacitance areal density (C _GG ) relative to the gate voltage (V _G );

(d) is the change curve of C _GG1 relative to 1/L _G and its linear fitting results;

(e) is the change curve of C _GG2 relative to 1/L _G and its linear fitting results;

(f) is the change curve of C _GS1 relative to 1/L _G and its linear fitting results;

(g) is the change curve of C _GS0 relative to 1/L _G and its linear fitting results;

(h) is the change curve of C _GD0 relative to 1/L _G and its linear fitting results;

Figure 3 is a schematic structural diagram of a certain DL _und -TFET device studied in Figure 2 and a schematic diagram of its geometric parameters;

In the picture:

1——High resistance silicon substrate; 2——Shallow trench isolation;

3——Gate dielectric layer; 4——Gate conductive layer;

5——Source side wall; 6——Drain side side wall;

7——Source impurity doping region; 8——Drain impurity doping region;

9——Source metal layer; 10——Drain metal layer;

Detailed ways

An exemplary embodiment of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. of. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined by the claims.

FIG. 1 shows the flow chart of the method for extracting the average drain terminal undercoverage electrical length L _und of a DL _und -TFET device proposed by a specific embodiment of the present invention. This flow chart integrates the proposed method of extracting L _und with the method of extracting ε _OFF , ε _ON , _LG , and EOT parameters, and the method of obtaining the physical components of each gate capacitance. According to the steps in Figure 1, extract the average drain end undercover area electrical length L _und of a certain DL _und -TFET device shown in Figure 3. This device is an N-type TFET device.

First, use a semiconductor parameter analyzer to test the gate-source capacitance and gate-drain capacitance of the device. The scanning range of the gate voltage V _G is -2.5V to 2.5V, and the source voltage V _S and drain voltage V _D are both 0V. A total of five devices with gate lengths were tested, and five devices were tested with each gate length. The gate length sizes were 60nm, 120nm, 180nm, 240nm and 300nm respectively;

Next, for each gate length device, divide the tested gate-source capacitance and gate-drain capacitance by the gate area of the device to obtain the gate-source capacitance area density and gate-drain capacitance area density;

Next, calculate the average gate-source capacitance area density C _GS and the average gate-drain capacitance area density C _GD corresponding to each gate length device;

Next, add the average gate-source capacitance area density C _GS and the average gate-drain capacitance area density C _GD to calculate the average gate capacitance area density C _GG corresponding to each gate length device;

Next, as shown in Figure 2(a), the variation curve of the average gate-source capacitance area density C _GS of each gate length device relative to the gate voltage V _G is drawn in a graph;

Next, as shown in Figure 2(b), the variation curve of the average gate-to-drain capacitance area density C _GD of each gate length device relative to the gate voltage V _G is drawn in a graph;

The gate length dependence and secondary turn-on phenomenon can be observed in both Figure 2(a) and Figure 2(b). After each turn on, there is a region where the capacitance hardly changes relative to the gate voltage, which is the capacitance saturation region, and the corresponding capacitance value is the saturation capacitance. Define V ₁ =-2.5V, V ₂ =1V

Next, as shown in Figure 2(c), the variation curve of the average gate capacitance area density C _GG of each gate length device relative to the gate voltage V _G is drawn in a graph;

In Figure 2(c), the gate length dependence and the three saturation regions can be observed. The gate voltage of the middle saturation region -0.7V is selected as V ₀ ;

Next, for each gate length device, extract the average gate-source capacitance area density (C _GS ) when V _G = V ₁ as C _GS1 ;

Next, for each gate length device, extract the average gate-source capacitance area density (C _GS ) when V _G = V ₀ as C _GS0 ;

Next, for each gate length device, extract the average gate-to-drain capacitance areal density ( _CGD ) when V _G = V ₀ as _CGD0 ;

Next, for each gate length device, extract the average gate capacitance areal density (C _GG ) when V _G = V ₁ as C _GG1 ;

Next, for each gate length device, extract the average gate capacitance areal density (C _GG ) when V _G = V ₂ as C _GG2 ;

Next, as shown in Figure 2(d), the change curve of C _GG1 relative to 1/L _G and its linear fitting result are drawn in a picture. The fitting result is

Next, as shown in Figure 2(e), the change curve of C _GG2 relative to 1/L _G and its linear fitting result are drawn in a picture. The fitting result is

Next, as shown in Figure 2(f), the change curve of C _GS1 relative to 1/L _G and its linear fitting result are drawn in a picture. The fitting result is

Next, as shown in Figure 2(g), the change curve of C _GS0 relative to 1/L _G and its linear fitting result are drawn in a picture. The fitting result is

Next, as shown in Figure 2(h), the change curve of C _GD0 relative to 1/L _G and its linear fitting result are drawn in a picture. The fitting result is

Next, according to formula (2), we can know that Bringing in the parameters ε ₀ =8.85×10 ^-14 F/cm and ε _ox =3.9, the extracted EOT =2.3nm;

Next, according to formula (4), we can know that Bringing in the parameters EOT=2.3nm, ε ₀ =8.85×10 ^-14 F/cm and H _G =89nm, we extract ε _ON =7.6;

Next, according to formula (3), we can know that Bringing in the parameters EOT=2.3nm, ε ₀ =8.85×10 ^-14 F/cm and H _G =89nm, we extract ε _OFF =6.9;

Next, according to formula (1), we can know that Bringing in the parameters EOT = 2.3nm, ε ₀ = 8.85×10 ^-14 F/cm, ε _OFF = 6.9 and ε _ON = 7.6, extract L _und = 19nm;

The length of L _und refers to the electrical length between the gate boundary near the drain end and the drain tunnel junction, which is approximately equal to the length L m between the gate boundary near the drain end and the boundary of the drain end metal layer 10 minus the length L _m surrounding the drain end metal layer 10 The drain terminal impurity doped region 8 has a width L _d of a doping concentration peak region. Through TEM characterization, the L _m of a certain device shown in Figure 3 is found to be 30nm, and through Sentaurus Sprocess simulation, the width of L _d is found to be 10nm. This verifies the rationality and accuracy of the average drain undercoverage length of the DL _und -TFET device extracted by the proposed method.

Although the present invention has been disclosed above in terms of preferred embodiments, this is not intended to limit the present invention. Any person familiar with the art can make many possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above, or modify it into equivalent implementations with equivalent changes, without departing from the scope of the technical solution of the present invention. example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims (5)

1. A method for extracting tunneling field effect transistor parameters, the steps include: 1) Use a semiconductor parameter analyzer to measure the gate capacitance of the N-type or P-type DL _und -TFET device, and then obtain the outer edge gate of the source end of the device when the channel surface of the N-type or P-type DL _und -TFET device is in a depletion state. The capacitance area density C _OFS0 and the outer edge gate capacitance area density C _OFD0 of the device drain end; 2) Calculate the value of L _und according to formula (1), In the above formula, ε _OFF and ε _ON are the dielectric constant of the source gate sidewall and the drain side gate sidewall of the DL _und -TFET device respectively, L _G is the gate length of the DL _und -TFET device, and EOT is DL _{und -} The effective gate oxide thickness of the TFET device, ε ₀ is the dielectric constant in vacuum, π is the pi, ε _OFF , ε _ON , _LG and EOT are the measured material and structural parameters of the DL _und -TFET device, so Obtain the parameters L _und of the tunneling field effect transistor. 2. The method for extracting tunneling field effect transistor parameters as claimed in claim 1, characterized in that a semiconductor parameter analyzer is used to measure the gate capacitance of the N-type or P-type DL _und -TFET device to obtain the N-type or P-type DL _und -The channel surface of the TFET device is in the accumulation state or the inversion state. The outer edge gate capacitance area density C _OFS1 at the source end of the device. N-type or P-type DL _und -The channel surface of the TFET device is in the inversion state or the accumulation state. When the outer edge gate capacitance area density C _OFD2 of the device drain end and the equivalent gate oxide layer capacitance area density C _OX of the DL _und -TFET device are obtained, the value of the gate length L _G is obtained according to the layout of the tested DL _und -TFET device. According to Formulas (2), (3) and (4) calculate the values of EOT, ε _OFF and ε _ON ; In formula (2), ε _OX refers to the dielectric constant of silicon dioxide, and H _G in formula (3) and formula (4) are both the height of the gate conductive layer of the DL _und -TFET device. 3. The method for extracting tunneling field effect transistor parameters as claimed in claim 1, characterized in that a semiconductor parameter analyzer is used to measure the gate-source capacitance of N-type or P-type DL _und -TFET devices corresponding to different gate voltages _VG . and gate-drain capacitance, the source voltage V _S and the drain voltage V _D are both 0V, the scanning range of the gate voltage V _G is from -VDD to VDD, VDD is the power supply voltage corresponding to the circuit composed of DL _und -TFET devices, each gate N long DL _und -TFET devices are tested, and a total of M gate length devices are tested. The size of N is a positive integer greater than or equal to 1, and the size of M is a positive integer greater than or equal to 1. 4. The method for extracting tunneling field effect transistor parameters as claimed in claim 3, characterized in that, for each gate length DL _und -TFET device, the average value of the gate-source capacitance and gate-drain capacitance of N devices is calculated. , and divided by the gate area of the device to obtain the average gate-source capacitance areal density C _GS and the average gate-drain capacitance areal density C _GD , add C _GS and _CGD to obtain the average gate capacitance areal density C _GG , and obtain the average gate-source capacitance The change curves of area density C _GS , average gate-to-leak capacitance area density C _GD and average gate capacitance area density C _GG with respect to the gate voltage V _G. Define a certain gate voltage in the saturation zone in the middle section of the "C _GG -V _G " curve as V ₀ , defines the "C _GS -V _G " curve of the DL _und -TFET device. A gate voltage in the saturation region after the second turn-on is V ₁ , defines the "C _GD -V _G " of the DL _und -TFET device. A certain gate voltage in the saturation region after the curve is turned on for the second time is V ₂ ; from the average gate capacitance areal density C _GG of DL _und -TFET devices with M gate lengths, the value when V _G = V ₁ is extracted C _GG1 , M in total; from the average gate capacitance areal density C _GG of DL _und -TFET devices with M gate lengths, the value C _GG2 when V _G = V ₂ is extracted, M in total; from the M gate lengths From the average gate-source capacitance area density C _GS of DL _und -TFET devices, extract the value C _GS1 when V _G = V ₁ , a total of M; from the average gate-source capacitance of DL _und -TFET devices with M gate lengths From the area density C _GS , the value C _GS0 when V _G = V ₀ is extracted, M in total; from the average gate-source capacitance area density C _GD of the DL _und -TFET device with M gate lengths, V _G = There are M values C _GD0 when V ₀ ; use MATLAB or other data processing software to linearly fit the M C _GG1 extracted above and their corresponding M 1/L _G to obtain the fitting formula C _GG1 =P ₁ +Q ₁ *(1/L _G ), where P ₁ refers to C _OX . Using the same method, make a linear fit to the M C _GG2 extracted above and its corresponding M 1/L _G Combined, the fitting formula C _GG2 =P ₂ +Q ₂ *(1/L _G ) is obtained, where Q ₂ refers to C _OFD2 * _LG ; using the same method, the M C _GS1 and other extracted Corresponding M 1/L _G are linearly fitted to obtain the fitting formula C _GS1 =P ₃ +Q ₃ *(1/L _G ), where Q ₃ refers to C _OFS1 *L _G ; using the same method, Perform linear fitting on the M C _GS0 extracted above and its corresponding M 1/L _G , and obtain the fitting formula C _GS0 =P ₄ +Q ₄ *(1/L _G ), where Q ₄ refers to C _OFS0 * _LG ; Use the same method to perform linear fitting on the M C _GD0 extracted above and its corresponding M 1/L _G , and obtain the fitting formula C _GD0 =P ₅ +Q ₅ *(1 /L _G ), where Q ₅ refers to C _OFD0 *L _G . 5. The method for extracting tunneling field effect transistor parameters according to claim 4, characterized in that the gate area A of the DLund-TFET device = gate length L _G * gate width W _G .