CN117374102A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present disclosure provides a semiconductor device and a method of manufacturing the same, wherein the semiconductor device includes a substrate, a channel layer, an insertion layer, a barrier layer, and a gate electrode. The channel layer is disposed on the substrate, and the channel layer includes a nitride semiconductor material. The barrier layer is disposed on a side of the channel layer remote from the substrate, the barrier layer includes a nitride semiconductor material, and an energy gap of the barrier layer is greater than an energy gap of the channel layer. The grid electrode is arranged on one side of the barrier layer away from the channel layer. The insertion layer is disposed between the channel layer and the barrier layer, and the insertion layer is provided with a gap in a region corresponding to the gate electrode. By arranging the insertion layer with the gap, not only can the electron mobility be improved, but also the defects of easy punch-through of the device, reduced breakdown voltage of the device and the like can be avoided.

Description

Semiconductor device and manufacturing method thereof

Technical field

The present disclosure relates to the field of semiconductors, and in particular, to a semiconductor device and a manufacturing method thereof.

Background technique

Components containing direct bandgap semiconductors, such as semiconductor components containing III-V materials or III-V compounds (category: III-V compounds) can operate under various conditions or in various environments (e.g., in different voltage and frequency) operate or work.

Semiconductor components may include heterojunction bipolar transistor (HBT), heterojunction field effect transistor (HFET), high-electron-mobility transistor (HEMT), modulation Doped FET (modulation-doped FET, MODFET), etc.

Contents of the invention

According to a first aspect of embodiments of the present disclosure, a semiconductor device is provided, the semiconductor device including:

substrate;

a channel layer, the channel layer is provided on the substrate, the channel layer includes a nitride semiconductor material;

A barrier layer, the barrier layer is disposed on a side of the channel layer away from the substrate, the barrier layer includes a nitride semiconductor material, and the energy gap of the barrier layer is larger than the channel energy gap of the layer;

a gate, the gate being disposed on a side of the barrier layer away from the channel layer;

Wherein, an insertion layer is provided between the channel layer and the barrier layer, and the insertion layer is provided with a gap in a region corresponding to the gate electrode.

In some embodiments, the insertion layer includes a first insertion block and a second insertion block arranged at intervals, and the gap is provided between the first insertion block and the second insertion block.

In some embodiments, the semiconductor device further includes a source electrode and a drain electrode. The source electrode and the drain electrode are disposed on a side of the barrier layer away from the channel layer. The source electrode and the drain electrode are located on Opposite sides of the gate.

In some embodiments, the orthographic projection of the first insertion block on the substrate at least partially overlaps the orthographic projection of the source on the substrate;

There is at least a partial overlap between an orthographic projection of the second insertion block on the substrate and an orthographic projection of the drain electrode on the substrate.

In some embodiments, the orthographic projection of the gap on the substrate partially overlaps and completely coincides with the orthographic projection of the gate on the substrate.

In some embodiments, the barrier layer includes a protruding portion and a main body portion, wherein the protruding portion is filled in the gap between the first insertion block and the second insertion block, so The main body part is located above the first insertion block, the protruding part and the second insertion block.

In some embodiments, the channel layer includes a compound In _a Al _b Ga _(1-ab) N, where a+b≦1;

Alternatively, the channel layer includes a compound Al _a Ga _(1-a) N, where a≦1.

In some embodiments, the barrier layer includes a compound In _a Al _b Ga _(1-ab) N, where a+b≦1;

Alternatively, the barrier layer includes the compound Al _a Ga _(1-a) N, where a≦1.

In some embodiments, the material of the insertion layer includes III-V group materials;

Alternatively, the material of the insertion layer includes Group III nitride.

In some embodiments, the channel layer is made of gallium nitride, the barrier layer is made of aluminum gallium nitride, and the insertion layer is made of aluminum nitride.

In some embodiments, the semiconductor device further includes a buffer layer disposed between the substrate and the channel layer, the buffer layer including a III-V compound.

In some embodiments, the material of the buffer layer includes AlN, AlGaN, InAlGaN, GaAs, AlAs, ZnO or a combination thereof.

In some embodiments, the semiconductor device further includes a nucleation layer disposed between the substrate and the channel layer.

In some embodiments, the semiconductor device further includes a depletion layer disposed between the barrier layer and the gate electrode.

In some embodiments, the depletion layer includes p-type dopants.

According to a second aspect of embodiments of the present disclosure, a method of manufacturing a semiconductor device is provided, the manufacturing method including:

Provide a substrate;

forming a channel layer on the substrate, the channel layer including a nitride semiconductor material;

An insertion layer is formed on the channel layer, and a gap is provided in the insertion layer;

forming a barrier layer on the insertion layer, the barrier layer comprising a nitride semiconductor material, and the energy gap of the barrier layer being greater than the energy gap of the channel layer;

A gate electrode is formed on the barrier layer, and the gate electrode is located above the gap.

In some embodiments, forming the intervening layer includes:

forming an insertion material layer on the channel layer;

A part of the insertion material layer is removed by selective etching to form an insertion layer.

In some embodiments, the material of the insertion layer includes III-V group materials;

Alternatively, the material of the insertion layer includes Group III nitride.

In some embodiments, the channel layer is made of gallium nitride, the barrier layer is made of aluminum gallium nitride, and the insertion layer is made of aluminum nitride.

In some embodiments, before forming the gate, a depletion layer is formed on the barrier layer, and the depletion layer includes a p-type dopant.

Description of the drawings

1 is a cross-sectional view of a semiconductor device provided by an exemplary embodiment of the present disclosure;

2 is a cross-sectional view of a semiconductor device provided by another exemplary embodiment of the present disclosure;

3 is a cross-sectional view of a semiconductor device provided by yet another exemplary embodiment of the present disclosure;

4 is a cross-sectional view of a semiconductor device provided by yet another exemplary embodiment of the present disclosure;

5 to 10 are cross-sectional views of various stages of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure.

Detailed ways

Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings refer to the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with aspects of the disclosure as detailed in the appended claims.

The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "the" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various information, the information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of the present disclosure, the first information may also be called second information, and similarly, the second information may also be called first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "when" or "in response to determining."

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are examples only and are not intended to be limiting. In this disclosure, in the following description, references to a first feature being formed or positioned on or over a second feature may include embodiments in which the first feature and the second feature are formed or positioned in direct contact, and may also include Embodiments are included in which additional features may be formed and positioned between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and/or letters in various instances. This repetition is for simplicity and clarity and does not by itself indicate a relationship between the various embodiments and/or configurations discussed.

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative only and do not limit the scope of the disclosure.

The present disclosure provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device includes a substrate, a channel layer, an insertion layer, a barrier layer and a gate electrode. The channel layer is provided on the substrate, and the channel layer includes a nitride semiconductor material. The barrier layer is disposed on a side of the channel layer away from the substrate, the barrier layer includes a nitride semiconductor material, and the energy gap of the barrier layer is greater than the energy gap of the channel layer . The gate electrode is disposed on a side of the barrier layer away from the channel layer. The insertion layer is provided between the channel layer and the barrier layer, and the insertion layer is provided with a gap in a region corresponding to the gate electrode. By providing the above-mentioned insertion layer with a gap, the electron mobility can be improved, and defects such as easy punch-through of the device and reduced breakdown voltage of the device can be avoided.

The semiconductor device of the present disclosure may be applied to, but is not limited to, HEMT devices, especially in low-voltage HEMT devices, high-voltage HEMT devices, and radio frequency (RF) HEMT devices.

Figure 1 is a cross-sectional view of a semiconductor device 100 in accordance with some embodiments of the present disclosure. The semiconductor device 100 may include a substrate 10 , a nucleation layer 20 , a buffer layer 30 , a nitride semiconductor layer 40 , an insertion layer 50 , a nitride semiconductor layer 60 , an electrode 70 , an electrode 90 , a depletion layer 82 and a gate electrode 84 .

The substrate 10 may include, but is not limited to, silicon (Si), doped silicon (doped Si), silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs) or other semiconductor materials. The substrate 10 may include, but is not limited to, sapphire, silicon on insulator (SOI), or other suitable materials. In some embodiments, the substrate 10 may also include a doped region (not shown in the figure), such as a p-well (p-well), an n-well (n-well), etc.

Nucleation layer 20 may be disposed on substrate 10 . Nucleation layer 20 may form an interface with substrate 10 . Nucleation layer 20 is configured to provide a top surface for growth of Group III nitride material thereon. In other words, nucleation layer 20 forms a suitable template for transitioning from the substrate's crystal lattice to one more suitable for growth of Group III nitride materials. Nucleation layer 20 may provide a transition to accommodate mismatches/differences between substrate 10 and the III nitride layer to be formed on its top surface (eg, epitaxially formed). The mismatch/difference may involve different lattice constants or thermal expansion coefficients. Mismatch/differences can lead to dislocations in the formation layer, thereby reducing the yield rate. Exemplary materials for nucleation layer 20 may include, but are not limited to, aluminum nitride (AlN) or any alloy thereof. The aluminum nitride may be, for example, but not limited to, doped n-type, p-type, or intrinsic. The material of the nucleation layer can be selected to eliminate mismatch/differences. For example, to accommodate mismatches/differences due to the first element in the layer to be formed on the nucleation layer, nucleation layer 20 is formed to include the first element.

Buffer layer 30 may be disposed on nucleation layer 20 . The buffer layer 30 may form an interface with the nucleation layer 20 . Buffer layer 30 has a bottommost surface in contact with nucleation layer 20 . The interface is formed by the bottommost surface of the buffer layer 30 and the topmost surface of the nucleation layer 20 . The buffer layer 30 has a topmost surface opposite a bottommost surface. Buffer layer 30 is configured to reduce lattice mismatch and thermal mismatch between the underlying layer and layers to be formed (eg, epitaxially formed thereon) on buffer layer 30, thereby curing defects due to mismatch/disparity.

Buffer layer 30 may include III-V compounds. III-V compounds may include, but are not limited to, aluminum, gallium, indium, nitrides, or combinations thereof. Accordingly, exemplary materials of buffer layer 30 may further include, for example, but not limited to, AlN, AlGaN, InAlGaN, GaAs, AlAs, ZnO, or combinations thereof. In some embodiments, buffer layer 30 may include two Group III elements, and the nucleation layer has only one Group III element. For example, the nucleation layer includes a compound containing aluminum and not containing gallium (eg, AlN), and the buffer layer 30 includes a III-V compound containing aluminum and gallium (eg, AlGaN).

The nitride semiconductor layer 40 (which may also be called the first nitride semiconductor layer 40 or the channel layer 40 ) may be disposed on the buffer layer 30 . The nitride semiconductor layer 40 may include a III-V group material layer. The nitride semiconductor layer 40 may include, but is not limited to, Group III nitride, such as the compound In _a Al _b Ga _(1-ab) N, where a+b≦1. The Group III nitride further includes, but is not limited to, for example, the compound _Ala Ga _(1-a) N, where a≦1. The nitride semiconductor layer 40 may include a gallium nitride (GaN) layer. The energy gap of GaN is about 3.4eV. The thickness of the nitride semiconductor layer 40 may range, but is not limited to, about 0.5 μm to about 10 μm.

The nitride semiconductor layer 60 (which may also be called the third nitride semiconductor layer 60 or the barrier layer 60 ) may be disposed on the nitride semiconductor layer 40 . The nitride semiconductor layer 60 may include a III-V group material layer. The nitride semiconductor layer 60 may include, but is not limited to, Group III nitride, such as the compound In _a Al _b Ga _(1-ab) N, where a+b≦1. The Group III nitride may further include, but is not limited to, for example, the compound Al _a Ga _(1-a) N, where a≦1. The forbidden band width (energy gap) of the nitride semiconductor layer 60 may be larger than the forbidden band width (energy gap) of the nitride semiconductor layer 40 . The nitride semiconductor layer 60 may include an aluminum gallium nitride (AlGaN) layer. The energy gap of AlGaN is approximately 4.0 eV. The thickness of the nitride semiconductor layer 60 may range from, but is not limited to, about 10 nm to about 100 nm.

A heterojunction is formed between the nitride semiconductor layer 60 and the nitride semiconductor layer 40 . Since the bandgap of the nitride semiconductor layer 60 is larger than the bandgap of the nitride semiconductor layer 40 , free charges are transferred from the nitride semiconductor layer 60 to the nitride semiconductor layer 40 , causing polarization at the heterojunction interface ( polarization), resulting in electrons overflowing from the wide-bandgap nitride semiconductor layer 60, leaving only positive charges (donor ions). These space charges generate electrostatic potential, which leads to energy band bending and the formation of a heterojunction junction. A two-dimensional potential well. This two-dimensional potential well can confine electrons induced by polarization, and these electrons can move two-dimensionally in the potential well along a plane parallel to the interface between the nitride semiconductor layer 60 and the nitride semiconductor layer 40 Movement, thereby accumulating charges at the interface between the nitride semiconductor layer 60 and the nitride semiconductor layer 40 to form a two-dimensional electron gas (two dimentional electron gas, 2DEG). 2DEG can have very high electron mobility. In some embodiments, the nitride semiconductor layer 60 with a larger bandgap than the nitride semiconductor layer 40 can be used as a barrier layer in the semiconductor device 100 . In some embodiments, compared to the nitride semiconductor layer 60 , the nitride semiconductor layer 40 having a smaller bandgap can provide a channel for carriers and serve as a channel layer in the semiconductor device 100 .

Since there is severe alloy disorder scattering at the interface between the nitride semiconductor layer 60 and the nitride semiconductor layer 40 , the electron mobility of the actual semiconductor device 100 is relatively low. In order to improve the electron mobility, the nitride semiconductor layer 50 (also called the second nitride semiconductor layer 50 or the insertion layer 50 ) can be provided between the nitride semiconductor layer 60 and the nitride semiconductor layer 40 .

The nitride semiconductor layer 50 may include a III-V group material layer. The nitride semiconductor layer 50 may include, but is not limited to, Group III nitride, such as aluminum nitride (AlN). The thickness of the nitride semiconductor layer 50 may range, but is not limited to, about 0.5 μm to about 10 μm.

In the related art, the nitride semiconductor layer 50 used to improve electron mobility is a whole layer. However, this will lead to defects such as increased concentration of two-dimensional electron gas (2DEG) in enhancement-mode semiconductor devices, easy punch-through of the device, and reduced breakdown voltage.

In order to suppress or avoid the above defects, the nitride semiconductor layer 50 in the embodiment of the present disclosure is not a whole layer, but includes first insertion blocks 52 and second insertion blocks 54 arranged at intervals. There is a gap (not labeled in the figure) between the first insertion block 52 and the second insertion block 54 . In some embodiments, first insert 52 is located beneath electrode 70 . In some embodiments, the second insert 54 is located beneath the electrode 90 . In some embodiments, the gap between first insert 52 and second insert 54 is located below gate 84 .

At least a portion of the nitride semiconductor layer 60 disposed on the nitride semiconductor layer 50 may be filled in the gap between the first insertion block 52 and the second insertion block 54 . Correspondingly, the nitride semiconductor layer 60 includes a protruding portion 63 and a main body portion 61 . The protruding portion 63 is filled in the gap between the first inserting block 52 and the second inserting block 54 , and the main body portion 61 is located above the first inserting block 52 , the protruding portion 63 and the second inserting block 54 .

An electrode 70 (or source electrode 70 ) may be disposed on the nitride semiconductor layer 60 . The electrode 70 may be in contact with the nitride semiconductor layer 60 . Electrode 70 may include, for example, but not limited to, a conductive material. The conductive material may include metals, alloys, doped semiconductor materials (eg, doped crystalline silicon), or other suitable conductive materials, such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN, or other suitable materials . Electrode 70 may be electrically connected to ground. Electrode 70 may be electrically connected to virtual ground. Electrode 70 may be electrically connected to true ground.

An electrode 90 (or drain electrode 90 ) may be disposed on the nitride semiconductor layer 60 . The electrode 90 may be in contact with the nitride semiconductor layer 60 . Electrode 90 may include, for example, but not limited to, a conductive material. The conductive material may include metals, alloys, doped semiconductor materials (eg, doped crystalline silicon), or other suitable conductive materials, such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN, or other suitable materials .

Depletion layer 82 may be disposed on nitride semiconductor layer 60 . The depletion layer 82 may be in direct contact with the nitride semiconductor layer 60 . Depletion layer 82 may be doped with impurities. Depletion layer 82 may contain p-type dopants. After careful consideration, the depletion layer 82 may include a p-doped GaN layer, a p-doped AlGaN layer, a p-doped AlN layer, or other suitable III-V group layers. The p-type dopant may include magnesium (Mg), beryllium (Be), zinc (Zn), and cadmium (Cd).

Depletion layer 82 may be configured to control the concentration of 2DEG in nitride semiconductor layer 40 . Depletion layer 82 may be used to deplete the 2DEG directly beneath depletion layer 82 .

Gate 84 may be disposed on depletion layer 82 . Gate 84 may include gate material. Gate metals may include titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), Molybdenum (Mo) and its compounds (such as but not limited to titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides or conductive oxides), metal alloys (such as aluminum-copper alloy (Al-Cu)) or Other suitable materials.

Electrode 70 and electrode 90 may be disposed on opposite sides of gate 84 . Although electrode 70 and electrode 90 are disposed on two opposite sides of gate 84 in FIG. 1 , electrode 70 , electrode 90 and gate 84 may have different configurations in other embodiments of the present disclosure due to design requirements.

However, although not shown in Figure 1, upon careful consideration, the structure of electrode 70 may be varied or altered in some other embodiments of the present disclosure. However, although not shown in Figure 1, upon careful consideration, the structure of electrode 90 may be varied or altered in some other embodiments of the present disclosure. For example, a portion of electrode 70 may be positioned in or extend in nitride semiconductor layer 60 . A portion of the electrode 90 may be positioned in the nitride semiconductor layer 60 or extend in the nitride semiconductor layer 60 . The electrode 70 may be disposed on the nitride semiconductor layer 50 . The electrode 90 may be disposed on the nitride semiconductor layer 50 . The electrode 70 may penetrate the nitride semiconductor layer 50 to contact the nitride semiconductor layer 40 . The electrode 90 may penetrate the nitride semiconductor layer 50 to contact the nitride semiconductor layer 40 .

In some embodiments, the semiconductor device 100 may further include a blocking layer (or hole blocking layer) (not shown in the figure). A barrier layer may be disposed between the gate electrode 84 and the nitride semiconductor layer 60 . A barrier layer may be disposed between gate 84 and depletion layer 82 . Depletion layer 82 may be separated from gate 84 by a barrier layer. A barrier layer may be disposed on depletion layer 82 . Gate 84 may be disposed on the barrier layer. Gate 84 may be in contact with the barrier layer. Gate 84 may cover the barrier layer. Gate 84 may completely cover the barrier layer.

The energy gap of the barrier layer may be larger than the energy gap of the nitride semiconductor layer 60 . The barrier layer may have an energy gap of about 4.0 eV to about 4.5 eV. The barrier layer may have an energy gap of about 4.5 eV to about 5.0 eV. The barrier layer may have an energy gap of about 5.0 eV to about 5.5 eV. The barrier layer may have an energy gap of about 5.5 eV to about 6.0 eV. The barrier layer may contain gallium. The barrier layer may include gallium oxide. Gallium oxide may contain Ga ₂ O ₃ . The barrier layer may include gallium oxynitride. Gallium oxynitride may include GaO _x N _(1-x) , where 0<x<1. The barrier layer may contain diamond. The barrier layer may include aluminum nitride. Barrier layers can contain combinations thereof. The energy gap of the barrier layer may be greater than the energy gap of depletion layer 82 .

Gate 84, barrier layer and depletion layer 82 may form a metal-insulator-semiconductor (MIS) structure. The MIS structure can help reduce leakage current and enhance breakdown voltage. Therefore, the gate voltage swing of the semiconductor device 100 can be improved.

Figure 2 is a cross-sectional view of a semiconductor device 200 in accordance with some embodiments of the present disclosure. In the embodiment of FIG. 2 , the orthographic projection of the gap between the first insertion block 52 and the second insertion block 54 on the substrate 10 does not completely coincide with the orthographic projection of the gate electrode 84 on the substrate 10 . In the orthographic projection direction, there is a gap between the right side of the first insertion block 52 and the left side of the grid 84 , and the left side of the second insertion block 54 coincides with the right side of the grid 84 .

Figure 3 is a cross-sectional view of a semiconductor device 300 in accordance with some embodiments of the present disclosure. In the embodiment of FIG. 3 , the orthographic projection of the gap between the first insertion block 52 and the second insertion block 54 on the substrate 10 does not completely coincide with the orthographic projection of the gate electrode 84 on the substrate 10 . In the orthographic projection direction, the right side of the first insertion block 52 coincides with the left side of the grid 84 , and there is a gap between the left side of the second insertion block 54 and the right side of the grid 84 .

Figure 4 is a cross-sectional view of a semiconductor device 400 in accordance with some embodiments of the present disclosure. In the embodiment of FIG. 4 , the orthographic projection of the gap between the first insertion block 52 and the second insertion block 54 on the substrate 10 does not completely coincide with the orthographic projection of the gate electrode 84 on the substrate 10 . In the orthographic projection direction, there is a gap between the right side of the first insertion block 52 and the left side of the grid 84 , and there is a gap between the left side of the second insertion block 54 and the right side of the grid 84 .

5-10 illustrate various stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure.

Referring to Figure 5, a substrate 10 is provided. A nucleation layer 20 , a buffer layer 30 , a nitride semiconductor layer 40 and an insertion material layer 503 may be formed on the substrate 10 . The nucleation layer 20 , the buffer layer 30 , the nitride semiconductor layer 40 and the insertion material layer 503 may be formed by, for example, metal organic chemical vapor deposition (MOCVD), epitaxial growth or other suitable deposition steps.

The substrate 10 may include, but is not limited to, silicon (Si), doped silicon (doped Si), silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs) or other semiconductor materials. The substrate 10 may include, but is not limited to, sapphire, silicon on insulator (SOI), or other suitable materials. In some embodiments, the substrate 10 may also include a doped region (not shown in the figure), such as a p-well (p-well), an n-well (n-well), etc.

Nucleation layer 20 may be formed on substrate 10 . Nucleation layer 20 may form an interface with substrate 10 . Nucleation layer 20 is configured to provide a top surface for growth of Group III nitride material thereon. In other words, nucleation layer 20 forms a suitable template for transitioning from the substrate's crystal lattice to one more suitable for growth of Group III nitride materials. Nucleation layer 20 may provide a transition to accommodate mismatches/differences between substrate 10 and the III nitride layer to be formed on its top surface (eg, epitaxially formed). The mismatch/difference may involve different lattice constants or thermal expansion coefficients. Mismatch/differences can lead to dislocations in the formation layer, thereby reducing the yield rate. Exemplary materials for nucleation layer 20 may include, but are not limited to, aluminum nitride (AlN) or any alloy thereof. The aluminum nitride may be, for example, but not limited to, doped n-type, p-type, or intrinsic. The material of the nucleation layer can be selected to eliminate mismatch/differences. For example, to accommodate mismatches/differences due to the first element in the layer to be formed on the nucleation layer, nucleation layer 20 is formed to include the first element.

The buffer layer 30 may be formed on the nucleation layer 20 . The buffer layer 30 may form an interface with the nucleation layer 20 . Buffer layer 30 has a bottommost surface in contact with nucleation layer 20 . The interface is formed by the bottommost surface of the buffer layer 30 and the topmost surface of the nucleation layer 20 . The buffer layer 30 has a topmost surface opposite a bottommost surface. Buffer layer 30 is configured to reduce lattice mismatch and thermal mismatch between the underlying layer and layers to be formed (eg, epitaxially formed thereon) on buffer layer 30, thereby curing defects due to mismatch/disparity.

Buffer layer 30 may include III-V compounds. III-V compounds may include, but are not limited to, aluminum, gallium, indium, nitrides, or combinations thereof. Accordingly, exemplary materials of buffer layer 30 may further include, for example, but not limited to, AlN, AlGaN, InAlGaN, GaAs, AlAs, ZnO, or combinations thereof. In some embodiments, buffer layer 30 may include two Group III elements, and the nucleation layer has only one Group III element. For example, the nucleation layer includes a compound containing aluminum and not containing gallium (eg, AlN), and the buffer layer 30 includes a III-V compound containing aluminum and gallium (eg, AlGaN).

The nitride semiconductor layer 40 (which may also be called the first nitride semiconductor layer 40 or the channel layer 40 ) may be formed on the buffer layer 30 . The nitride semiconductor layer 40 may include a III-V group material layer. The nitride semiconductor layer 40 may include, but is not limited to, Group III nitride, such as the compound In _a Al _b Ga _(1-ab) N, where a+b≦1. The Group III nitride further includes, but is not limited to, for example, the compound _Ala Ga _(1-a) N, where a≦1. The nitride semiconductor layer 40 may include a gallium nitride (GaN) layer. The energy gap of GaN is about 3.4eV. The thickness of the nitride semiconductor layer 40 may range, but is not limited to, about 0.5 μm to about 10 μm.

The insertion material layer 503 may be formed on the nitride semiconductor layer 40 . Insertion material layer 503 may include a layer of III-V material. Insertion material layer 503 may include, but is not limited to, Group III nitride, such as aluminum nitride (AlN). The thickness of the insert material layer 503 may range, but is not limited to, about 0.5 μm to about 10 μm.

Referring to FIG. 6 , a portion of the insertion material layer 503 (a portion located under the gate electrode 84 ) may be removed by selective etching, thereby forming the insertion layer 50 . In some embodiments, the insertion layer 50 includes first insertion blocks 52 and second insertion blocks 54 that are spaced apart. There is a gap between the first insertion block 52 and the second insertion block 54 .

Referring to FIG. 7 , a nitride semiconductor layer 60 may be formed on the insertion layer 50 . A portion of the nitride semiconductor layer 60 may be filled in the gap between the first insertion block 52 and the second insertion block 54 . Correspondingly, the nitride semiconductor layer 60 includes a protruding portion 63 and a main body portion 61 . The protruding portion 63 is filled in the gap between the first inserting block 52 and the second inserting block 54 , and the main body portion 61 is located above the first inserting block 52 , the protruding portion 63 and the second inserting block 54 .

The nitride semiconductor layer 60 (which may also be called the third nitride semiconductor layer 60 or the barrier layer 60 ) may include a III-V group material layer. The nitride semiconductor layer 60 may include, but is not limited to, Group III nitride, such as the compound In _a Al _b Ga _(1-ab) N, where a+b≦1. The Group III nitride may further include, but is not limited to, for example, the compound Al _a Ga _(1-a) N, where a≦1. The forbidden band width (energy gap) of the nitride semiconductor layer 60 may be larger than the forbidden band width (energy gap) of the nitride semiconductor layer 40 . The nitride semiconductor layer 60 may include an aluminum gallium nitride (AlGaN) layer. The energy gap of AlGaN is approximately 4.0 eV. The thickness of the nitride semiconductor layer 60 may range from, but is not limited to, about 10 nm to about 100 nm.

Referring to FIG. 8 , a depletion material layer 820 may be formed on the nitride semiconductor layer 60 . The depletion material layer 820 may be in direct contact with the nitride semiconductor layer 60 . Depletion material layer 820 may be doped with impurities. Depletion material layer 820 may include p-type dopants. Depletion material layer 820 may include a p-doped GaN layer, a p-doped AlGaN layer, a p-doped AlN layer, or other suitable III-V layer. The p-type dopant may include magnesium (Mg), beryllium (Be), zinc (Zn), and cadmium (Cd).

Referring to FIG. 9 , a portion of the depletion material layer 820 may be removed by selective etching, thereby forming the depletion layer 82 .

Referring to FIG. 10 , electrode 70 , electrode 90 and gate electrode 84 may be formed on nitride semiconductor layer 60 and depletion layer 82 to form a semiconductor device that is the same as or similar to semiconductor device 100 as described and illustrated in FIG. 1 .

Among them, the electrode 70 (or source electrode 70) may be formed on the nitride semiconductor layer 60. The electrode 70 may be in contact with the nitride semiconductor layer 60 . Electrode 70 may include, for example, but not limited to, a conductive material. The conductive material may include metals, alloys, doped semiconductor materials (eg, doped crystalline silicon), or other suitable conductive materials, such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN, or other suitable materials .

An electrode 90 (also called a drain electrode 90 ) may be formed on the nitride semiconductor layer 60 . The electrode 90 may be in contact with the nitride semiconductor layer 60 . Electrode 90 may include, for example, but not limited to, a conductive material. The conductive material may include metals, alloys, doped semiconductor materials (eg, doped crystalline silicon), or other suitable conductive materials, such as Ti, Al, Ni, Cu, Au, Pt, Pd, W, TiN, or other suitable materials .

Gate 84 may be formed on depletion layer 82 . Gate 84 may include gate material. Gate metals may include titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), Molybdenum (Mo) and its compounds (such as but not limited to titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides or conductive oxides), metal alloys (such as aluminum-copper alloy (Al-Cu)) or Other suitable materials.

For convenience of description, spatially relative terms such as "below", "below", "lower part", "above", "upper part", "lower part", "left side", "right side", etc. may be used herein. Terms used to describe the relationship of one element or feature to another element or feature or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 80 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.

As used herein, the terms "approximately," "substantially," "substantially," and "approximately" are used to describe and explain small variations. When used in connection with an event or situation, the terms may refer to instances of the exact occurrence of the event or situation as well as instances of near occurrence of the event or situation. As used herein with respect to a given value or a given range, the term "about" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed in this article as one endpoint to the other endpoint or as between two endpoints. All ranges disclosed herein are inclusive of the endpoints unless otherwise indicated. The term "substantially coplanar" may mean that two surfaces are located within a few micrometers (μm) of a position along the same plane, such as within 10 μm, 5 μm, 1 μm, or 0.5 μm of a difference in position along the same plane. When a value or property is referred to as being "substantially" the same, the term may refer to a value that is within ±10%, ±5%, ±1%, or ±0.5% of the mean of the stated values.

The foregoing summary summarizes features of several embodiments and detailed aspects of the disclosure. The embodiments described in this disclosure may readily serve as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or achieving the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the disclosure, and various changes, substitutions and alterations may be made without departing from the spirit and scope of the disclosure.

Claims (20)

1. A semiconductor device, the semiconductor device comprising:

a substrate;

a channel layer disposed on the substrate, the channel layer comprising a nitride semiconductor material;

a barrier layer disposed on a side of the channel layer remote from the substrate, the barrier layer comprising a nitride semiconductor material and having an energy gap greater than an energy gap of the channel layer;

the grid electrode is arranged on one side of the barrier layer, which is far away from the channel layer;

an insertion layer is arranged between the channel layer and the barrier layer, and a gap is arranged in a region corresponding to the grid electrode.

2. The semiconductor device according to claim 1, wherein the interposer layer includes first and second interposer blocks arranged at intervals, the gap being provided between the first and second interposer blocks.

3. The semiconductor device of claim 2, further comprising a source and a drain disposed on a side of the barrier layer remote from the channel layer, the source and drain being on opposite sides of the gate.

4. A semiconductor device according to claim 3, wherein there is at least a partial overlap between the orthographic projection of the first interposer on the substrate and the orthographic projection of the source on the substrate;

there is at least a partial overlap between the orthographic projection of the second insert onto the substrate and the orthographic projection of the drain onto the substrate.

5. A semiconductor device according to claim 3, wherein the orthographic projection of the gap onto the substrate partially overlaps and fully coincides with the orthographic projection of the gate onto the substrate.

6. The semiconductor device according to claim 3, wherein the barrier layer includes a protruding portion and a body portion, wherein the protruding portion is filled in the gap between the first insertion block and the second insertion block, and wherein the body portion is located above the first insertion block, the protruding portion, and the second insertion block.

7. The semiconductor device according to claim 1, wherein the channel layer includes a compound In _a Al _b Ga _(1-a-b) N, wherein a+b is less than or equal to 1;

alternatively, the channel layer includes a compound Al _a Ga _(1-a) N, wherein a is less than or equal to 1.

8. The semiconductor device according to claim 1, wherein the barrier layer includes a compound In _a Al _b Ga _(1-a-b) N, wherein a+b is less than or equal to 1;

alternatively, the barrier layer comprises a compound Al _a Ga _(1-a) N, wherein a is less than or equal to 1.

9. The semiconductor device of claim 1, wherein the material of the interposer comprises a group III-V material;

alternatively, the material of the insertion layer includes a group III nitride.

10. The semiconductor device according to claim 1, wherein a material of the channel layer comprises gallium nitride, a material of the barrier layer comprises aluminum gallium nitride, and a material of the insertion layer comprises aluminum nitride.

11. The semiconductor device of claim 1, further comprising a buffer layer disposed between the substrate and the channel layer, the buffer layer comprising a III-V compound.

12. The semiconductor device of claim 11, wherein the material of the buffer layer comprises AlN, alGaN, inAlGaN, gaAs, alAs, znO or a combination thereof.

13. The semiconductor device of claim 1, further comprising a nucleation layer disposed between the substrate and the channel layer.

14. The semiconductor device according to claim 1, further comprising a depletion layer disposed between the barrier layer and the gate.

15. The semiconductor device of claim 14, wherein the depletion layer comprises a p-type dopant.

16. A method of manufacturing a semiconductor device, the method comprising:

providing a substrate;

forming a channel layer on the substrate, the channel layer comprising a nitride semiconductor material;

forming an insertion layer on the channel layer, wherein a gap is arranged in the insertion layer;

forming a barrier layer on the insertion layer, the barrier layer including a nitride semiconductor material, and an energy gap of the barrier layer being greater than an energy gap of the channel layer;

a gate is formed on the barrier layer, the gate being located over the gap.

17. The method of manufacturing of claim 16, wherein the step of forming the interposer includes:

forming an insertion material layer on the channel layer;

and removing a part of the area of the insertion material layer by means of selective etching to form an insertion layer.

18. The method of claim 17, wherein the material of the interposer comprises a group III-V material;

alternatively, the material of the insertion layer includes a group III nitride.

19. The method of claim 16, wherein the material of the channel layer comprises gallium nitride, the material of the barrier layer comprises aluminum gallium nitride, and the material of the insert layer comprises aluminum nitride.

20. The method of manufacturing of claim 16, wherein a depletion layer is formed on the barrier layer prior to forming the gate, the depletion layer comprising a p-type dopant.