CN117373915B - Semiconductor structure thinning method and structure - Google Patents

Abstract

The present application relates to a semiconductor structure thinning method and structure, comprising: providing a carrier wafer and a device wafer, wherein the device wafer comprises a doped substrate and an epitaxial layer and a device layer located on the front side of the doped substrate, bonding the top surface of the device layer to the front side of the carrier wafer, and then removing the main part of the doped substrate in the device wafer in a direction perpendicular to the substrate to obtain a residual doped substrate, wherein the thickness of the main part of the doped substrate is greater than half the thickness of the doped substrate, injecting a thermal radiation wave through the top surface of the residual doped substrate at room temperature, so that the temperature of the residual doped substrate is increased to a target temperature, and the epitaxial layer of the device wafer is kept at room temperature, and finally wet etching and removing the residual doped substrate, thereby improving the etching selectivity, simplifying the method for improving the etching selectivity, reducing the economic cost of etching in a back-illuminated semiconductor structure, and reducing pollution to the environment.

Description

Semiconductor structure thinning method and structure

Technical Field

The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure thinning method and structure.

Background technique

A complementary metal oxide semiconductor (CMOS) image sensor is a sensor that can convert the color and brightness of captured light into electronic signals and transmit the electronic signals to a processor. Based on the incident direction of light, CMOS image sensors can be divided into front-side illumination (FSI) complementary metal oxide semiconductor image sensors and back-side illumination (BSI) complementary metal oxide semiconductor image sensors.

In the manufacturing process of BSI CMOS, the device wafer that has completed the front process needs to be thinned. In order to avoid damaging the epitaxial layer while etching the substrate layer, the etchant needs to have a large etching selectivity between the substrate layer and the epitaxial layer. In order to ensure a large etching selectivity, most of the current etching solutions are expensive and complex in composition, with a short life of the solution, high etching cost, and uneven surface after etching. How to reduce the etching cost in back-illuminated semiconductor structures is one of the problems that need to be solved urgently.

Summary of the invention

Based on this, it is necessary to provide a semiconductor structure thinning method and structure to address the problem of high etching cost of back-illuminated semiconductor structures in the prior art.

In order to achieve the above-mentioned objectives, on the one hand, the present application provides a method for thinning a semiconductor structure, comprising: providing a carrier wafer and a device wafer, the device wafer comprising a doped substrate and an epitaxial layer and a device layer sequentially located on the front side of the doped substrate; bonding the top surface of the device layer to the front side of the carrier wafer; removing the main portion of the doped substrate in the device wafer in a direction perpendicular to the substrate to obtain a residual doped substrate after thinning, wherein the thickness of the main portion of the doped substrate is greater than half the thickness of the doped substrate before thinning; injecting a thermal radiation wave through the top surface of the residual doped substrate at room temperature, so that the temperature of the residual doped substrate is raised to the target temperature, and the epitaxial layer of the device wafer is maintained at room temperature; and wet etching and removing the residual doped substrate.

In the above embodiment, a carrier wafer and a device wafer are first provided, wherein the device wafer includes a doped substrate and an epitaxial layer and a device layer located on the front side of the doped substrate, the top surface of the device layer is bonded to the front side of the carrier wafer, and then the main part of the doped substrate in the device wafer is removed along a direction perpendicular to the substrate to obtain a residual doped substrate, wherein the thickness of the main part of the doped substrate is greater than half the thickness of the doped substrate, and a thermal radiation wave is injected through the top surface of the residual doped substrate at room temperature so that the temperature of the residual doped substrate is increased to a target temperature, and the epitaxial layer of the device wafer is maintained at room temperature, and finally the residual doped substrate is wet-etched and removed, and a temperature difference is generated between the residual doped substrate and the epitaxial layer by injecting thermal radiation waves, and then the residual doped substrate is removed by wet etching, and the etching rates of wet etching at different temperatures are different, so as to improve the etching selectivity and reduce the economic cost of etching in the back-illuminated semiconductor structure.

In one embodiment, the semiconductor structure thinning method includes: the thermal radiation wave includes at least one of infrared, ultraviolet and microwave.

In one embodiment, a semiconductor structure thinning method includes: doping a substrate with doping ions including at least one of boron ions, gallium ions, aluminum ions, and indium ions.

In one embodiment, removing the main portion of the doped substrate along a direction perpendicular to the substrate includes: removing the main portion of the doped substrate along a direction perpendicular to the substrate by using a chemical mechanical polishing process and/or a wet etching process.

In one embodiment, the semiconductor structure thinning method includes: using a first chemical solution to wet etch and remove the main part of the doped substrate; wet etching and removing the residual doped substrate, including: using a second chemical solution to wet etch and remove the residual doped substrate; the second chemical solution has a higher etching rate for the residual doped substrate than for the epitaxial layer of the device wafer.

In one embodiment, the semiconductor structure thinning method includes: the second chemical solution is obtained by diluting the first chemical solution m times with water, where m>2.

In one embodiment, the semiconductor structure thinning method includes: the etching rate of the second chemical solution on the residual doped substrate is related to m, and the etching rate of the first chemical solution on the residual doped substrate; and the etching rate of the second chemical solution on the epitaxial layer of the device wafer is related to m, and the etching rate of the first chemical solution on the epitaxial layer of the device wafer.

In one embodiment, the semiconductor structure thinning method includes: the thickness of the main portion of the doped substrate is 0.7 times to 0.999 times the thickness of the doped substrate.

In one embodiment, a semiconductor structure thinning method includes: raising the temperature of a residual doped substrate to a target temperature, wherein the target temperature is 30° C. to 100° C.

The present disclosure also provides a semiconductor structure, which is prepared using the semiconductor structure thinning method in any one of the embodiments of the present disclosure.

The semiconductor structure thinning method and structure disclosed in the present invention have the following unexpected beneficial effects:

In the semiconductor structure thinning method and structure disclosed in the present invention, a carrier wafer and a device wafer are first provided, the device wafer includes a doped substrate and an epitaxial layer and a device layer located on the front of the doped substrate, the top surface of the device layer is bonded to the front of the carrier wafer, and then chemical mechanical grinding or wet etching is used to remove the main part of the doped substrate in the device wafer in a direction perpendicular to the substrate, reducing the etching time to obtain a residual doped substrate, injecting a thermal radiation wave through the top surface of the residual doped substrate at room temperature, using the different characteristics of different doping concentrations The absorption capacity increases the temperature of the residual doped substrate to the target temperature, and the epitaxial layer of the device wafer is kept at room temperature, so that the residual doped substrate and the epitaxial layer have a temperature difference, and finally the diluted second chemical solution is used for wet etching, and the residual doped substrate is removed. The etching selectivity is improved by the temperature difference, the method of improving the etching selectivity is simplified, and the damage to the epitaxial layer is avoided while reducing the high requirements for the etchant, and the etching is carried out by using the diluted second chemical solution, which further reduces the economic cost and reduces the pollution to the environment.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

FIG1 is a schematic flow chart of a method for thinning a back-illuminated semiconductor structure provided in one embodiment;

FIG2 is a schematic diagram of a film layer structure of a device wafer provided in an embodiment;

FIG3 is a schematic diagram of bonding a device wafer and a carrier wafer provided in an embodiment;

FIG4 is a schematic cross-sectional structure diagram of step S430 in a back-illuminated semiconductor structure thinning method provided in one embodiment;

FIG5 is a schematic cross-sectional view of step S440 in a back-illuminated semiconductor structure thinning method provided in one embodiment;

FIG6 is a schematic diagram of a back-illuminated semiconductor structure provided in one embodiment;

FIG. 7 is a schematic diagram of a specific implementation process of thinning a back-illuminated semiconductor structure provided in one embodiment.

Description of reference numerals:

100, device wafer; 110, substrate layer; 111, residual doped substrate; 120, epitaxial layer; 130, device layer; 200, carrier wafer.

Detailed ways

In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

It should be understood that when an element or layer is referred to as being "on, "adjacent to, "connected to, or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, "directly adjacent to, "directly connected to, or "directly coupled to" other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and/or portions, these elements, components, regions, layers, doping types, and/or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

When used herein, the singular forms "a", "an", and "said/the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and/or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and/or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and/or groups is not excluded. At the same time, when used herein, the term "and/or" includes any and all combinations of the relevant listed items.

Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and/or tolerances are anticipated. Accordingly, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

Typically, in the preparation of a back-illuminated semiconductor structure, an epitaxial layer is first grown on a substrate by a deposition process, and then a corresponding device layer is fabricated on the epitaxial layer according to device requirements to form a device wafer, the device wafer is flipped over so that the top surface of the device layer is bonded to the front surface of the carrier wafer, and then the substrate layer of the device wafer is thinned until all substrate layers are removed, while the thickness of the epitaxial layer must be ensured, and finally a back-illuminated semiconductor structure that meets the requirements is formed. In order to ensure that the substrate layer is etched while avoiding etching of the epitaxial layer, the etching solution used for etching should have a large etching selectivity ratio. The existing etching solution has complex components, a short solution life, a high economic cost of the etching solution, and a low surface flatness after etching.

Referring to FIG. 1 to FIG. 6 , in some embodiments, the present disclosure provides a method for thinning a back-illuminated semiconductor structure, comprising the following steps:

Step S410: providing a carrier wafer 200 and a device wafer 100 , wherein the device wafer 100 includes a doped substrate (substrate layer 110 ) and an epitaxial layer 120 and a device layer 130 sequentially located on the front side of the doped substrate.

In the above steps, the material used for the substrate of the device wafer 100 may be a semiconductor material, an insulating material, a conductor material or any combination thereof. The substrate may be a single-layer structure or a multi-layer structure. For example, the substrate may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III/V semiconductor substrates or II/VI semiconductor substrates. Alternatively, for example, the substrate may be a layered substrate including Si/SiGe, Si/SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate should not limit the scope of protection of the present disclosure. The doping concentration of the doped substrate should be high-concentration doping, for example, the doping concentration may be between 10 ¹⁶ cm ^-3 and 10 ¹⁸ cm ^-3 , this range is only used as an example, and other doping concentrations may also be used in other embodiments. In addition, the thickness of the doped substrate may be 600 microns to 800 microns, for example, 630 microns, 650 microns, 700 microns, 730 microns, 750 microns, 780 microns, etc. The material of the epitaxial layer 120 may be a semiconductor material such as Si or Ge, and the epitaxial layer 120 should be doped at a low concentration, with a doping concentration much lower than that of the doped substrate, and the thickness of the epitaxial layer 120 may be 4 microns to 10 microns, for example, 5 microns, 7 microns, 8 microns, 9 microns, etc.

In the above steps, the preparation process of the device wafer 100 also includes pre-treating the substrate surface, using acidic, alkaline or ultrapure water and other agents to remove organic or inorganic impurities on the substrate surface, and hydrofluoric acid and other agents can also be used to remove surface oxides, and then the crystal structure foundation of the substrate surface is prepared by heat treatment or etching, and the pre-treatment effect is tested to ensure that the pre-treatment effect is achieved, and then select suitable epitaxial raw materials, such as silane, dimethylsilane, etc., inject the epitaxial raw materials into the reactor, and control the temperature, pressure, and gas flow to obtain an epitaxial layer 120 that meets the requirements. When the thickness of the epitaxial layer 120 meets the requirements, stop the growth of the epitaxial layer 120, and gradually cool the substrate to room temperature. The device layer 130 is made on the prepared epitaxial layer 120. The device layer 130 is mainly a photodiode array and a metal layer. In actual operation, the device layer 130 can be made according to different device requirements.

Step S420: Bonding the top surface of the device layer 130 to the front surface of the carrier wafer 200. The bonding of the top surface of the device layer 130 to the front surface of the carrier wafer 200 includes: placing the device wafer 100 and the carrier wafer 200 on an aligner, achieving precise alignment of the device wafer 100 and the carrier wafer 200 through an alignment system, applying a bonding adhesive, pressing the device wafer 100 and the carrier wafer 200, curing the bonded wafers at high temperature, and then performing an annealing process to remove stress and defects generated during the bonding process.

Step S430: removing the main portion of the doped substrate along a direction perpendicular to the substrate to obtain a thinned residual doped substrate.

In the above steps, dry etching such as mechanical grinding or wet etching can be used to remove the main part of the doped substrate to obtain the residual doped substrate 111. The thickness of the main part of the device wafer 100 is greater than half of the thickness of the doped substrate before thinning. Performing preliminary removal treatment on the doped substrate can increase the etching speed of the doped substrate and improve the etching efficiency.

Step S440 : injecting a thermal radiation wave through the top surface of the residual doped substrate 111 at room temperature, so that the temperature of the residual doped substrate 111 is increased to a target temperature, and the epitaxial layer 120 is kept at room temperature.

In the above steps, thermal radiation waves can be injected into the residual doped substrate 111 by top surface injection or side injection. Since the doping concentration of the residual doped substrate 111 is different from the doping concentration in the epitaxial layer 120, the difference in doping concentration will affect the band structure inside the semiconductor, thereby affecting the wave absorption capacity of the semiconductor material. The wave absorption capacity of the residual doped substrate 111 is stronger than that of the epitaxial layer 120. When heated by thermal radiation waves, a temperature difference can be generated between the residual doped substrate 111 and the epitaxial layer 120. The present application utilizes thermal radiation waves and the inherent characteristics of the residual doped substrate 111 and the epitaxial layer 120 to generate a temperature difference, simplifies the method of manufacturing the temperature difference, and reduces the complexity of improving the etching selectivity.

Step S450 : wet-etching and removing the remaining doped substrate 111 .

In the above steps, the solution used for wet etching can be an alkaline solution with selective etching characteristics, such as a hydrofluoric acid-nitric acid mixed solution, hydroiodic acid, and ammonia water. Since the etching rates of the etching solutions at different temperatures are different, the temperature difference between the residual doped substrate 111 and the epitaxial layer 120 can be used to increase the etching selectivity of the etching solution, thereby avoiding damage to the epitaxial layer 120 while etching the residual doped substrate 111.

In the above embodiment, a carrier wafer and a device wafer are provided, wherein the device wafer includes a doped substrate and an epitaxial layer and a device layer located on the front side of the doped substrate. The carrier wafer can support the device wafer after thinning to avoid the generation of broken pieces, and the epitaxial layer can be used as a reaction stop layer to avoid damage to the device layer during wet etching. The top surface of the device layer is bonded to the front side of the carrier wafer, and then the main part of the doped substrate in the device wafer is removed along a direction perpendicular to the substrate to obtain a residual doped substrate, wherein the thickness of the main part of the doped substrate is greater than half of the thickness of the doped substrate, and a part of the doped substrate is removed in advance to improve the etching efficiency, and then, by utilizing the different wave absorption capabilities of semiconductor materials with different doping concentrations, a thermal radiation wave is injected through the top surface of the residual doped substrate at room temperature, so that the temperature of the residual doped substrate is increased to the target temperature, and the epitaxial layer of the device wafer is kept at room temperature, and finally, by utilizing the different etching rates of wet etching at different temperatures, wet etching is used to remove the residual doped substrate, thereby improving the etching selectivity, reducing the complexity of improving the etching selectivity, and reducing the economic cost of etching in the back-illuminated semiconductor structure.

In one embodiment, a back-illuminated semiconductor structure thinning method includes: injecting a thermal radiation wave through a top surface of a residual doped substrate at room temperature, wherein the thermal radiation wave includes at least one of infrared, ultraviolet, and microwave.

In the above embodiments, in order to ensure the stability and accuracy of the heating process, the appropriate heating power and heating time may be set according to the characteristics of the device wafer, and the substrate temperature may be monitored in real time.

In one embodiment, the back-illuminated semiconductor structure thinning method includes: the doping ions of the doped substrate include at least one of boron ions, gallium ions, aluminum ions and indium ions. In addition, N-type ions may also be used for doping, such as one or more of phosphorus ions, arsenic ions or antimony ions.

In the above embodiments, the doping process for doping the doped substrate may include: thermal diffusion method, gas phase diffusion method and molecular beam epitaxy method. Among them, the thermal diffusion method is to diffuse the doping source material and the substrate material at high temperature so that the dopant is evenly distributed in the substrate. This method has a relatively shallow doping depth, but the control is relatively simple. It can be used when the device wafer size is small; the gas phase diffusion method relies on gas phase reaction for doping. By heating the doping source material, it is decomposed into gaseous dopants, and then the gaseous dopants are transported to the substrate surface. It is suitable for requirements with low doping concentration; and the molecular beam epitaxy method is to inject a molecular beam of the doping source material into the substrate surface through a molecular beam epitaxy device, which is suitable for high-precision doping. In actual production, the corresponding doping process can be adopted according to the characteristics and requirements of the device wafer.

In one embodiment, removing the main portion of the doped substrate along a direction perpendicular to the substrate includes: removing the main portion of the doped substrate along a direction perpendicular to the substrate by using a chemical mechanical polishing process and/or a wet etching process.

In the above embodiment, chemical mechanical polishing includes: determining appropriate polishing parameters, selecting polishing liquid according to the characteristics of the device wafer, selecting a polishing head according to the size and surface condition of the device wafer, for example, a hard polyurethane polishing head or a polypropylene polishing head can be selected, and finally performing a polishing process. During the polishing, a suitable rotation speed and polishing pressure are selected according to the size of the device wafer and the material of the substrate to improve the controllability of etching and increase the stability of the polishing effect.

In one embodiment, a method for thinning a back-illuminated semiconductor structure includes: wet etching and removing a main portion of a doped substrate using a first chemical solution; wet etching and removing the remaining doped substrate, including: wet etching and removing the remaining doped substrate using a second chemical solution; the etching rate of the second chemical solution on the remaining doped substrate is greater than the etching rate of the epitaxial layer of the device wafer.

In the above embodiment, the wet etching process includes: cleaning impurities on the surface of the doped substrate of the device wafer, placing the cleaned device wafer into an etching solution for etching, and the etching solution can be a hydrofluoric acid and nitric acid mixed solution, hydroiodic acid, ammonia water and other alkaline solutions with selective etching characteristics. For example, a hydrofluoric acid and nitric acid mixed solution is used, and the concentration of the solution is generally 5:1:1, that is, the volume ratio of HNO3:HF:HAc is 5:1:1, wherein HNO3 is nitric acid, HF is hydrofluoric acid, and HAc is acetic acid. The appropriate solution concentration is selected according to the required etching depth and substrate material, and stirring is performed while etching to ensure that the etching depth is 100%. To ensure that the etching solution evenly covers the surface of the doped substrate to enhance the etching effect, the reaction state needs to be observed in real time to avoid over-reaction or under-reaction. The etching thickness can be monitored by using instruments such as reflection spectroscopy, surface profiler or ellipsometer. For example, reflection spectroscopy is used to monitor the thickness change of the doped substrate layer during the etching process by measuring the reflectivity change of the doped substrate of the device wafer in the visible light or infrared range. As the etching depth increases, the reflection spectrum will change. The etching end point can be determined based on the characteristics of the change. When the etching thickness reaches the requirement, the etching is stopped to ensure the accuracy of the etching.

In one embodiment, a back-illuminated semiconductor structure thinning method includes: a second chemical solution is obtained by diluting a first chemical solution m times with water, where m>2. The use of the diluted second chemical solution can reduce the etching rate of the epitaxial layer, avoid damaging the epitaxial layer, improve the etching flatness, avoid the economic cost of etching with different chemical solutions, and reduce the pollution to the environment.

In one embodiment, a back-illuminated semiconductor structure thinning method includes: the etching rate of the second chemical solution on the residual doped substrate is related to m, and the etching rate of the first chemical solution on the residual doped substrate; and the etching rate of the second chemical solution on the epitaxial layer of the device wafer is related to m, and the etching rate of the first chemical solution on the epitaxial layer of the device wafer.

In the above embodiment, it can be known that when m is larger, the etching rate of the second chemical solution on the residual doped substrate and the epitaxial layer is lower, and the etching time is longer; in addition, the temperature also has a certain influence on the etching rate. When the concentration of the second chemical solution is constant, the higher the temperature, the higher the etching rate. Therefore, when the diluted second chemical solution is used to etch the residual doped substrate, since the etching rate of the diluted second chemical solution on the residual doped substrate and the epitaxial layer is lower, the concentration of the second chemical solution is kept unchanged, the residual doped substrate is heated by using thermal radiation waves, the temperature of the epitaxial layer is kept unchanged, and the temperature difference between the residual doped substrate and the epitaxial layer is used to reduce the etching rate of the epitaxial layer while increasing the etching rate of the second chemical solution on the residual doped substrate, thereby increasing the etching selectivity.

In one embodiment, the back-illuminated semiconductor structure thinning method includes: the thickness of the main body of the doped substrate is 0.7 times to 0.999 times the thickness of the doped substrate, for example: 0.7 times, 0.75 times, 0.8 times, 0.85 times, 0.9 times, 0.95 times, etc.

In one embodiment, a back-illuminated semiconductor structure thinning method includes: raising the temperature of the remaining doped substrate to a target temperature of 30°C to 100°C. For example: 35°C, 40°C, 45°C, 50°C, 55°C, 60°C, 65°C, 70°C, 75°C, 80°C, 85°C, 90°C, 95°C, etc. It can be seen that when the concentration of the second chemical solution remains unchanged, the higher the target temperature, the greater the etching selectivity, and the lower the destructiveness to the epitaxial layer. However, too high a temperature may affect the characteristic value of the device wafer. In other embodiments, the target temperature is not limited to the above-listed range, and a suitable target temperature can be selected according to actual needs and the dilution factor m.

Referring to FIG. 7 , the present disclosure further provides a back-illuminated semiconductor structure, which is prepared by the back-illuminated semiconductor structure thinning method in any one of the embodiments of the present disclosure, comprising:

Step S710: providing a carrier wafer and a device wafer, wherein the device wafer comprises a doped substrate and an epitaxial layer and a device layer located on the front side of the doped substrate, wherein the thickness of the doped substrate layer is 600 microns to 800 microns, and the thickness of the epitaxial layer is 4 microns to 10 microns.

Step S720: bonding the top surface of the device layer to the front surface of the carrier wafer.

Step S730: 70%-99.9% of the thickness of the doped substrate is removed in a direction perpendicular to the substrate to obtain a residual doped substrate. The doped substrate is roughly thinned using a hydrofluoric acid and nitric acid mixed solution. At room temperature, the hydrofluoric acid and nitric acid mixed solution used in this embodiment has an etching rate of 10 microns/minute for the doped substrate, an etching rate of 3 microns/minute for the epitaxial layer, and an etching selectivity of 3.3.

Step S740: inject infrared light through the top surface of the residual doped substrate at room temperature for heating, so that the temperature of the residual doped substrate rises to a target temperature and the epitaxial layer is kept at room temperature; wherein the target temperature may be 35°C.

Step S750: wet-etching and removing the remaining doped substrate to obtain a back-illuminated semiconductor structure.

In the above steps, the etching solution used for wet etching is a diluted hydrofluoric acid and nitric acid mixed solution, the dilution multiple is 5 times, and when diluted 5 times and without heating treatment, the etching rate of the hydrofluoric acid and nitric acid mixed solution on the residual doped substrate is 2.1 microns/minute, and the etching rate on the epitaxial layer is 0.5 microns/minute. When the residual doped substrate is heated to 35°C by infrared light, the etching rate of the wet etching solution on the residual doped substrate is 8 microns/minute, and the etching rate on the epitaxial layer is 0.5 microns/minute, and the etching selectivity is 16, which is significantly improved.

In the above embodiments, the unexpected technical effect of the present application is: by providing a carrier wafer and a device wafer, the device wafer includes a doped substrate and an epitaxial layer and a device layer located on the front side of the doped substrate, and after the top surface of the device layer is bonded to the front side of the carrier wafer, the doped substrate is firstly roughly thinned using a hydrofluoric acid and nitric acid mixed solution to remove 70%-99.9% of the thickness of the doped substrate to obtain a residual doped substrate, and then the residual doped substrate is infrared heated, and the hydrofluoric acid and nitric acid mixed solution is diluted, and the heated residual doped substrate is wet-etched using the diluted etching solution, thereby improving the etching selectivity while reducing the economic cost of the etching solution, and also reducing the etching rate of the epitaxial layer and improving the surface flatness.

It should be understood that, although the various steps in the flowcharts in FIG. 1 and FIG. 7 are displayed in sequence according to the indications of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in FIG. 1 and FIG. 7 may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims (10)

1. A method for thinning a semiconductor structure, characterized in that the method comprises: Providing a carrier wafer and a device wafer; the device wafer comprises a doped substrate and an epitaxial layer and a device layer sequentially located on the front of the doped substrate; wherein the material of the epitaxial layer comprises any semiconductor material of silicon or germanium, and the doping concentration of the epitaxial layer is less than the doping concentration of the doped substrate; the device layer comprises a photodiode array and a metal layer; Bonding the top surface of the device layer to the front surface of the carrier wafer; Removing the main body of the doped substrate in a direction perpendicular to the substrate to obtain a thinned residual doped substrate; the thickness of the main body is greater than half of the thickness of the doped substrate before thinning; the wave absorbing ability of the residual doped substrate is stronger than that of the epitaxial layer; Injecting thermal radiation waves through the top surface of the residual doped substrate at room temperature, so that the temperature of the residual doped substrate is increased to a target temperature, and the epitaxial layer is kept at room temperature; the target temperature is 30° C. to 100° C.; the thermal radiation waves include at least one of infrared, ultraviolet and microwave; The residual doped substrate is wet-etched and removed. 2 . The semiconductor structure thinning method according to claim 1 , wherein the doping concentration of the doped substrate is 10 ¹⁶ cm ⁻³ to 10 ¹⁸ cm ⁻³ . 3 . The semiconductor structure thinning method according to claim 1 , wherein the doping ions of the doped substrate include at least one of boron ions, gallium ions, aluminum ions and indium ions. 4. The semiconductor structure thinning method according to any one of claims 1 to 3, characterized in that the step of removing the main portion of the doped substrate along a direction perpendicular to the substrate comprises: A chemical mechanical polishing process and/or a wet etching process is adopted to remove the main part of the doped substrate along the direction perpendicular to the substrate. 5. The semiconductor structure thinning method according to any one of claims 1 to 3, characterized in that the main part of the doped substrate is removed by wet etching using a first chemical solution; the wet etching and removal of the remaining doped substrate comprises: The residual doped substrate is wet-etched and removed by using a second chemical solution; the etching rate of the residual doped substrate by the second chemical solution is greater than the etching rate of the epitaxial layer. 6. The semiconductor structure thinning method according to claim 5 is characterized in that the second chemical solution is obtained by diluting the first chemical solution m times with water; m>2. 7. The semiconductor structure thinning method according to claim 6, characterized in that the etching rate of the second chemical solution on the residual doped substrate is related to m, and the etching rate of the first chemical solution on the residual doped substrate is related to m; and The etching rate of the epitaxial layer by the second chemical solution is related to m, and the etching rate of the epitaxial layer by the first chemical solution is related to m. 8 . The semiconductor structure thinning method according to claim 1 , wherein the thickness of the main body portion is 0.7 to 0.999 times the thickness of the doped substrate. 9. The semiconductor structure thinning method according to any one of claims 1 to 3, characterized in that the thickness of the doped substrate is 600 microns to 800 microns; the thickness of the epitaxial layer is 4 microns to 10 microns. 10. A semiconductor structure, characterized in that it is manufactured by using the semiconductor structure thinning method according to any one of claims 1 to 9.