CN117348332B - Layout correction method, device, equipment and storage medium - Google Patents
Layout correction method, device, equipment and storage medium Download PDFInfo
- Publication number
- CN117348332B CN117348332B CN202311638969.7A CN202311638969A CN117348332B CN 117348332 B CN117348332 B CN 117348332B CN 202311638969 A CN202311638969 A CN 202311638969A CN 117348332 B CN117348332 B CN 117348332B
- Authority
- CN
- China
- Prior art keywords
- layout
- morphology
- hot spot
- target
- correction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012937 correction Methods 0.000 title claims abstract description 70
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000003860 storage Methods 0.000 title claims abstract description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 72
- 230000003287 optical effect Effects 0.000 claims abstract description 52
- 230000000694 effects Effects 0.000 claims abstract description 35
- 230000002159 abnormal effect Effects 0.000 claims abstract description 21
- 238000005520 cutting process Methods 0.000 claims abstract description 7
- 230000011218 segmentation Effects 0.000 claims description 19
- 238000002715 modification method Methods 0.000 claims description 13
- 230000008569 process Effects 0.000 abstract description 11
- 238000013461 design Methods 0.000 description 22
- 238000010586 diagram Methods 0.000 description 15
- 238000012545 processing Methods 0.000 description 11
- 239000007787 solid Substances 0.000 description 11
- 238000012986 modification Methods 0.000 description 9
- 230000004048 modification Effects 0.000 description 9
- 238000004590 computer program Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 5
- 238000012876 topography Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 238000004088 simulation Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000001902 propagating effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/30—Computing systems specially adapted for manufacturing
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
The application relates to a layout correction method, device, equipment and storage medium. The layout correction method comprises the following steps: acquiring a first layout and a first simulated photoresist morphology corresponding to the first layout, which are obtained after at least one optical proximity effect correction; determining a plurality of hot spot morphologies in the first simulated photoresist morphology; the hot spot morphology comprises at least one morphology meeting preset abnormal conditions; cutting a plurality of second layouts from the first layout, wherein each second layout comprises at least one hot spot layout, and each hot spot layout corresponds to one hot spot morphology; and carrying out optical proximity effect correction on the second layout to obtain a third layout, and updating the first layout by using the third layout to obtain the target layout. According to the method and the device, the debugging process is simplified, the operation time is shortened, and the efficiency is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a layout correction method, apparatus, device, and storage medium.
Background
The photoetching process is to transfer the pattern on the mask plate onto each structural layer of the wafer, and the principle is that the light propagates onto the structural layer after passing through the pattern on the mask plate, and the pattern on the mask plate is equivalent to the barrier on the propagation path, so that the pattern related to the pattern on the mask plate is obtained on the structural layer. When the line width of the pattern on the mask plate is gradually close to or even smaller than the exposure wavelength of the photoetching process, obvious diffraction and interference effects (namely optical proximity effects) are generated between adjacent patterns, so that the pattern actually reaching the structural layer is not identical with the pattern on the design layout (namely the mask plate), namely pattern transfer distortion is generated.
Therefore, in order to reduce distortion, an optical proximity correction technique (Optical Proximity Correction, abbreviated as OPC) is widely used for correcting a design layout of a mask. However, as the total area of the design layout increases, the size of the pattern decreases and becomes complicated, some places (for example, corrugated shapes) where the optical proximity effect is not converged after the optical proximity effect correction still appear when the design layout after the optical proximity effect correction is inspected, so that the whole design layout needs to be corrected again. When the surrounding environment of these places where convergence is still not yet achieved is complex, the process of re-correction of the entire design layout is complex to debug and the running time is long.
Disclosure of Invention
In view of this, embodiments of the present application provide a layout correction method, apparatus, device, and storage medium for solving at least one problem existing in the background art.
In a first aspect, an embodiment of the present application provides a layout modification method, including:
acquiring a first layout obtained after at least one optical proximity effect correction and a first simulated photoresist morphology corresponding to the first layout;
determining a plurality of hot spot morphologies in the first simulated photoresist morphology; one of the hotspot profiles comprises at least one profile meeting a preset abnormal condition;
a plurality of second layouts are segmented from the first layout, each second layout comprises at least one hot spot layout, and each hot spot layout corresponds to one hot spot morphology;
and carrying out optical proximity effect correction on the second layout to obtain a third layout, and updating the first layout by using the third layout to obtain a target layout.
With reference to the first aspect, in an optional implementation manner, the preset abnormal condition includes at least one of an edge placement error being greater than a first abnormal value and a pattern line width deviation being greater than a second abnormal value.
With reference to the first aspect, in an optional implementation manner, the splitting a plurality of second layouts from the first layout, where each second layout includes at least one hotspot layout, and each hotspot layout corresponds to one hotspot morphology, includes:
creating a plurality of rectangles having sides greater than or equal to four times the optical diameter;
the rectangle is taken as the boundary of the second layout, and the acquired first layout is segmented, so that a hot layout cluster corresponding to one hot morphology cluster is positioned in the middle of the rectangle, and a plurality of second layouts are acquired; the one hotspot morphology cluster comprises at least one hotspot morphology, and the minimum value of the distance between two adjacent hotspot morphology clusters is greater than or equal to a minimum distance threshold.
With reference to the first aspect, in an optional implementation manner, the updating the first layout with the third layout to obtain a target layout includes:
cutting off the edge of the preset width of the third layout to obtain a fourth layout;
and replacing the corresponding region in the first layout with the fourth layout to obtain a target layout.
With reference to the first aspect, in an optional implementation manner, the preset width is greater than or equal to one optical diameter.
With reference to the first aspect, in an optional implementation manner, the layout correction method further includes:
determining whether the second simulated photoresist morphology corresponding to the target layout contains the hot spot morphology;
and if the second simulated photoresist morphology corresponding to the target domain does not contain the hot spot morphology, obtaining a result of finishing the correction of the target domain and outputting the target domain.
With reference to the first aspect, in an optional implementation manner, the layout correction method further includes:
and if the second simulated photoresist morphology corresponding to the target domain contains the hot spot morphology, obtaining a result that the target domain is not corrected, and returning to the determination of a plurality of hot spot morphologies in the first simulated photoresist morphology to continue execution until obtaining the result that the target domain is corrected.
In a second aspect, an embodiment of the present application provides a layout correction device, including:
the acquisition unit is used for acquiring a first layout obtained after at least one optical proximity effect correction and a first simulated photoresist morphology corresponding to the first layout;
the first determining unit is used for determining a plurality of hot spot morphologies in the first simulated photoresist morphology; one of the hotspot profiles comprises at least one profile meeting a preset abnormal condition;
the segmentation unit is used for segmenting a plurality of second layouts from the first layout, each second layout comprises at least one hot spot layout, and each hot spot layout corresponds to one hot spot morphology;
the layout updating unit is used for carrying out optical proximity effect correction on the second layout to obtain a third layout, and updating the first layout by utilizing the third layout to obtain a target layout.
In a third aspect, an embodiment of the present application provides a layout correction device, including a processor and a memory; the memory has stored thereon computer executable instructions that when executed by the processor perform the layout modification method described above.
In a fourth aspect, an embodiment of the present application provides a storage medium, where computer executable instructions are stored, where the computer executable instructions are executed by a processor to perform the layout correction method described above.
The beneficial effects that technical scheme that this application embodiment provided include: determining a plurality of hot spot morphologies in the first simulated photoresist morphology according to the first simulated photoresist morphology corresponding to the first layout after the optical proximity effect correction; and then, a plurality of second layouts including at least one hot spot layout are segmented from the first layout, so that the optical proximity effect correction is carried out on the second layout obtained after the fine segmentation of the first layout. And the first layout is updated by using the third layout after the optical proximity effect correction is carried out on the second layout, and the first layout is recovered, so that the integrity of the target layout and the consistency between the target layout and the first layout are ensured.
Additional aspects and advantages of embodiments of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of embodiments of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. In the drawings:
FIG. 1 is a schematic diagram of one specific example of a ripple-like topography in an embodiment of the present application;
FIG. 2 is a flowchart of a specific example of a layout modification method in an embodiment of the present application;
FIG. 3 is a schematic diagram of a specific example of a second layout in an embodiment of the present application;
FIG. 4 is a schematic diagram showing a specific example of a simulated photoresist profile in an embodiment of the present application;
FIG. 5 is a schematic diagram illustrating a comparison of a specific example of the first and second layouts after OPC in an embodiment of the present application;
FIG. 6 is a schematic diagram illustrating a comparison of a specific example of the second layout after OPC in an embodiment of the present application;
FIG. 7 is a schematic diagram of a specific example of a step after splicing in an embodiment of the present application;
FIG. 8 is a schematic diagram of a specific example of a target layout in an embodiment of the present application;
FIG. 9 is a flowchart of another specific example of a layout modification method in an embodiment of the present application;
FIG. 10 is a schematic block diagram of a specific example of a layout modification apparatus in an embodiment of the present application;
fig. 11 is a schematic block diagram of a specific example of a layout modification apparatus in an embodiment of the present application.
Detailed Description
In order to make the technical solution and the beneficial effects of the embodiments of the present application more obvious and understandable, the following details are given by way of example. Wherein the drawings are not necessarily to scale, and wherein local features may be exaggerated or reduced to more clearly show details of the local features; unless otherwise defined, technical and scientific terms used herein have the same meaning as those in the technical field to which the embodiments of the present application belong.
It should be noted that the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. When "first" is described, it does not necessarily mean that "second" is present; and when "second" is discussed, it does not necessarily mean that the present application necessarily exists "first". The singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term "comprising" is used to determine the presence of an included feature, but does not exclude the presence or addition of one or more other features. The term "and/or" includes any and all combinations of the associated listed items.
Before a structure is prepared on a wafer by adopting a photoetching process, the design layout of a mask plate adopted in photoetching needs to be optimized, and an optical proximity effect correction technology can be adopted to correct the design layout so as to reduce pattern transfer distortion and improve the structure preparation precision. The specific correction process can be to establish an optical proximity effect correction model, and the model can be used for carrying out optical proximity effect correction on an original design layout to obtain a simulated photoresist morphology (corresponding to a structure on a wafer obtained by actual preparation) calculated in a simulation mode, and obtain a corrected design layout and a verification result file. Whether the result of the correction can meet the design requirement can be shown in the verification result file. If the pattern size on the design layout is close to the limit of photoetching resolution, the window of the photoetching process can be reduced, and the line edge roughness of the photoresist is increased and the mask error enhancement factor is increased. Thus, for such design layouts and design layouts which are relatively complex in graphics, the simulated photoresist topography obtained by simulation calculation according to the corrected design layout is an unacceptable hot spot topography (photoresist topography) such as a ripple topography which may include at least one of a pattern linewidth anomaly and an edge placement error anomaly, for example, as shown in fig. 1. The region filled with points in FIG. 1 is an ideal photoresist morphology, and the region with the solid curve as the upper and lower boundaries is a simulated photoresist morphology obtained by simulation calculation of the corrected design layout.
Therefore, the embodiment of the application provides a layout correction method which can be applied to the fine correction of the first layout obtained after at least one optical proximity effect correction is carried out on the original design layout. Both the original design layout and the first layout may be two-dimensional figures. As shown in fig. 2, the layout correction method includes:
s10, acquiring a first layout obtained after at least one optical proximity effect correction and a first simulated photoresist morphology corresponding to the first layout;
step S20, determining a plurality of hot spot morphologies in the first simulated photoresist morphology; the hot spot morphology comprises at least one morphology meeting preset abnormal conditions;
step S30, a plurality of second layouts are segmented from the first layout, each second layout comprises at least one hot spot layout, and each hot spot layout corresponds to one hot spot morphology;
and S40, performing optical proximity effect correction on the second layout to obtain a third layout, and updating the first layout by using the third layout to obtain the target layout.
In this embodiment, the preset abnormal condition in step S20 may be set according to actual requirements, for example, the preset abnormal condition may include at least one of an edge placement error being greater than a first abnormal value and a pattern line width deviation being greater than a second abnormal value, where the edge placement error is a value that a single edge of the simulated photoresist profile deviates from an ideal photoresist profile, and the first abnormal value may be 2% -4%, such as 3%, of a normal value of the pattern line width; the pattern linewidth deviation is a value of the pattern linewidth of the simulated photoresist morphology deviating from the ideal photoresist morphology, and the second abnormal value can be 4% -7%, such as 5%, of the normal value of the pattern linewidth. The hotspot morphology determined by step S20 may be considered as an unacceptable hotspot morphology that fails to meet the design requirements.
Each of the second layouts segmented in step S30 may include at least one hotspot layout corresponding to the hotspot morphology. There is a one-to-one correspondence between the hotspot layout and the hotspot morphology. The segmentation mode can be selected according to actual requirements, for example, a region comprising a hot spot layout can be selected in a matting mode; the whole first layout can be divided into a plurality of subareas in a segmentation mode, wherein some subareas can comprise a hot spot layout, other subareas can not comprise a hot spot layout, and the subareas comprising the hot spot layout form the second layout. The shape of the cut-out second layout may include at least one of a rectangle, a square, a triangle, a trapezoid, and the like.
In step S40, the updating of the first layout by using the third layout may be that the corresponding region in the first layout is replaced by using the third layout, so as to obtain an updated complete first layout, that is, the target layout.
In the embodiment of the application, a plurality of hot spot morphologies in the first simulated photoresist morphology are determined according to the first simulated photoresist morphology corresponding to the first layout after the optical proximity effect correction; and then, a plurality of second layouts including at least one hot spot layout are segmented from the first layout, so that the optical proximity effect correction is carried out on the second layout obtained after the fine segmentation of the first layout. And the first layout is updated by using the third layout after the optical proximity effect correction is carried out on the second layout, and the first layout is recovered, so that the integrity of the target layout and the consistency between the target layout and the first layout are ensured.
In an alternative embodiment, in step S30, a plurality of second layouts are segmented from the first layout, each second layout includes at least one hotspot layout, each hotspot layout corresponds to one hotspot morphology, and the method includes:
step S301, creating a plurality of rectangles with the side length being greater than or equal to four times of the optical diameter;
step S302, taking a rectangle as a boundary of a second layout, and segmenting the acquired first layout so that a hot-spot layout cluster corresponding to one hot-spot morphology cluster is positioned in the middle of the rectangle, thereby acquiring a plurality of second layouts; one hotspot profile cluster comprises at least one hotspot profile, and the minimum value of the distance between two adjacent hotspot profile clusters is greater than or equal to a minimum distance threshold.
In the embodiments of the present application, the optical diameter may be defined as the smallest dimension of the line width of the pattern that is not affected by the surrounding environment. The definition of the minimum value of the distance between two adjacent hotspot morphology clusters can be set according to actual requirements, for example, the definition can be defined as the minimum value between the center point of the first hotspot morphology in one hotspot morphology cluster and the center point of the second hotspot morphology in the other hotspot morphology cluster; may also be defined as a minimum between one side edge of a first hotspot profile in one hotspot profile cluster and either side edge of a second hotspot profile in another hotspot profile cluster.
Corresponding to the hotspot morphology cluster, a hotspot layout cluster can be included on the first layout. According to the corresponding relation between the hot spot morphology clusters and the hot spot layout clusters, mirror image rectangles consistent with the rectangles of the second layout can be formed on the first simulated photoresist morphology. As a specific example, as shown in fig. 3, a plurality of hotspot profiles are included in one hotspot profile cluster, which is located in the middle of a mirrored rectangle with a side length greater than four times the optical diameter, which mirrored rectangle corresponds to a rectangle on the second layout. The first layout is finely segmented by rectangles with the optical diameter being more than or equal to four times, so that the optical proximity effect correction effect can be effectively improved, the debugging process is simplified, the operation time is shortened, and the efficiency is improved.
In an alternative embodiment, at least one of finer segmentation, eliminating the influence of adjacent patterns on segmentation points and introducing mask error enhancement factors can be adopted to control the movement of edges in the process of carrying out optical proximity effect correction on the second layout, and because the core of OPC is to segment the patterns and move the segmented edges, better control the movement of the edges can obtain good optical proximity effect correction results, so that the photoresist morphology obtained after OPC is carried out by at least one of finer segmentation, eliminating the influence of adjacent patterns on segmentation points and introducing mask error enhancement factors can be improved beneficially. As shown in fig. 4, in the uppermost graph in fig. 4, the unfilled graph bordered by the outer solid curve is an unoptimized simulated photoresist morphology obtained after OPC without using finer segmentation, the dot-filled graph bordered by the inner solid curve is an optimized simulated photoresist morphology obtained after OPC using finer segmentation, and the gray-filled region is an ideal photoresist morphology. In the middle graph in fig. 4, the unfilled graph with the outer solid curve as the boundary is the non-optimized simulated photoresist morphology obtained after the influence of the adjacent graph on the cut point is not eliminated, the point filled graph with the inner solid curve as the boundary is the optimized simulated photoresist morphology obtained after the influence of the adjacent graph on the cut point is eliminated, and the gray filled region is the ideal photoresist morphology. In the bottom graph in fig. 4, the unfilled graph with the outer solid curve as the boundary is the non-optimized simulated photoresist morphology obtained after OPC without introducing the mask error enhancement factor, the dot filled graph with the inner solid curve as the boundary is the optimized simulated photoresist morphology obtained after OPC with introducing the mask error enhancement factor, and the gray filled region is the ideal photoresist morphology. As can be seen from fig. 4, the optimized simulated photoresist morphology is significantly improved compared with the non-optimized simulated photoresist morphology, and the edge placement error and the line width deviation are smaller, so as to meet the design requirements.
As shown in fig. 5 and fig. 6, the post-OPC results of the three methods of combining finer segmentation, eliminating the influence of the adjacent patterns on the segmentation points, and introducing the mask error enhancement factor in the embodiments of the present application are performed on the three second layouts, respectively. The gray completely filled region in the lower graph of fig. 5 is the target layout, the point filled region is the first layout, the oblique line filled region is the third layout obtained by simultaneously introducing finer segmentation and eliminating the influence of the adjacent graph on the segmentation points and the mask error enhancement factor after OPC, the gray completely filled region in the upper graph of fig. 5 is the ideal photoresist morphology, the non-filled region with the solid curve as the boundary is the first simulated photoresist morphology corresponding to the first layout, the point filled region with the solid curve as the boundary is the third simulated photoresist morphology corresponding to the third layout, and it can be seen that the ripple morphology of the third simulated photoresist morphology is obviously improved, for example, the third simulated photoresist morphology and the ideal photoresist morphology can be well bordered. Similarly, a significant improvement in the wavelike morphology of the third simulated photoresist morphology can be seen in fig. 6. The gray completely filled region in the lower graph of fig. 6 is the target layout, the region filled with dots is the first layout, the region filled with oblique lines is the third layout (ladder-like layout) obtained by simultaneously introducing finer segmentation, eliminating the influence of adjacent graphs on segmentation points and mask error enhancement factors after OPC, the region completely filled with gray in the upper graph of fig. 6 is the ideal photoresist morphology, the non-filled region bordered by the solid curve is the first simulated photoresist morphology corresponding to the first layout, and the region filled with dots bordered by the solid curve is the third simulated photoresist morphology corresponding to the third layout.
When the split second layout is subjected to OPC, the graph at the split edge is regarded as an endpoint, so that errors at the position are larger during layout correction, steps are generated at the split edge when the obtained third layout is directly spliced with the first layout, and the steps are indicated in an elliptical dotted line shown in fig. 7, so that the simulated photoresist morphology formed in the process can be protruded out of the ideal photoresist morphology at the position, and the effect of optical proximity effect correction is affected.
To this end, in an alternative embodiment, updating the first layout with the third layout in step S40 to obtain the target layout includes:
s401, cutting off edges of the third layout with preset width to obtain a fourth layout;
and step S402, replacing the corresponding region in the first layout with the fourth layout to obtain the target layout.
In an alternative embodiment, the preset width may be set according to actual requirements, for example, the preset width may be greater than or equal to one optical diameter. Cutting off the edges of the third layout with preset width, namely cutting off the four sides of the rectangle of the third layout with preset width, wherein the edge of the rectangle is integrally removed with a character-returning area, and the width of each edge of the character-returning area is larger than or equal to one time of optical diameter. As shown in fig. 8, after the edges of the return font area are cut off by the third layout in the rectangular dotted line frame, the corresponding area in the first layout is replaced, the obtained target layout can be seen to be well attached to the edges of the spliced part, the single-side difference is smaller than 0.5nm, and the design requirement is met. The single-side difference is the step height of the boundary of the two layouts at the splicing position.
In the embodiment of the application, the fourth layout obtained by cutting the edge of the preset width of the third layout replaces the corresponding area in the first layout, so that the unilateral difference of the obtained target layout at the spliced edge is reduced, and the precision is improved.
In an alternative embodiment, as shown in fig. 9, the layout modification method further includes:
step S50, determining whether a second simulated photoresist morphology corresponding to the target layout contains a hot spot morphology;
and step S60, if the second simulated photoresist morphology corresponding to the target domain does not contain the hot spot morphology, obtaining a result of finishing the correction of the target domain and outputting the target domain.
In an alternative embodiment, as shown in fig. 9, the layout modification method further includes:
and step S70, if the second simulated photoresist morphology corresponding to the target domain contains the hot spot morphology, obtaining a result that the target domain is not corrected, and returning to determine a plurality of hot spot morphologies in the first simulated photoresist morphology to continue execution until a result that the target domain is corrected is obtained.
In the embodiment of the application, if the result of finishing the correction of the target layout is obtained, it is indicated that the edge placement error in the second simulated photoresist morphology is smaller than or equal to the first abnormal value, and the first abnormal value may be 2% -4%, such as 3%, of the normal value of the line width of the pattern; the pattern line width deviation is less than or equal to a second outlier, which may be 4% -7%, such as 5%, of the normal value of the pattern line width. After the result of the target layout correction is obtained, the target layout can be sent to other required departments such as a design department for subsequent processing. And finally, obtaining a result of finishing the correction of the target layout by setting a step of judging whether the second simulated photoresist morphology corresponding to the target layout contains the hot spot morphology or not, and verifying the final optical proximity effect correction layout so that the edge placement error, the line width abnormality and the ripple morphology of the layout all meet the requirements of corresponding line widths, thereby ensuring that the pattern on the mask can be accurately transferred onto the wafer.
The embodiment of the present application further provides a layout correction device, corresponding to the above layout correction method, as shown in fig. 10, where the layout correction device 100 includes:
an obtaining unit 10, configured to obtain a first layout obtained after at least one optical proximity correction and a first simulated photoresist morphology corresponding to the first layout;
a first determining unit 20, configured to determine a plurality of hot spot profiles in the first simulated photoresist profile; the hot spot morphology comprises at least one morphology meeting preset abnormal conditions;
a splitting unit 30, configured to split a plurality of second layouts from the first layout, where each second layout includes at least one hotspot layout, and each hotspot layout corresponds to one hotspot morphology;
and the layout updating unit 40 is used for carrying out optical proximity effect correction on the second layout to obtain a third layout, and updating the first layout by using the third layout to obtain the target layout.
In an alternative embodiment, the preset exception condition includes at least one of an edge placement error being greater than a first exception value and a pattern linewidth deviation being greater than a second exception value.
In an alternative embodiment, the slicing unit 30 includes:
a rectangle creation unit for creating a plurality of rectangles having sides longer than or equal to four times the optical diameter;
the second layout obtaining unit is used for taking the rectangle as the boundary of the second layout, and segmenting the obtained first layout so that a hot layout cluster corresponding to one hot morphology cluster is positioned in the middle of the rectangle, and a plurality of second layouts are obtained; one hotspot profile cluster comprises at least one hotspot profile, and the minimum value of the distance between two adjacent hotspot profile clusters is greater than or equal to a minimum distance threshold.
In an alternative embodiment, the layout updating unit 40 includes:
a fourth layout obtaining unit, configured to cut an edge of a preset width of the third layout, to obtain a fourth layout;
the target layout obtaining unit is used for replacing the corresponding area in the first layout with the fourth layout to obtain the target layout.
In an alternative embodiment, the predetermined width is greater than or equal to one optical diameter.
In an alternative embodiment, the layout modification apparatus 100 further includes:
the second determining unit is used for determining whether the second simulated photoresist morphology corresponding to the target domain contains a hot spot morphology or not;
the first result obtaining unit is used for obtaining a result of finishing the correction of the target layout and outputting the target layout if the second simulated photoresist morphology corresponding to the target layout does not contain the hot spot morphology.
In an alternative embodiment, the layout modification apparatus 100 further includes:
and the second result obtaining unit is used for obtaining the result that the target layout is not corrected and returning to determine a plurality of hot spot morphologies in the first simulated photoresist morphology to continue execution until the result that the target layout is corrected is obtained if the hot spot morphology is contained in the second simulated photoresist morphology corresponding to the target layout.
The embodiment of the application also provides layout correction equipment. As shown in fig. 11, the layout modification apparatus 200 includes a processor 201 and a memory 202; the memory 202 has stored thereon computer executable instructions that when executed by the processor 201 perform the layout modification method described above.
The processor 201 may be a Central Processing Unit (CPU) or other form of processing unit having data processing and/or instruction execution capabilities and may control other components in the layout modification device to perform the desired functions.
Memory 202 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, random Access Memory (RAM) and/or cache memory (cache) and the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, and the like. One or more computer program instructions may be stored on a computer readable storage medium and the processor 201 may execute the program instructions to implement the steps in the layout modification method described above and/or other desired functions.
In an alternative embodiment, the layout modification apparatus 200 may further include: input/output interface 204, and communication interface 205, etc. The processor 201, the memory 202 and the communication interface 205 are connected to each other via a bus 203. The communication interface 205 is used to provide a communication channel, and the input/output interface 204 is connected to an input device or an output device. The input devices include a keyboard, a mouse, and a microphone. The output device is used to output various information to the outside, including a display, a speaker, a printer, and a communication network and a remote output apparatus connected thereto. In addition, the layout modification apparatus 200 may include any other suitable components depending on the particular application.
The embodiment of the application also provides a storage medium, and the storage medium is stored with computer executable instructions which execute the layout correction method when being run by a processor.
Embodiments of the present application may be a system, method, and/or computer program product. The computer program product may include a computer readable storage medium having computer readable program instructions embodied thereon for causing a processor to implement aspects of embodiments of the present application. The computer program product may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of embodiments of the present application are implemented by personalizing electronic circuitry, such as programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), with state information for computer-readable program instructions, which may execute the computer-readable program instructions.
A computer readable storage medium may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A computer readable storage medium is a tangible device that can hold and store instructions for use by an instruction execution device. The readable storage medium may include, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: portable computer disks, hard disks, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static Random Access Memory (SRAM), portable compact disk read-only memory (CD-ROM), digital Versatile Disks (DVD), memory sticks, floppy disks, mechanical coding devices, punch cards or in-groove structures such as punch cards or grooves having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media, as used herein, are not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.
The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a respective computing/processing device or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network interface card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing/processing device.
Various aspects of embodiments of the present application are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
It should be noted that, the layout correction method embodiment, the layout correction device embodiment, the storage medium embodiment and the layout correction device embodiment provided in the embodiments of the present application belong to the same concept; the features of the embodiments described in the present invention may be combined arbitrarily without any conflict.
It should be understood that the above examples are illustrative and are not intended to encompass all possible implementations encompassed by the claims. Various modifications and changes may be made in the above embodiments without departing from the scope of the disclosure. Likewise, the various features of the above embodiments may be combined arbitrarily to form further embodiments of the application that may not be explicitly described. Thus, the above examples merely represent several embodiments of the present application and do not limit the scope of protection of the patent of the present application.
Claims (8)
1. A layout correction method is characterized by comprising the following steps:
acquiring a first layout obtained after at least one optical proximity effect correction and a first simulated photoresist morphology corresponding to the first layout;
determining a plurality of hot spot morphologies in the first simulated photoresist morphology; one of the hotspot profiles comprises at least one profile meeting a preset abnormal condition;
a plurality of second layouts are segmented from the first layout, each second layout comprises at least one hot spot layout, and each hot spot layout corresponds to one hot spot morphology;
performing optical proximity effect correction on the second layout to obtain a third layout, and updating the first layout by using the third layout to obtain a target layout;
the step of segmenting a plurality of second layouts from the first layout, wherein each second layout comprises at least one hot spot layout, each hot spot layout corresponds to one hot spot morphology, and the step of segmenting comprises the following steps:
creating a plurality of rectangles having sides greater than or equal to four times the optical diameter;
the rectangle is taken as the boundary of the second layout, and the acquired first layout is segmented, so that a hot layout cluster corresponding to one hot morphology cluster is positioned in the middle of the rectangle, and a plurality of second layouts are acquired; the hot spot morphology clusters comprise at least one hot spot morphology, and the minimum value of the distance between two adjacent hot spot morphology clusters is larger than or equal to a minimum distance threshold;
the updating the first layout by using the third layout to obtain a target layout comprises the following steps:
cutting off the edge of the preset width of the third layout to obtain a fourth layout;
replacing the corresponding region in the first layout with the fourth layout to obtain a target layout;
the optical diameter is the smallest dimension of the pattern linewidth that is not affected by the surrounding environment.
2. The layout correction method according to claim 1, wherein the preset abnormal condition includes at least one of an edge placement error being larger than a first abnormal value and a pattern line width deviation being larger than a second abnormal value.
3. The layout modification method according to claim 1, wherein the preset width is greater than or equal to one optical diameter.
4. A layout modification method according to any one of claims 1 to 3, further comprising:
determining whether the second simulated photoresist morphology corresponding to the target layout contains the hot spot morphology;
and if the second simulated photoresist morphology corresponding to the target domain does not contain the hot spot morphology, obtaining a result of finishing the correction of the target domain and outputting the target domain.
5. The layout modification method according to claim 4, further comprising:
and if the second simulated photoresist morphology corresponding to the target domain contains the hot spot morphology, obtaining a result that the target domain is not corrected, and returning to the determination of a plurality of hot spot morphologies in the first simulated photoresist morphology to continue execution until obtaining the result that the target domain is corrected.
6. A layout correction apparatus, comprising:
the acquisition unit is used for acquiring a first layout obtained after at least one optical proximity effect correction and a first simulated photoresist morphology corresponding to the first layout;
the first determining unit is used for determining a plurality of hot spot morphologies in the first simulated photoresist morphology; one of the hotspot profiles comprises at least one profile meeting a preset abnormal condition;
the segmentation unit is used for segmenting a plurality of second layouts from the first layout, each second layout comprises at least one hot spot layout, and each hot spot layout corresponds to one hot spot morphology;
the layout updating unit is used for carrying out optical proximity effect correction on the second layout to obtain a third layout, and updating the first layout by utilizing the third layout to obtain a target layout;
the segmentation unit includes:
a rectangle creation unit for creating a plurality of rectangles having sides longer than or equal to four times the optical diameter;
the second layout obtaining unit is used for taking the rectangle as the boundary of the second layout, and segmenting the obtained first layout so that a hot layout cluster corresponding to one hot morphology cluster is positioned in the middle of the rectangle, and a plurality of second layouts are obtained; the hot spot morphology clusters comprise at least one hot spot morphology, and the minimum value of the distance between two adjacent hot spot morphology clusters is larger than or equal to the minimum distance threshold;
the layout updating unit comprises:
a fourth layout obtaining unit, configured to cut an edge of a preset width of the third layout, to obtain a fourth layout;
the target layout obtaining unit is used for replacing the corresponding area in the first layout with the fourth layout to obtain a target layout;
the optical diameter is the smallest dimension of the pattern linewidth that is not affected by the surrounding environment.
7. A layout correction device is characterized by comprising a processor and a memory; the memory having stored thereon computer executable instructions which, when executed by the processor, perform the layout modification method according to any of claims 1-5.
8. A storage medium having stored thereon computer executable instructions which when executed by a processor perform the layout modification method of any of claims 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311638969.7A CN117348332B (en) | 2023-12-04 | 2023-12-04 | Layout correction method, device, equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311638969.7A CN117348332B (en) | 2023-12-04 | 2023-12-04 | Layout correction method, device, equipment and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117348332A CN117348332A (en) | 2024-01-05 |
| CN117348332B true CN117348332B (en) | 2024-02-02 |
Family
ID=89363478
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311638969.7A Active CN117348332B (en) | 2023-12-04 | 2023-12-04 | Layout correction method, device, equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117348332B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118036545B (en) * | 2024-04-11 | 2024-06-14 | 北京芯愿景软件技术股份有限公司 | Layout graph comparison method and device and layout graph comparison replacement method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112255896A (en) * | 2020-11-20 | 2021-01-22 | 上海华力集成电路制造有限公司 | Multiple pattern hot spot optimization method |
| CN114253064A (en) * | 2020-09-21 | 2022-03-29 | 中芯国际集成电路制造(上海)有限公司 | Optical proximity correction method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7805692B2 (en) * | 2006-05-15 | 2010-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for local hot spot fixing |
| NL2007642A (en) * | 2010-11-10 | 2012-05-14 | Asml Netherlands Bv | Optimization flows of source, mask and projection optics. |
| US20170262570A1 (en) * | 2016-03-11 | 2017-09-14 | Mentor Graphics Corporation | Layout Design Repair Using Pattern Classification |
-
2023
- 2023-12-04 CN CN202311638969.7A patent/CN117348332B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114253064A (en) * | 2020-09-21 | 2022-03-29 | 中芯国际集成电路制造(上海)有限公司 | Optical proximity correction method |
| CN112255896A (en) * | 2020-11-20 | 2021-01-22 | 上海华力集成电路制造有限公司 | Multiple pattern hot spot optimization method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117348332A (en) | 2024-01-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102525162B1 (en) | OPC(Optical Proximity Correction) method, and methods for manufacturing mask using the OPC method | |
| JP5341399B2 (en) | PATTERN VERIFICATION METHOD, PATTERN VERIFICATION DEVICE, PROGRAM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD | |
| JP3934719B2 (en) | Optical proximity correction method | |
| JP4510118B2 (en) | Optical proximity effect correction method and apparatus, optical proximity effect verification method and apparatus, exposure mask manufacturing method, optical proximity effect correction program, and optical proximity effect verification program | |
| US10394116B2 (en) | Semiconductor fabrication design rule loophole checking for design for manufacturability optimization | |
| CN117348332B (en) | Layout correction method, device, equipment and storage medium | |
| US20130183832A1 (en) | Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections for semiconductor applications | |
| TWI547753B (en) | Methods and systems for designing and manufacturing optical lithography masks | |
| US6536015B2 (en) | Apparatus and method of correcting layout pattern data, method of manufacturing semiconductor devices and recording medium | |
| JP4357287B2 (en) | Correction guide generation method, pattern creation method, mask manufacturing method, semiconductor device manufacturing method, and program | |
| US8997027B2 (en) | Methods for modifying an integrated circuit layout design | |
| US10726187B2 (en) | Self-aligned double patterning-aware routing in chip manufacturing | |
| JP2014081472A (en) | Optical proximity effect correction method, processing unit, program, production method of mask, and production method of semiconductor device | |
| TWI557584B (en) | Method semiconductor device design, method of preparing a layout of an integrated circuit device and non-transitory computer readable medium | |
| JP5052625B2 (en) | Method and program for designing mask layout | |
| CN115047707A (en) | Optical proximity correction method and system, mask, equipment and storage medium | |
| CN117631436A (en) | Sub-resolution auxiliary graph optimization method, system and storage medium | |
| US20250190674A1 (en) | Correcting rule violations in a layout | |
| US7975246B2 (en) | MEEF reduction by elongation of square shapes | |
| US8930858B1 (en) | Method for optical proximity correction | |
| CN113777877A (en) | Method and system for integrated circuit optical proximity correction parallel processing | |
| JP2004302110A (en) | Verifying method for mask pattern, program for verifying mask pattern and method for manufacturing mask | |
| CN115268205A (en) | Method for improving edge placement error | |
| JP2013242427A (en) | Method and program for controlling opc processing, and method for manufacturing mask | |
| CN114660890A (en) | OPC correction method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |