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CN117316787A - Chip manufacturing method and packaging structure - Google Patents

Chip manufacturing method and packaging structure Download PDF

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Publication number
CN117316787A
CN117316787A CN202311516986.3A CN202311516986A CN117316787A CN 117316787 A CN117316787 A CN 117316787A CN 202311516986 A CN202311516986 A CN 202311516986A CN 117316787 A CN117316787 A CN 117316787A
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CN
China
Prior art keywords
layer
solder
wafer
bonding
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311516986.3A
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Chinese (zh)
Inventor
胡川
燕英强
向迅
陈志涛
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Institute of Semiconductors of Guangdong Academy of Sciences
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Institute of Semiconductors of Guangdong Academy of Sciences
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Application filed by Institute of Semiconductors of Guangdong Academy of Sciences filed Critical Institute of Semiconductors of Guangdong Academy of Sciences
Priority to CN202311516986.3A priority Critical patent/CN117316787A/en
Publication of CN117316787A publication Critical patent/CN117316787A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L21/603—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

The embodiment of the invention provides a chip manufacturing method and a packaging structure, and relates to the technical field of circuit packaging, wherein the chip manufacturing method comprises the steps of providing at least two wafer layers; the wafer layer comprises a surface layer and at least one middle layer; the middle layer is provided with a through connecting column; a bonding layer is arranged on the functional surface of the middle layer and the surface layer; the functional surface of the middle layer and the surface layer is also provided with a metal column or solder; solder is positioned in the groove of the bonding layer; wherein the height of the solder is smaller than the height of the groove; and the width of the solder is smaller than the width of the groove; stacking the wafer layers in sequence and hot-pressing the wafer layers so that metal columns of two adjacent wafer layers are embedded into solder and form an interconnection piece with the connecting columns; and the bonding layer wraps the solder and fills the functional surfaces of the two adjacent wafer layers. The method solves the problem that the TSV through silicon via lamination packaging technology of the storage in the prior art easily causes filler particles, air holes or holes in the solder, and reduces the risk of solder short circuit.

Description

Chip manufacturing method and packaging structure
Technical Field
The application relates to the technical field of device packaging, in particular to a chip manufacturing method and a packaging structure.
Background
In the prior art, with the rapid development of artificial intelligence, a semiconductor device is required to have higher and higher computational power. The bottleneck affecting the increase of computing power at present comes from the storage and extraction speed of huge amounts of data, and the data transmission bandwidth of a memory is required to be higher and higher.
Currently, however, memory packaging techniques have failed to meet data transmission bandwidth requirements. The utilization of TSV technology and TCB stack packaging is critical to breaking through the technological bottlenecks.
In the conventional packaging process, a flip chip and a reflow soldering process are often adopted to perform stack packaging, and then an Underfill is used to fill the chip gap, and then the package is further performed, or a plastic package is directly performed with a plastic package Underfill (MUF) without Underfill. However, the welding pins have large spacing, otherwise, the welding flux is easy to short; the use of underfill or underfill to fill the chip gaps should not be too small, or else the chip gaps cannot be completely filled to store the holes. This affects the packing density to some extent. The other scheme is as follows: and uniformly covering NCF (non-conductive film) or NCP (non-conductive paste) on the surface of the chip and the solder or the metal column, and then discharging the NCF or NCP on the surface of the solder under the condition of heating and pressurizing, thereby realizing solder welding and NCF or NCP bonding. However, the presence of a certain amount of filler (filler) particles in the soldered solder may cause short circuits and reliability problems, low yields, and the solder may easily extrude to cause short circuits.
Disclosure of Invention
The invention aims to provide a chip manufacturing method and a packaging structure, which are used for solving the problems of low packaging density, filling particles in solder, holes between chips, solder short circuit and the like which are easy to cause in the memory TSV silicon through hole lamination packaging technology in the prior art.
Embodiments of the invention may be implemented as follows:
in a first aspect, a chip manufacturing method includes:
providing at least two wafer layers; the wafer layer comprises a surface layer and at least one middle layer; the middle layer is provided with a through connecting column; a bonding layer is arranged on the functional surface of the middle layer and the surface layer; the functional surface of the middle layer and the surface layer is also provided with a metal column or solder; the solder is positioned in the groove of the bonding layer; wherein the height of the solder is smaller than the height of the groove; and the width of the solder is smaller than the width of the groove;
stacking and hot-pressing the wafer layers in sequence, so that metal columns of two adjacent wafer layers are embedded into the solder and form an interconnection piece with the connecting columns; the bonding layer wraps the solder and fills the functional surfaces of the two adjacent wafer layers; the functional surface is a surface on each wafer layer for bonding other wafer layers.
Further, the step of providing at least two wafer layers includes:
coating a bonding layer on the functional surface provided with the solder;
arranging the grooves at target positions of the bonding layer to expose the solder on the wafer layer, and taking the function surface provided with the solder as an etching stop layer;
wherein the height of the solder is smaller than the height of the groove; and the width of the solder is smaller than the width of the groove.
Further, the step of providing at least two wafer layers further includes:
a blind hole is formed in the middle layer;
an insulating layer is arranged on the inner wall of the blind hole;
and filling a metal filling layer on the inner wall of the insulating layer to obtain the through connecting column.
Further, the surface layer includes a top layer, and when the metal pillars are disposed on the functional surface of the top layer, the step of providing at least two wafer layers includes:
preparing at least one metal column, wherein the surface of the metal column is provided with a protective layer;
transferring the metal columns to a temporary carrier plate;
and pasting the metal posts on the target positions of the functional surfaces of the top layers based on the temporary carrier plates so as to correspond to the solders on the functional surfaces of the middle layers.
Further, the surface layer includes a top layer, and when solder is disposed on the functional surface of the top layer, the step of providing at least two wafer layers includes:
preparing a connecting column on the functional surface of the top layer;
solder is prepared at the target locations on the functional side of the top layer to connect the solder with the connection posts.
Further, the top layer includes top layer and bottom layer, the intermediate layer includes first functional surface, second functional surface, wherein sets up solder and metal column respectively on first functional surface, the second functional surface, the step of providing two at least wafer layers includes:
preparing at least one metal column at a target position of the functional surface of the top layer so as to correspond to the solder on the first functional surface, wherein a protective layer is arranged on the surface of the metal column;
and preparing solder at a target position on the functional surface of the bottom layer so as to correspond to the metal column on the second functional surface, and connecting the solder with the connecting column of the middle layer.
Further, the top layer includes top layer and bottom layer, the intermediate layer includes first functional surface, second functional surface, wherein sets up solder and metal column respectively on first functional surface, the second functional surface, the step of providing two at least wafer layers includes:
Preparing at least one metal column, wherein the surface of the metal column is provided with a protective layer;
transferring the metal columns to a temporary carrier plate;
attaching the metal posts to target positions of the functional surfaces of the top layer based on the temporary carrier plate so as to correspond to the solders on the first functional surface;
and preparing solder at a target position on the functional surface of the bottom layer so as to correspond to the metal column on the second functional surface, and connecting the solder with the connecting column of the middle layer.
Further, the step of transferring the metal posts to a temporary carrier plate includes:
a temporary bonding layer is arranged on the temporary carrier plate;
and transferring the metal posts to the surface of the temporary bonding layer so as to attach the metal posts to the functional surface of the top layer through the temporary bonding layer.
Further, the step of stacking and hot-pressing the wafer layers sequentially includes:
fixing two adjacent wafer layers so that metal columns of the two adjacent wafer layers correspond to solder one by one;
and performing one-time thermocompression bonding on the wafer layer in the vacuum bonding chamber.
Further, the step of stacking and hot-pressing the wafer layers sequentially includes:
Pre-bonding two adjacent wafer layers to enable metal columns of the two adjacent wafer layers to be partially embedded into solder;
performing primary hot-press bonding on the two adjacent wafer layers after pre-bonding in a vacuum bonding cavity so as to completely embed the metal columns of the two adjacent chips into the solder and form an interconnection piece with the connecting columns; and the bonding layer wraps the solder and fills the functional surfaces of the adjacent two layers of chips.
Further, the step of stacking and hot-pressing the wafer layers in sequence further includes:
cutting the intermediate layer and the surface layer respectively according to a preset cutting path in the vacuum bonding cavity to obtain a first chip and a second chip respectively;
sequentially thermocompression bonding the first chip and the second chip to a substrate to sequentially embed metal columns of two adjacent layers of chips into the solder and form an interconnection with the connecting columns; and the bonding layer wraps the solder and fills the functional surfaces of the adjacent two layers of chips.
Further, the step of stacking and hot-pressing the wafer layers in sequence further includes:
cutting the middle layer and the surface layer respectively according to preset cutting channels to obtain a first chip and a second chip respectively;
Thermocompression bonding the first chip to a substrate;
pre-bonding the first chip and the second chip so that metal posts of two adjacent layers of chips are partially embedded into solder;
in the vacuum bonding chamber, performing primary hot-press bonding on the first chip and the second chip after pre-bonding so as to completely embed the metal columns of the two adjacent layers of chips into the solder and form an interconnection piece with the connecting columns; and the bonding layer wraps the solder and fills the functional surfaces of the adjacent two layers of chips.
Further, after the step of stacking and hot-pressing the wafer layers in sequence, the method further includes:
cutting the wafer layer after hot pressing according to a preset cutting path;
flip-chip mounting the cut wafer layer on a substrate;
performing plastic packaging on one surface of the substrate close to the wafer layer;
and preparing external pins on one surface of the substrate far away from the wafer layer.
In a second aspect, a package structure, the package structure includes:
a substrate;
a chip attached to one side surface of the substrate; wherein the chip is prepared by the method of any one of the first aspects;
the external pins are attached to the surface of one side of the substrate far away from the chip;
And wrapping the plastic sealing layer of the chip on the substrate.
Further, the chip includes:
at least two wafer layers;
an interconnect through at least one wafer layer; wherein the interconnect comprises a metal post, solder, and a connection post;
bonding layers between two adjacent wafer layers; the bonding layer wraps the solder and the metal column and fills the functional surfaces of the two adjacent wafer layers.
The functional surface is a surface on each wafer layer for bonding other wafer layers.
Further, the functional surface of the wafer layer comprises the metal posts or the solder.
Further, the surface of the metal post includes a protective layer.
The beneficial effects of the embodiment of the invention include, for example:
the chip manufacturing method comprises the steps of providing at least two wafer layers; the wafer layer comprises a surface layer and at least one middle layer; the middle layer is provided with a through connecting column; a bonding layer is arranged on the functional surface of the middle layer and the surface layer; the functional surface of the middle layer and the surface layer is also provided with a metal column or solder; solder is positioned in the groove of the bonding layer; wherein the height of the solder is smaller than the height of the groove; and the width of the solder is smaller than the width of the groove; stacking the wafer layers in sequence and hot-pressing the wafer layers so that metal columns of two adjacent wafer layers are embedded into solder and form an interconnection piece with the connecting columns; the bonding layer wraps the solder and fills the functional surfaces of the two adjacent wafer layers; the functional surface is a surface on each wafer layer for bonding other wafer layers. So that the metal columns of two adjacent wafer layers are embedded into solder and form an interconnection part with the connecting columns; and the bonding layer wraps the solder and fills the functional surfaces of the two adjacent wafer layers. The method solves the problem that the TSV through silicon via lamination packaging technology of the storage in the prior art easily causes filler particles, air holes or holes in the solder, and reduces the risk of solder short circuit.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a vertical cross-sectional view of a package structure according to an embodiment of the present application.
Fig. 2 is a vertical cross-sectional view of a connector in an embodiment of the present application.
Fig. 3 is a flowchart illustrating steps of a method for manufacturing a chip according to an embodiment of the present application.
Fig. 4 is a second flowchart of a step of a chip manufacturing method according to an embodiment of the present application.
Fig. 5 is one of the step flowcharts of step S1 in the embodiment of the present application.
Fig. 6 is one of the vertical sectional views of the structure prepared in step S1 in the embodiment of the present application.
Fig. 7 is a vertical cross-sectional view of a top wafer layer in an embodiment of the present application.
Fig. 8 is a vertical cross-sectional view of an intermediate wafer layer in an embodiment of the present application.
Fig. 9 is a vertical cross-sectional view of an underlying wafer layer in an embodiment of the present application.
Fig. 10 is a vertical cross-sectional view of a through hole in an embodiment of the present application.
Fig. 11 is a vertical cross-sectional view of a through hole with the backside of the underlying wafer layer subtracted in an embodiment of the present application.
Fig. 12 is a second step flowchart of step S1 in the embodiment of the present application.
Fig. 13 is a vertical cross-sectional view of a bonding layer preparation structure in an embodiment of the present application.
Fig. 14 is a third step flowchart of step S1 in the embodiment of the present application.
Fig. 15 is a vertical cross-sectional view of a temporary carrier-based metal pillar fabrication structure in an embodiment of the present application.
Fig. 16 is a vertical cross-sectional view of a metal pillar making structure in an embodiment of the present application.
Fig. 17 is a fourth step flowchart of step S1 in the embodiment of the present application.
Fig. 18 is one of the vertical cross-sectional views of the top solder preparation structure in the embodiment of the present application.
Fig. 19 is a vertical cross-sectional view of a solder preparation structure with the backside of the top wafer layer subtracted in an embodiment of the present application.
Fig. 20 is a second vertical cross-sectional view of a top wafer level solder preparation structure in accordance with an embodiment of the present application.
Fig. 21 is one of the step flowcharts of step S2 in the embodiment of the present application.
Fig. 22 is one of the vertical sectional views of the structure prepared in step S2 in the embodiment of the present application.
Fig. 23 is a vertical cross-sectional view of the multi-layered wafer layer structure after two adjacent wafer layers are secured by the alignment clip according to the embodiment of the present application.
Fig. 24 is one of the vertical cross-sectional views of the bonded chip structure in the embodiment of the present application.
Fig. 25 is one of the vertical sectional views of the pre-bond preparation structure in the embodiment of the present application.
Fig. 26 is a second vertical cross-sectional view of a bonded chip structure in an embodiment of the present application.
Fig. 27 is a second step flowchart of step S2 in the embodiment of the present application.
Fig. 28 is a vertical cross-sectional view of a first chip in an embodiment of the application.
Fig. 29 is a vertical cross-sectional view of the first chip after bonding to the substrate in an embodiment of the present application.
Fig. 30 is a vertical cross-sectional view of the second chip after bonding to the first chip in an embodiment of the present application.
Fig. 31 is a third step flowchart of step S2 in the embodiment of the present application.
FIG. 32 is a second vertical cross-sectional view of a pre-bond preparation structure in an embodiment of the present application.
Icon: 100-package structure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
Herein, the term "chip" refers to both any type of semiconductor chip (chip) or integrated circuit chip that performs a particular function and any type of semiconductor die (die) or integrated circuit die that performs a particular function.
The term "wafer layer" herein refers to a silicon wafer that is prepared before the chips are formed without dicing.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
As in the background art, with the rapid development of artificial intelligence, the demand for computing power for semiconductor devices is increasing, and the bottleneck affecting the increase in computing power comes from the storage and extraction speed of huge amounts of data, which requires an increasing memory data transmission bandwidth. However, current memory packaging techniques have failed to meet the data transmission bandwidth requirements. Therefore, the utilization of TSV (3D) packaging technology and TCB (bonded hot-pressed) stack packaging is a key to breaking through the technological bottlenecks.
The inventor researches and discovers that in the prior art, TSV bump and metal pillars (pilar) are often prepared on a chip, then a film chip and a reflow soldering process are used for laminated packaging, then a chip gap is filled with underfill, and then plastic packaging is performed, however, in order to enable the underfill to fill the chip gap and avoid solder short circuit, the space and the height of the metal pillars are limited, so that the packaging density is affected to a certain extent, and the packaging thickness is larger, and the cost is higher. However, this approach is not applicable to wafer level packaging, but only to chip to wafer level packaging.
In another manufacturing process, TSV bump and metal pillars (pilar) are manufactured on a chip, and then a film chip and a reflow soldering process are used for stack packaging, unlike the case where a MUF (small particle filler) molding compound is used for plastic packaging, the MUF directly fills the chip gap; but also in order for MUF (small particle filler) to fill the chip gap and avoid solder shorts, the filler particle size in MUF (small particle filler) must be small (typically 2-5 microns); but this approach is prone to hole creation by the bump and is not suitable for wafer level packaging as well.
The above two packaging methods also result in greater warpage as the number of stacked layers is greater, so that the bump is not soldered and the alignment offset is greater.
Based on this, the embodiment of the application provides a packaging structure and a manufacturing method thereof, so as to solve the problems of uneven filling of underfill and easy solder short circuit caused by the memory TSV silicon through hole lamination packaging technology in the prior art.
The solution provided by the embodiment of the present invention will be described in detail from the viewpoint of the construction of the resulting package structure of one of the embodiments.
Referring to fig. 1, the embodiment provides a vertical cross-sectional view of a package structure according to an embodiment, as shown in fig. 1, where the package structure in the embodiment of the application includes: the chip comprises a substrate, a chip attached to one side surface of the substrate, a plastic layer wrapping the chip on the substrate, and external pins attached to one side surface of the substrate away from the chip.
In this embodiment, the chip includes: at least two wafer layers; an interconnect through at least one wafer layer; wherein the interconnect comprises a metal post, solder, and a connection post; bonding layers between two adjacent wafer layers; the metal columns are embedded into the solder, and the bonding layer wraps the solder and fills the functional surfaces of the two adjacent wafer layers. Please refer to fig. 2, wherein the functional surface is a surface on each wafer layer for bonding other wafer layers. It can be understood that the metal posts and the solder are arranged on the surfaces, which are contacted with each other, of the two adjacent wafer layers, and the metal posts are embedded by the solder and form a connecting structure, namely an interconnection piece, between the two adjacent wafer layers with the connecting posts on the through holes.
In this embodiment of the present application, the height and width of the metal pillar in this application may be set according to needs, and exemplary, the diameter of the metal pillar may be 2 micrometers to 20 micrometers, for example, the diameter may be 5 micrometers, 10 micrometers, 15 micrometers, etc. set, and the diameter is lower than the conventional setting (generally 25 micrometers) in the prior art, so that the interconnection elements on the wafer layer may be arranged in a density manner in this application, and due to the preparation manner of the chip, the yield of the device may be satisfied on the basis of high density, and the problem of solder short circuit that is easy to cause is avoided.
Further, the height-width ratio of the metal column can be 1 to 10, the height-width ratio can be adjusted according to the setting, for example, the height-width ratio can be 5,6,7, and the like, so that the adjustable aspect ratio is used for adjusting the height between two adjacent layers of wafer layers to enable the resistivity of the chip to be lower, the reliability to be improved, and the parallelism between the layers can be adjusted after the metal column is used for adjusting the height between the two adjacent layers of wafer layers, so that the manufactured chip is better in flatness and uniform in thickness through the uniform height.
In the embodiment of the application, the metal pillar material may be copper, gold, nickel-copper material, or nano-wire, such as nano-gold wire, nano-silver wire, nano-copper wire, etc. The material of the metal post surface protection material layer can be Ni Au, paAu, niPaAu and the like.
In one possible embodiment, the functional surface of the wafer layer may include metal posts or solder thereon.
Further, the surface of the metal post includes a protective layer.
In another embodiment, the package structure may also include: the chip comprises a wafer layer, a chip attached to one side surface of the wafer layer, a plastic sealing layer wrapping the chip on the wafer layer, and external pins attached to one side surface of the wafer layer away from the chip.
As an implementation method, referring to fig. 3, the steps of the chip manufacturing method may include:
s1, providing at least two wafer layers; the wafer layer comprises a surface layer and at least one middle layer; the middle layer is provided with a through connecting column; a bonding layer is arranged on the functional surface of the middle layer and the surface layer; the functional surface of the middle layer and the surface layer is also provided with a metal column or solder; solder is positioned in the groove of the bonding layer; wherein the height of the solder is smaller than the height of the groove; and the width of the solder is smaller than the width of the groove;
s2, stacking the wafer layers in sequence and hot-pressing the wafer layers to enable metal columns of two adjacent wafer layers to be embedded into solder and form an interconnection piece with the connecting columns; the bonding layer wraps the solder and fills the functional surfaces of the two adjacent wafer layers; the functional surface is a surface on each wafer layer for bonding other wafer layers.
In another implementation method, referring to fig. 4, after the steps of stacking wafer layers in sequence and hot-pressing in the chip manufacturing method, the method may further include:
s3, cutting the wafer layer after hot pressing according to a preset cutting path;
s4, flip-chip mounting the cut wafer layer on the substrate;
s5, performing plastic packaging on one surface of the substrate close to the wafer layer;
s6, preparing external pins on one surface of the substrate far away from the wafer layer.
In one embodiment, the substrate in the package structure 100 is used as a carrier of the package structure 100 to provide support protection, and specifically any carrier or carrier-like structure can be used, and the substrate can be designed to include or not include interconnection lines according to requirements. In some possible embodiments, the substrate may be made of a composite material of organic materials such as BT material, ABF material, MIS material, PI resin material, and PE resin material. In other possible embodiments, the substrate may also be made of ceramic materials such as alumina, aluminum nitride, or silicon carbide. In other embodiments, the substrate may be made of copper, glass, silicon, or other suitable materials. Since the substrate according to the embodiment of the invention is a permanent substrate as a package structure (i.e. it is not required to be removed in the packaging process), it can provide a supporting protection effect for the package structure, and for example, when the substrate is made of a material with good thermal conductivity, such as copper, it can also provide an enhanced heat dissipation effect for a chip mounted thereon, so that the package structure has a more excellent heat dissipation effect.
In one implementation, the external pins in the package structure 100 may include: the solder ball is used for providing an interface for external connection of the whole packaging structure, and specifically can be arranged on the surface of the substrate, which is away from the chip, and corresponds to the through silicon via (or the redistribution layer RDL) on the bottom wafer layer through the through silicon via on the substrate so as to form at least partial electrical connection with the metal column on the chip. Thereby, by electrically interconnecting the external device with the solder balls.
In the embodiment of the present application, the plastic sealing layer may be prepared from a plastic sealing material commonly used in the art, and the specific material is not particularly limited in the embodiment of the present invention.
Referring to fig. 5, the step S1 of providing at least three wafer layers in the above-mentioned package structure by providing a chip manufacturing method includes the following steps:
a1, arranging blind holes on the middle layer;
a2, arranging an insulating layer on the inner wall of the blind hole;
a3, arranging a metal filling layer on the inner wall of the insulating layer to obtain a through connecting column.
It can be appreciated that in embodiments of the present application, it may be preferable to prepare at least two wafer layers; the wafer layer includes a surface layer and at least one intermediate layer, please refer to fig. 6, in one embodiment, the surface layer may include a top layer, a bottom layer and at least one intermediate layer, wherein the surface of the wafer layer is correspondingly provided with metal pillars and solder; wherein, at least the middle layer is provided with a through connecting column so as to form an interconnection structure with the metal column and the solder arranged on the top layer and the bottom layer. Wherein, the interlayer is provided with a through hole, the through hole can be used for preparing a blind hole in the wafer by adopting the technologies of photoetching, deep silicon etching, pecvd, metal sputtering, electroplating, chemical plating and the like, the inner side wall of the blind hole is sequentially deposited with an insulating layer, adhesion/diffusion barrier layer metal and electroplating seed layer metal, and the hole is filled with conductive metal (such as electroplated copper). Exemplary, please refer to fig. 7, 8-9, which are schematic structural diagrams of a top layer, a bottom layer and at least one middle layer according to an embodiment of the present application.
For example, referring to fig. 10, in the embodiment of the present application, an insulating layer is required to be disposed on the inner wall of the through hole to avoid affecting the electrical performance of the device.
In another embodiment, referring to fig. 11, for example, when blind holes or through holes are formed in the underlying wafer layer, after the underlying wafer layer is subtracted, the blind holes are formed in the wafer by using the above-mentioned hole forming method, and then the insulating layer is filled in the blind holes sequentially.
Referring to fig. 12, step S1 of at least three wafer layers in the embodiment of the present application includes the following steps:
b1, coating a bonding material layer on a functional surface provided with solder;
b2, arranging a groove at a target position of the bonding material layer to expose the solder on the wafer layer, and taking the functional surface provided with the solder as an etching stop layer;
wherein, the height and width of the groove are smaller than the height and width of the solder.
In this application is implemented, can prepare connection structure respectively on the functional face on top layer wafer layer, intermediate level wafer layer and bottom wafer layer respectively to when the bonding of follow-up hot pressing, constitute interconnect with the conductive metal that the through-hole was filled, further, this top layer wafer layer and bottom wafer layer are last the connection structure that sets up different, can understand, when preparing the metal column at top layer wafer layer, this bottom wafer layer then corresponds the preparation solder, in order to accomplish the bonding hot-pressing on multilayer wafer layer, form interconnect.
The bonding layer is prepared at least on the functional surface corresponding to the solder, and it is understood that, for example, in the intermediate layer, on the functional surface for preparing the metal pillar, the functional surface provided with the metal pillar is used as an etching stop layer. Further, the bonding layer may be prepared by referring to fig. 13, for example, a bonding material layer may be coated on the functional surface corresponding to the solder, and the bonding material may be an insulating permanent bonding material, for example, a photosensitive bonding material and a non-photosensitive permanent bonding material, for example: NCF, SU8, PPMA, etc. lithographically. For example, when the bonding material layer is coated on the functional surface of the wafer layer, the functional surface may be understood as a wafer layer contacting with an adjacent wafer layer, that is, a surface on each wafer layer for bonding other wafer layers, for example, when the bottom wafer layer is provided with solder, the functional surface of the bottom wafer layer is a side on which the bottom wafer layer is provided with solder; correspondingly, the functional surface of the top wafer layer can be understood as one side of the top wafer layer, on which the metal column is arranged; the functional surface of the intermediate layer wafer layer is understood to be the side of the intermediate layer wafer layer on which the metal pillars or solder are provided.
In this embodiment of the present application, after thermal compression bonding, the metal pillars of two adjacent wafer layers may be embedded into the solder, so that the portion of the metal pillars embedded into the solder is covered by the solder, and the solder covering the metal pillars wets the surface of the metal pillars, i.e. the upper surface and the side surface of the metal pillars, to form the alloy layer.
After the bonding material layer is applied, the bonding material layer covering the metal posts and/or solder can be removed by photolithography or laser to form grooves exposing the metal posts and/or solder on the wafer layer. Wherein the height of the solder is smaller than the height of the groove; and the width of the solder is smaller than the width of the recess, the arrangement can be understood as: and a certain gap exists between the bonding material and the connecting structure (the metal column and/or the solder) so that material particles filled in the bonding material cannot be extruded to a connecting interface of the metal column and the solder in the bonding process, and the filling material particles are prevented from being present between the bonded metal column and the solder, so that the metal column is completely wrapped by the solder, and the solder is completely wrapped by the bonding layer. Based on the above, the grooves can provide storage space for melted solder in the process of embedding and fixing the metal columns and the solder in the process of thermocompression bonding, so that the solder (holder) is prevented from being extruded to the periphery to generate short circuit between welding spots.
Referring to fig. 14, when the surface layer includes a top layer and metal pillars are disposed on a functional surface of the top layer, step S1 of at least three wafer layers in the embodiment of the present application includes the following steps:
c1, preparing at least one metal column, wherein the surface of the metal column is provided with a protective layer;
c2, transferring the metal column to a temporary carrier plate;
and C3, attaching the metal column to the target position of the functional surface of the top layer based on the temporary carrier plate so as to correspond to the solder on the functional surface of the middle layer.
In this embodiment, when the top wafer layer is prepared, the metal pillars or the solder joints may be prepared only on one side surface of the top wafer layer, and the metal pillars may be disposed on one side of the top wafer layer, which is close to the middle wafer layer, and the preparation manner of the metal pillars may refer to the manner of preparing the metal pillars, which is not described herein again.
In this embodiment, please refer to fig. 15, a metal column with a preset height is prepared based on the temporary carrier, the height of the metal column can be set according to needs, and the spacing between bonded wafer layers can be limited by the metal column with the preset height, so as to avoid electrical short circuit between bumps due to overflow of solder to two sides. It will be appreciated that in embodiments of the present application, the metal posts (holders) are embedded in the insert solder (holder) and that the molten solder (holder) extends upwardly along the metal posts (holders) during bonding, thereby preventing the solder (holder) from extruding around and creating inter-pad shorts.
In the practical embodiment, the material of the metal column may be copper and/or gold and/or nickel copper electroless plating, or nano-wires, such as nano-gold wires, nano-silver wires, nano-copper wires, and the like.
In one possible embodiment, the metal pillars may have a height of 5-20 microns in diameter and a ratio of aspect ratio may range from (1:1-10:1).
Wherein in this embodiment, subtractive, photolithographic, electroplating and/or electroplating processes may be employed to prepare metal pillars on a side surface of the wafer layer, which may be the functional side and/or the backside of the wafer layer; the surface of the metal column is also wrapped with a diffusion insulating layer. In this embodiment, the metal post (pilar) surface is provided with a protective layer, which can be understood as: an adhesion layer or/and a copper diffusion barrier layer is/are coated on the surface of the metal column (pilar), and a soldering tin or/and a soldering wetting layer can be coated outside the diffusion barrier layer to serve as an oxidation layer for preventing oxidation of the metal column.
Further, the step of transferring the metal pillars to the temporary carrier comprises:
a temporary bonding material layer is arranged on the temporary carrier plate; and transferring the metal posts to the surface of the temporary bonding material layer so as to attach the metal posts to the functional surface of the top layer through the temporary bonding material layer.
Referring to fig. 15, the metal column may be prepared by: and attaching the prepared metal posts on a temporary carrier plate with a temporary bonding material, and transferring the temporary carrier plate to a wafer layer provided with through holes so as to be correspondingly contacted with the through holes to form the interconnection piece. In some exemplary embodiments, a temporary bonding material is attached to a temporary carrier to form a temporary bonding structure, where the temporary bonding material may be a thermal bonding film, a photolytic bonding film, or the like, and the temporary carrier needs to be removed during a subsequent bonding process, and the structure of the removed top wafer layer is schematically shown in fig. 16. In this embodiment, the metal pillars are transferred and fixed at predetermined positions to form an interconnection structure in one-to-one correspondence with solder joints, vias, etc. in subsequent bonding.
In this embodiment, the metal pillars on the wafer layer may partially participate in the preparation of the interconnection lines, that is, some metal pillars are directly electrically connected to the vertical interconnection members, and the other metal pillars do not participate in the electrical connection, but only serve as mechanical supports, so as to maintain the flatness of the laminated chip between the layers after lamination, so that the flatness is higher, the uniformity is better, and the stability of the device is improved.
In another possible embodiment, the metal posts can be directly prepared to the functional surface on the top layer.
Further, the step of transferring the metal pillars to the temporary carrier comprises:
a temporary bonding material layer is arranged on the temporary carrier plate; and transferring the metal posts to the surface of the temporary bonding material layer so as to attach the metal posts to the functional surface of the top layer through the temporary bonding material layer.
In one embodiment, the top wafer layer may not require through silicon vias. The top wafer layer may be reduced back to a thickness, and the top wafer layer has a thickness greater than the middle wafer layer. For example, the metal posts may be disposed directly at target locations on the functional side of the top wafer layer to correspond to connection structure locations on the middle wafer layer.
Referring to fig. 17, the surface layer includes a top layer, and when solder is disposed on a functional surface of the top layer, step S1 of at least three wafer layers in the embodiment of the present application includes the following steps:
d1, preparing a connecting column on the functional surface of the top layer;
d2, preparing solder at the target position on the functional surface of the top layer so as to connect the solder with the connecting column.
In this embodiment, when preparing the top wafer layer, metal pillars or solder joints may be prepared on only one side surface of the top wafer layer, referring to fig. 18 for example, solder points may be disposed on one side of the top wafer layer, which is close to the middle wafer layer, and the preparation method of the solder belt is as follows:
And preparing solder on one side of the top wafer layer, which is close to the middle wafer layer, by photoetching, sputtering, electroplating/chemical plating and the like, wherein the bottom wafer layer can be used for preparing through silicon vias in advance and filling a metal layer. The solder is correspondingly prepared on the metal via hole. Illustratively, the solder may be disposed on the functional side of the underlying wafer layer.
In one embodiment, referring to fig. 19, if the top wafer layer already includes the connection posts, the top back can be reduced to a certain thickness to expose the connection posts on the wafer layer and ensure that the top wafer layer has a greater thickness than the middle wafer layer.
In another embodiment, referring to fig. 20, the top wafer layer may not have a connection post, and during the solder preparation process, the solder may be directly prepared by photolithography, sputtering, electroplating/electroless plating on a side near the middle wafer layer, where the position of the solder needs to correspond to the metal post disposed on the functional surface of the middle layer.
In an embodiment, when the surface layer includes a top layer and a bottom layer, the middle layer includes a first functional surface and a second functional surface, where solder and a metal pillar are respectively disposed on the first functional surface and the second functional surface, the method for providing at least two wafer layers S1 in this embodiment includes the following steps:
Preparing at least one metal column at a target position of the functional surface of the top layer so as to correspond to the solder on the first functional surface, wherein a protective layer is arranged on the surface of the metal column;
and preparing solder at the target position on the functional surface of the bottom layer to correspond to the metal column on the second functional surface, so that the solder is connected with the connecting column of the middle layer.
In another embodiment, when the surface layer includes a top layer and a bottom layer, the middle layer includes a first functional surface and a second functional surface, where solder and metal pillars are disposed on the first functional surface and the second functional surface respectively, the method for providing at least two wafer layers S1 further includes the following steps:
preparing at least one metal column, wherein the surface of the metal column is provided with a protective layer;
transferring the metal column to a temporary carrier plate;
attaching a metal column to a target position of a functional surface of the top layer based on the temporary carrier plate so as to correspond to the solder on the first functional surface;
and preparing solder at the target position on the functional surface of the bottom layer to correspond to the metal column on the second functional surface, so that the solder is connected with the connecting column of the middle layer.
In this embodiment, when the surface layer includes a top layer and a bottom layer, and the middle layer includes a first functional surface and a second functional surface, the structure of the at least two wafer layers is shown in fig. 21.
In one embodiment, referring to fig. 22, the step S2 of stacking and hot-pressing wafer layers sequentially includes the following steps:
e1, fixing two adjacent wafer layers so that metal columns of the two adjacent wafer layers correspond to solder one by one;
and E2, performing primary thermocompression bonding on the wafer layer in the vacuum bonding chamber.
In one possible embodiment, referring to fig. 23, two adjacent wafer layers may be fixed by using a positioning clamp, and it may be appreciated that the positioning clamp aligns the solder and metal pillars on the two adjacent wafer layers to ensure the accuracy between the stacked wafer layers when the wafer layers subsequently enter the vacuum bonding chamber for thermocompression bonding. Referring to fig. 24, the metal posts are completely bonded with the solder in the vacuum bonding chamber under high temperature and high pressure conditions, i.e. the metal posts are embedded in the solder and are encapsulated by the solder. In this bonded structure, the solder wraps the metal posts, and the surface of the solder is curved due to the liquid tension under the condition of heating and pressurizing, and the examples of the drawings are only referred to herein.
Further, in this embodiment, the depth of the metal pillar embedded into the solder can also be adjusted to adaptively adjust the package structure of the chip, i.e. the inter-layer spacing between two adjacent wafer layers in the chip, so as to reduce the resistivity of the chip and improve the inter-chip parallelism.
In another embodiment, the two adjacent wafer layers may be pre-bonded, that is, it may be understood that the metal pillars and the solder are pre-bonded by using a thermocompression bonding process, where the pre-bonding method specifically includes pre-bonding the two adjacent wafer layers so that the metal pillars of the two adjacent wafer layers are partially embedded in the solder; in the vacuum bonding chamber, performing primary hot-press bonding on two adjacent wafer layers after pre-bonding to completely embed the metal columns of the two adjacent chips into the solder and form an interconnection piece with the connecting columns; and the bonding layer wraps the solder and fills the functional surfaces of the adjacent two layers of chips.
It can be understood that under the conventional environment (vacuum condition in the non-vacuum bonding cabin), the alignment of the metal pillar and the solder is realized, the metal pillar and the solder can be partially bonded under the condition of heating and pressurizing, only the metal pillar and the solder are half-embedded, and a certain gap exists between the insulating bonding materials, refer to fig. 25. In the embodiment, after a certain gap is reserved between the insulating bonding materials, air in the gap is discharged from a vacuum bonding cavity through a hot-press bonding process in a vacuum environment of the vacuum bonding cavity, so that accurate alignment of the metal column and the solder is realized to a certain extent, and bubbles in the bonding process of the metal column and the solder are avoided, and stability of the packaged device is prevented from being influenced.
After the pre-bonding is completed, transferring the wafer to a vacuum bonding chamber, and performing hot-press bonding on the adjacent laminated wafer layers after the pre-bonding in the vacuum bonding chamber to obtain a bonded wafer assembly. The prepared wafer layer is then superimposed over the bonded wafer assembly this time. Referring to fig. 26, the bonded laminated wafer assembly includes a plurality of wafer layers, which may be, in order, a top wafer layer, at least one middle wafer layer, and a bottom wafer layer. In this embodiment, the metal pillars on the stacked chip may partially participate in the preparation of the interconnection line, that is, some metal pillars are directly electrically connected to the vertical interconnection element, and the other metal pillars do not participate in the electrical connection, but only serve as mechanical supports, so as to maintain the flatness of the stacked chip between layers after lamination, so that the flatness is higher, the uniformity is better, and the stability of the device is improved.
In one possible embodiment, the temporary bonding material provided on the temporary carrier plate is removed during thermocompression bonding.
After the laminated wafer assembly is obtained by thermocompression bonding, the laminated wafer assembly may be attached to a temporary carrier with bonding material, and the temporary carrier and the temporary bonding material may be referred to above and will not be described herein. After transferring to the temporary carrier plate, the back surface of the bottom wafer layer can be thinned to expose the vertical interconnection line, wherein the interconnection line is composed of a metal column, a metal material layer filled in the silicon through hole and solder. And preparing RDL and external connection pin pads or solder balls at corresponding positions of corresponding interconnection lines to obtain the prepared laminated chip.
The inventor also finds that a packaging mode is adopted in the prior art, namely TSV bump, metal column (pilar) or solder is prepared on a chip, and NCF is uniformly covered on the metal column or solder; or the bonding pad is coated with NCP, then the NCP or NCF on the surface of the metal column (pilar) or the solder is discharged under the condition of heating and pressurizing by using a TCB bonder, and the bonding between the metal column (pilar) or the solder and the NCP or the NCF is realized, but a certain amount of filling material exists in the solder on the surface of the welded metal column (pilar), so that the packaged device chip is short-circuited, the reliability is influenced, and the solder is easy to extrude.
In another embodiment, referring to fig. 27, the step S2 of stacking and hot-pressing the wafer layers sequentially further includes the following steps:
f1, respectively cutting the intermediate layer and the surface layer in the vacuum bonding cavity according to a preset cutting path to respectively obtain a first chip and a second chip;
f2, sequentially thermocompression bonding the first chip and the second chip onto the substrate to sequentially embed the metal columns of the adjacent two layers of chips into solder and form an interconnection piece with the connecting columns; and the bonding layer wraps the solder and fills the functional surfaces of the adjacent two layers of chips.
Referring to fig. 28 and 29, the wafer layer is divided into a single row or column of chips according to a predetermined dicing street, i.e. the wafer layer is diced into equally spaced chips, wherein the chips of the adjacent layer of the wafer layer are diced to serve as the second chips. Referring to fig. 30, the first die is then transferred to a substrate, and in one embodiment, the diced first die may be bonded to the substrate by TCB equipment, the substrate may be a supporting wafer, the supporting wafer is not thinned, and then the diced die are sequentially bonded in a stacked manner, i.e., metal pillars are bonded to solder, in that order. In this embodiment, the substrate may be made of a composite material of organic materials such as BT material, ABF material, MIS material, PI resin material and PE resin material. In other possible embodiments, the substrate may also be made of ceramic materials such as alumina, aluminum nitride, or silicon carbide. In other embodiments, the substrate may be made of copper, glass, silicon, or other suitable materials. Based on the above embodiment, on the basis of the pressed first chip, please refer to fig. 30, a second chip is thermocompression bonded to the first chip in order to prepare the metal pillars, solder, and connection pillars into the interconnect.
After bonding is completed, plastic packaging can be directly performed, then back thinning is performed on the chip substrate after plastic packaging so as to expose the vertical interconnection lines of the chips, and then external pins and solder balls are prepared on one side of the substrate away from the laminated chips. The prepared device is then cut into individual pieces.
In another embodiment, referring to fig. 31, the step S2 of stacking and hot-pressing the wafer layers sequentially further includes the following steps:
h1, respectively cutting the intermediate layer and the surface layer according to preset cutting channels to respectively obtain a first chip and a second chip;
h2, thermocompression bonding the first chip to the substrate;
h3, pre-bonding the first chip and the second chip to enable the metal posts of the two adjacent layers of chips to be partially embedded into the solder;
carrying out primary hot-press bonding on the first chip and the second chip which are subjected to pre-bonding in the vacuum bonding cavity so as to completely embed the metal columns of the two adjacent layers of chips into solder and form an interconnection piece with the connecting columns; and the bonding layer wraps the solder and fills the functional surfaces of the adjacent two layers of chips.
In this embodiment, after the wafer layer is divided into a single row or column of chips according to the preset dicing street, the first chip is then transferred to the substrate or wafer, in another possible embodiment, the diced chips may be bonded to the substrate by using a TCB device, where the substrate may be a supporting wafer, and the supporting wafer is not thinned, and then the diced chips are sequentially laminated and bonded to the solder in order, i.e., by using metal columns. Referring to fig. 32, unlike the previous embodiment, in the step of bonding the cut chip on the substrate or the wafer by using the TCB apparatus, the cut chip is pre-bonded first, that is, it can be understood that the metal pillars and the solder are pre-bonded by using a thermocompression bonding process, and the pre-bonding manner is that, under a conventional environment (a vacuum condition in the non-vacuum bonding chamber), the alignment of the metal pillars and the solder is achieved, and the metal pillars and the solder can be partially bonded under the condition of heating and pressurizing, and only the metal pillars and the solder are partially embedded at this time, and a certain gap exists between the insulating bonding materials. In the embodiment, after a certain gap is reserved between the insulating bonding materials, air in the gap is discharged from a vacuum bonding cavity through a hot-press bonding process in a vacuum environment of the vacuum bonding cavity, so that accurate alignment of the metal column and the solder is realized to a certain extent, and bubbles in the bonding process of the metal column and the solder are avoided, and stability of the packaged device is prevented from being influenced.
In this embodiment, the step after pre-bonding may be implemented in a non-vacuum bonding cavity, and further, the pre-bonded chip is integrally bonded in the vacuum bonding cavity through a thermocompression bonding process.
Further, each time a chip is pre-bonded in a lamination, repeated thermocompression bonding for a plurality of times can form a multi-layer stacked pre-bonded device, and the temperature of the bottom device needs to be kept below the melting point of soldering tin during thermocompression bonding. Heating and pressurizing the whole multi-layer stack body of the multi-layer chip subjected to pre-bonding in the vacuum bonding cabin to completely bond, so that the metal columns are embedded into the final positions of the solder to form final welding; and the insulating permanent bonding material is solidified and bonded, gaps of chips of each layer are filled, and the solder is wrapped, so that welding spots of adjacent solder and the metal column are completely isolated.
In this embodiment, in the pre-bonding process, it is necessary to ensure that the height between the adjacent solder and the metal post is not depressed to the minimum, and to reserve a certain height, so that a certain gap is left on the bonding material, so that air is pumped away in the vacuum bonding cavity, and no air hole or no hole is ensured during bonding.
Further, before the integral bonding, the contamination and oxidation of the metal posts and the solder surface may be treated with formic acid and plasma acid to activate the bonding material surface, which may be performed in a thermocompression bonding apparatus.
In summary, the embodiment of the application provides a chip manufacturing method, which includes: comprises providing at least two wafer layers; the wafer layer comprises a surface layer and at least one middle layer; the middle layer is provided with a through connecting column; a bonding layer is arranged on the functional surface of the middle layer and the surface layer; the functional surface of the middle layer and the surface layer is also provided with a metal column or solder; solder is positioned in the groove of the bonding layer; wherein the height of the solder is smaller than the height of the groove; and the width of the solder is smaller than the width of the groove; stacking the wafer layers in sequence and hot-pressing the wafer layers so that metal columns of two adjacent wafer layers are embedded into solder and form an interconnection piece with the connecting columns; and the bonding layer wraps the solder and fills the functional surfaces of the two adjacent wafer layers. The method solves the problems that the bottom filling glue is not uniformly filled, which is easily caused by the memory TSV silicon through hole lamination packaging technology in the prior art, for example, the memory TSV silicon through hole lamination packaging technology easily causes filler particles, air holes or holes in solder, and the solder is easy to cause solder short circuit, and reduces the risk of solder short circuit.
Specifically, it can be understood that in this embodiment, different metal pillars and solder joints are respectively prepared on the two side surfaces of a wafer or a chip (a cut wafer), so that the bonded metal pillars are embedded into the solder joints, the height of the metal pillars is controllable to adjust the circumference or the chip spacing after bonding, meanwhile, as the height of the bonding material layer is higher than that of the metal pillars and/or solder and a certain gap exists between the bonding material layer and the metal pillars and/or solder, the quantity of overflowed solder to two sides in the bonding process is extremely small, and filler material particles are prevented from existing between the bonded metal pillars and solder, so that electrical short circuit between the bumps is not easy to occur in the packaged device, and the reliability of the packaged device is higher.
The present invention is not limited to the above embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims (17)

1. The chip manufacturing method is characterized by comprising the following steps of:
providing at least two wafer layers; the wafer layer comprises a surface layer and at least one middle layer; the middle layer is provided with a through connecting column; a bonding layer is arranged on the functional surface of the middle layer and the surface layer; the functional surface of the middle layer and the surface layer is also provided with a metal column or solder; the solder is positioned in the groove of the bonding layer; wherein the height of the solder is smaller than the height of the groove; and the width of the solder is smaller than the width of the groove;
stacking and hot-pressing the wafer layers in sequence, so that metal columns of two adjacent wafer layers are embedded into the solder and form an interconnection piece with the connecting columns; the bonding layer wraps the solder and fills the functional surfaces of the two adjacent wafer layers; the functional surface is a surface on each wafer layer for bonding other wafer layers.
2. The method of claim 1, wherein the step of providing at least two wafer layers comprises:
coating a bonding layer on the functional surface provided with the solder;
arranging the grooves at target positions of the bonding layer to expose the solder on the wafer layer, and taking the function surface provided with the solder as an etching stop layer;
wherein the height of the solder is smaller than the height of the groove; and the width of the solder is smaller than the width of the groove.
3. The method of claim 1, wherein the step of providing at least two wafer layers further comprises:
a blind hole is formed in the middle layer;
an insulating layer is arranged on the inner wall of the blind hole;
and filling a metal filling layer on the inner wall of the insulating layer to obtain the through connecting column.
4. The method of claim 1, wherein the surface layer comprises a top layer, and the step of providing at least two wafer layers when the metal pillars are disposed on the functional surface of the top layer comprises:
preparing at least one metal column, wherein the surface of the metal column is provided with a protective layer;
transferring the metal columns to a temporary carrier plate;
And pasting the metal posts on the target positions of the functional surfaces of the top layers based on the temporary carrier plates so as to correspond to the solders on the functional surfaces of the middle layers.
5. The method of claim 1, wherein the surface layer comprises a top layer, and wherein the step of providing at least two wafer layers when solder is disposed on the functional surface of the top layer comprises:
preparing a connecting column on the functional surface of the top layer;
solder is prepared at the target locations on the functional side of the top layer to connect the solder with the connection posts.
6. The method of manufacturing a chip according to claim 1, wherein the surface layer includes a top layer and a bottom layer, the middle layer includes a first functional surface and a second functional surface, solder and metal pillars are respectively disposed on the first functional surface and the second functional surface, and the step of providing at least two wafer layers includes:
preparing at least one metal column at a target position of the functional surface of the top layer so as to correspond to the solder on the first functional surface, wherein a protective layer is arranged on the surface of the metal column;
and preparing solder at a target position on the functional surface of the bottom layer so as to correspond to the metal column on the second functional surface, and connecting the solder with the connecting column of the middle layer.
7. The method of manufacturing a chip according to claim 1, wherein the surface layer includes a top layer and a bottom layer, the middle layer includes a first functional surface and a second functional surface, solder and metal pillars are respectively disposed on the first functional surface and the second functional surface, and the step of providing at least two wafer layers includes:
preparing at least one metal column, wherein the surface of the metal column is provided with a protective layer;
transferring the metal columns to a temporary carrier plate;
attaching the metal posts to target positions of the functional surfaces of the top layer based on the temporary carrier plate so as to correspond to the solders on the first functional surface;
and preparing solder at a target position on the functional surface of the bottom layer so as to correspond to the metal column on the second functional surface, and connecting the solder with the connecting column of the middle layer.
8. The chip manufacturing method according to claim 4 or 7, wherein the step of transferring the metal pillars to a temporary carrier plate comprises:
a temporary bonding layer is arranged on the temporary carrier plate;
and transferring the metal posts to the surface of the temporary bonding layer so as to attach the metal posts to the functional surface of the top layer through the temporary bonding layer.
9. The method of claim 1, wherein the step of sequentially stacking and thermally pressing the wafer layers comprises:
fixing two adjacent wafer layers so that metal columns of the two adjacent wafer layers correspond to solder one by one;
and performing one-time thermocompression bonding on the wafer layer in the vacuum bonding chamber.
10. The method of claim 1, wherein the step of sequentially stacking and thermally pressing the wafer layers comprises:
pre-bonding two adjacent wafer layers to enable metal columns of the two adjacent wafer layers to be partially embedded into solder;
performing primary hot-press bonding on the two adjacent wafer layers after pre-bonding in a vacuum bonding cavity so as to completely embed the metal columns of the two adjacent chips into the solder and form an interconnection piece with the connecting columns; and the bonding layer wraps the solder and fills the functional surfaces of the adjacent two layers of chips.
11. The method of claim 1, wherein the step of sequentially stacking and thermally pressing the wafer layers further comprises:
cutting the intermediate layer and the surface layer respectively according to a preset cutting path in the vacuum bonding cavity to obtain a first chip and a second chip respectively;
Sequentially thermocompression bonding the first chip and the second chip to a substrate to sequentially embed metal columns of two adjacent layers of chips into the solder and form an interconnection with the connecting columns; and the bonding layer wraps the solder and fills the functional surfaces of the adjacent two layers of chips.
12. The method of claim 1, wherein the step of sequentially stacking and thermally pressing the wafer layers further comprises:
cutting the middle layer and the surface layer respectively according to preset cutting channels to obtain a first chip and a second chip respectively;
thermocompression bonding the first chip to a substrate;
pre-bonding the first chip and the second chip so that metal posts of two adjacent layers of chips are partially embedded into solder;
in the vacuum bonding chamber, performing primary hot-press bonding on the first chip and the second chip after pre-bonding so as to completely embed the metal columns of the two adjacent layers of chips into the solder and form an interconnection piece with the connecting columns; and the bonding layer wraps the solder and fills the functional surfaces of the adjacent two layers of chips.
13. The method of manufacturing a chip according to claim 1, wherein after the step of sequentially stacking and thermally pressing the wafer layers, further comprises:
Cutting the wafer layer after hot pressing according to a preset cutting path;
flip-chip mounting the cut wafer layer on a substrate;
performing plastic packaging on one surface of the substrate close to the wafer layer;
and preparing external pins on one surface of the substrate far away from the wafer layer.
14. A package structure, comprising:
a substrate;
a chip attached to one side surface of the substrate; wherein the chip is prepared by the method of any one of claims 1 to 13;
the external pins are attached to the surface of one side of the substrate far away from the chip;
and wrapping the plastic sealing layer of the chip on the substrate.
15. The package structure of claim 14, wherein the chip comprises:
at least two wafer layers;
an interconnect through at least one wafer layer; wherein the interconnect comprises a metal post, solder, and a connection post;
bonding layers between two adjacent wafer layers; the bonding layer wraps the solder and the metal columns and fills the functional surfaces of the two adjacent wafer layers;
the functional surface is a surface on each wafer layer for bonding other wafer layers.
16. The package structure of claim 15, wherein the functional surface of the wafer layer includes the metal posts or the solder thereon.
17. The package structure of claim 15, wherein a surface of the metal pillar comprises a protective layer.
CN202311516986.3A 2023-11-14 2023-11-14 Chip manufacturing method and packaging structure Pending CN117316787A (en)

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