CN117295341A - Ferroelectric nonvolatile memory and preparation method thereof - Google Patents

Abstract

The invention provides a ferroelectric non-volatile memory and a preparation method. The memory includes a substrate, a source-side control gate, a storage gate and a drain-side control gate arranged in sequence above the substrate; wherein, a source side control gate is arranged on the substrate. electrode and drain, the substrate area between the source and drain forms a channel that isolates the source and drain; a ferroelectric layer is provided between the channel and the memory gate, and the memory gate is used to feed the ferroelectric layer Apply voltage to the upper surface of the ferroelectric layer to change the polarization state of the ferroelectric layer; the source side control gate and the drain side control gate are used to control the channel on or off; by controlling the storage gate, source, source side control gate, drain side Control the voltage of the gate and drain to realize data writing, reading and erasing. The above invention can increase storage density, reduce power consumption and enhance reliability.

Description

Ferroelectric non-volatile memory and preparation method

Technical field

The present invention relates to the field of memory technology, and more specifically, to a ferroelectric non-volatile memory and a preparation method.

Background technique

Nonvolatile (nonvolatile) storage devices have the characteristics of not losing data after power failure, and can be seen everywhere in the contemporary information society. With the development of the semiconductor industry and the popularization of embedded applications such as specialized hardware and the Internet of Things, the industry has also put forward higher requirements for non-volatile memory power consumption, speed, storage density, reliability, erasure and write endurance and other performances. Require.

Currently, ferroelectric field effect transistors (FeFETs) use ferroelectric films to replace the gate oxide in the MOSFET structure to use the polarization of the ferroelectric films to adjust the channel on and off states; by applying voltages of different polarities to the gate , which can control the residual polarization of the ferroelectric layer to switch between two directions to achieve the purpose of storing "0" and "1". It has fast erasing and writing speed, low operating voltage, high storage density, non-destructive readout and repeated erasing. Strong writing skills and other advantages. However, there are still some problems with FeFETs with traditional structures.

First of all, the traditional 1T structure FeFET memory has storage density and reliability problems due to write crosstalk. Traditional memory array programming operations require voltages to be applied to the gate (word line) and drain (bit line) at the same time. Therefore, in a cross array structure, memory cells at the intersection of specific word lines and bit lines can be individually selected and programmed. In contrast, the FeFET with a 1T structure cannot achieve cross selection by itself because the programming operation is only controlled by the voltage of the gate relative to the channel. Additional gate devices are required when constructing a cross array structure, resulting in a reduction in integration density.

Secondly, potential leakage current reduces the reliability of memory data and increases power consumption. Since the FeFET threshold voltage has strong fluctuations and the device threshold voltage is lower when the polarization direction of the ferroelectric layer is downwards; the threshold voltage shift may cause the FeFET threshold voltage of the downward polarization direction to be lower than 0V and remain on when not selected. state, significantly increasing leakage current, resulting in poor reliability and increased power consumption. To mitigate the effects of leakage current, higher threshold voltages are often used in FeFET memory designs. However, the higher threshold voltage makes the gate voltage also higher when reading data, which will cause a strong electric field in the ferroelectric layer and interfere with the polarization state of the ferroelectric layer; that is, the corresponding memory cell will be weakly programmed when reading data. . Therefore, using a higher threshold voltage cannot effectively improve memory reliability.

Contents of the invention

In view of the above problems, the purpose of the present invention is to provide a ferroelectric non-volatile memory and a preparation method to solve the problems of limited storage density, low reliability and high power consumption of existing FeFET memory devices.

The ferroelectric non-volatile memory provided by the invention includes a substrate, a source-side control gate, a storage gate and a drain-side control gate arranged in sequence above the substrate; wherein, a source electrode and a drain electrode are provided on the substrate, and are located on the source side. The substrate area between the electrode and the drain forms a channel that isolates the source and drain; a ferroelectric layer is provided between the channel and the storage gate, and the storage gate is used to apply voltage to the upper surface of the ferroelectric layer to Change the polarization state of the ferroelectric layer; the source side control gate and the drain side control gate are used to control the channel on or off; by controlling the voltage of the storage gate, source, source side control gate, drain side control gate and drain , realizing data writing, reading and erasing.

In addition, an optional technical solution is that the substrate is of a first doping type, and the source and drain are of a second doping type that is opposite to the first doping type.

In addition, an optional technical solution is that the channel includes a channel under the source side control gate, a channel under the storage gate and a channel under the drain side control gate; the substrate material includes silicon, germanium, gallium nitride, and gallium arsenide. , at least one of indium arsenide, indium phosphide, silicon carbide, indium antimonide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, and indium tin oxide; the formation method of the channel on the substrate includes :Shallow trench isolation or field oxide isolation.

In addition, an optional technical solution is that the material of the ferroelectric layer includes hafnium oxide, zirconium oxide, hafnium zirconium oxide, hafnium aluminum oxide, hafnium lanthanum oxide, lead titanate, PZT, SBT, BLT, and is made of any one of the above materials It consists of a single layer or a multi-layer combination of multiple materials, and the ferroelectric layer is formed on the substrate by: atomic layer deposition, physical vapor deposition, low-pressure chemical vapor deposition, and plasma chemical deposition.

In addition, an optional technical solution is to provide buffer media on the upper and lower surfaces of the ferroelectric layer respectively; the buffer media includes at least one layer of silicon dioxide or silicon carbide or aluminum oxide or hafnium oxide or HfAlO or HfSiO or Ta2O5 or TaSiO media layer.

In addition, an optional technical solution is that the material of the memory gate includes: doped polysilicon, tantalum, neodymium, titanium nitride, tungsten nitride, tantalum nitride, metal silicide; between the memory gate and the source side control gate, Insulating dielectrics are respectively provided between the storage gate and the drain side control gate.

In addition, an optional technical solution is to apply a positive voltage greater than the polarization flip threshold to the storage gate and drain of the memory cell to be written, and the drain-side control gate and the source-side control gate are The voltages are all 0V; except for the WL where the selected memory cell is located, the voltage is 0V, and the remaining WL applies a voltage greater than the leakage control gate threshold voltage; the channel of the selected memory cell is turned off, and the polarization state of the ferroelectric layer changes. After the voltage is removed, the ferroelectric layer has residual polarization in the downward direction, and "1" is written into the memory cell.

In addition, an optional technical solution is to set the voltage of the drain side control gate and the source side control gate to 0V when erasing data, and apply an amplitude greater than the polarization flip threshold to the storage gate of the memory cell to be erased. negative voltage; the potential on the upper surface of the ferroelectric layer is negative voltage, and the voltage on the lower surface is the substrate voltage 0V. After the voltage is removed, the ferroelectric layer retains the residual polarization in the upward direction, and the memory cell is erased to "0" .

In addition, an optional technical solution is to apply a voltage greater than the threshold voltage to the drain-side control gate and the source-side control gate, and apply a read voltage to the storage gate, and the read voltage is between the ferroelectric layer located on both sides. between the threshold voltages corresponding to the two polarization states; if the polarization direction of the ferroelectric layer is downward, the voltage of the storage gate is greater than the threshold voltage, the channel is turned on, and "1" is read; otherwise, the channel is turned off, and "1" is read. Out "0".

On the other hand, the present invention provides a method for preparing a ferroelectric non-volatile memory, which includes: forming a gate dielectric and a buffer dielectric under the ferroelectric layer on a substrate by thermal oxidation or chemical vapor deposition; Form a ferroelectric layer and a memory gate located on the ferroelectric layer, and pattern it by reactive ion etching or wet etching; deposit an insulating layer material on the gate dielectric, and dry etching or reactive ion etching to the gate The dielectric is exposed to form an insulating layer; the control gate material is deposited on the insulating layer and patterned through dry etching or reactive ion etching until the substrate is exposed, forming a source-side control gate and a drain-side control gate located on both sides of the storage gate. ; Form source-drain epitaxy on the substrate through lightly doped implantation or oblique implantation, deposit sidewall isolation materials on the source-drain epitaxy, and etch until the substrate is exposed to form the sidewalls of the source-side control gate and the drain-side control gate. Wall; heavily doped source and drain regions formed on the substrate by ion implantation or diffusion.

Using the above-mentioned ferroelectric non-volatile memory and preparation method, a source-side control gate, a storage gate and a drain-side control gate are set, and a ferroelectric layer is set under the storage gate. CG is used to realize cross-selection during programming, which can improve storage density. , eliminate write crosstalk, and use CG to cut off the leakage current, which can reduce the threshold voltage and operating voltage, improve the data retention time of the memory, increase the storage window and erasure speed, reduce the leakage current and power consumption, and improve the overall performance of the memory and reliability.

To achieve the above and related objects, one or more aspects of the invention include features that will be described in detail below. The following description and accompanying drawings detail certain exemplary aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Furthermore, the invention is intended to include all such aspects and their equivalents.

Description of drawings

By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will be clearer and easier to understand. In the attached picture:

Figure 1 is a schematic structural diagram of a ferroelectric non-volatile memory according to an embodiment of the present invention;

Figure 2 is a schematic diagram of writing of a ferroelectric non-volatile memory according to an embodiment of the present invention;

Figure 3 is a schematic diagram of crosstalk elimination of a ferroelectric non-volatile memory according to an embodiment of the present invention;

Figure 4 is a flow chart of a preparation method for a ferroelectric non-volatile memory according to an embodiment of the present invention.

The reference numerals include: substrate 1, drain electrode 2, source electrode 3, ferroelectric layer 4, drain side control gate 5, memory gate 6, source side control gate 7.

The same reference numbers throughout the drawings indicate similar or corresponding features or functions.

Detailed ways

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It will be apparent, however, that these embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more embodiments.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " "Back", "Left", "Right", "Vertical", "Horizontal", "Top", "Bottom", "Inside", "Outside", "Clockwise", "Counterclockwise", "Axis", The orientations or positional relationships indicated by "radial direction", "circumferential direction", etc. are based on the orientations or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply the referred devices or components. Must have a specific orientation, be constructed and operate in a specific orientation and are therefore not to be construed as limitations of the invention.

In order to solve the problems of limited storage density, low reliability and high power consumption of existing memory solutions, the present invention provides a ferroelectric non-volatile memory and a preparation method, which have a source-side control gate, a memory gate and a drain-side control Gate these three gates, and set up a ferroelectric layer under the memory gate. CG is used to realize cross-selection during programming, which can improve storage density and eliminate write crosstalk. In addition, CG is used to cut off leakage current, which can reduce the threshold voltage and operation voltage, improve the data retention time of the memory, increase the storage window and erasing speed, reduce leakage current and power consumption, and improve the overall performance and reliability of the memory.

In order to describe the ferroelectric non-volatile memory and the preparation method of the present invention in detail, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Figure 1 shows a schematic structure of a ferroelectric non-volatile memory according to an embodiment of the present invention.

As shown in Figure 1, the ferroelectric non-volatile memory according to the embodiment of the present invention includes a substrate 1, a source-side control gate 7, a storage gate 6 and a drain-side control gate 5 arranged in sequence above the substrate 1; wherein, A source electrode 3 and a drain electrode 2 are provided on the substrate 1. The area of the substrate 1 between the source electrode 3 and the drain electrode 2 forms a channel that isolates the source electrode 3 and the drain electrode 2; between the channel and the memory gate 6 A ferroelectric layer 4 is provided. The memory gate 6 is used to apply voltage to the upper surface of the ferroelectric layer 4 to change the polarization state of the ferroelectric layer 4; the source side control gate 7 and the drain side control gate 5 are used to control the channel. Turn on or off; by controlling the voltage of storage gate 6, source 3, source side control gate 7, drain side control gate 5 and drain 2, data writing, reading and erasing are realized.

Specifically, the memory may include six terminals: a substrate 1, a source-side control gate 7 (CGS), a memory gate 6 (MG), a drain-side control gate 5 (CGD), a source 3, and a drain 2. The memory gate is Below 6 is the ferroelectric layer 4 based on materials with ferroelectric properties such as hafnium zirconium oxide and hafnium oxide. Buffer materials such as silicon dioxide can be added between the ferroelectric layer 4 and the substrate 1 to form a buffer medium, memory gate 6 An insulating dielectric is provided between the source-side control gate 7 and the memory gate 6 and the drain-side control gate 5. The insulating dielectric can be formed of an insulating layer using an insulating material such as silicon nitride.

During the use of ferroelectric non-volatile memory, the drain side control gate 5 can be connected to the word line (WL), drain 2 to the bit line (BL), the storage gate to the same voltage as drain 2, and source 3 The common source line (Common SL) is grounded, and the substrate 1 is grounded, forming a NOR cross array structure to achieve random access, random writing, and block erasing of data.

In the specific embodiment of the present invention, the substrate 1 is located at the bottom and has the first doping type; its upper part includes source and drain regions, and the source and drain regions are doped to be opposite to the doping type of the substrate 1 The second doping type; the area between the source 3 and the drain 2 forms a channel, and the channel includes the channel under the source side control gate 7, the channel under the storage gate 6 and the channel under the drain side control gate 5; The material of the substrate 1 includes silicon, germanium, gallium nitride, gallium arsenide, indium arsenide, indium phosphide, silicon carbide, indium antimonide, IGZO (indium gallium zinc oxide), IAZO (indium aluminum zinc oxide), ITZO (Indium Tin Zinc Oxide), ITO (Indium Tin Oxide).

Wherein, the substrate can be set as a silicon substrate, located at the bottom, with P-type doping; its upper part includes source and drain regions, with N+ doping in the source and drain regions; the region between the source and drain is a channel. The gate dielectric, control gate (including source side control gate 7 and drain side control gate 5, the same below), memory gate, ferroelectric layer, and each insulating layer are all stacked on the substrate. Ion implantation is used to form a p-well with a high doping concentration in the substrate, and then each memory cell is isolated through shallow trench isolation (STI) and field oxide processes.

Among them, the gate dielectric between the lower surface of the control gate and the upper surface of the substrate 1, the two control gates (including the source side control gate 7 and the drain side control gate 5), the memory gate 6, the ferroelectric layer 4, and each insulating dielectric are all stacked Above the substrate 1, the channels can be divided into the channel under the source side control gate 7, the channel under the memory gate 6 and the channel under the drain side control gate 5 according to the vertical corresponding relationship. Available substrate 1 materials include elements Semiconductors, such as silicon and germanium; compound semiconductors, such as gallium nitride, gallium arsenide, indium arsenide, indium phosphide, silicon carbide, indium antimonide; oxide semiconductors, such as IGZO (Indium Gallium Zinc Oxide), IAZO (Indium Aluminum zinc oxide), ITZO (indium tin zinc oxide), ITO (indium tin oxide); alloy compound semiconductors; organic materials; flexible materials and combinations of the above materials. Materials are doped to form the substrate 1 through diffusion, ion implantation, etc., The material is divided into regions of each substrate 1 through isolation technologies such as shallow trench isolation (STI) and field oxide. In addition, a high doping concentration region can be further formed in the substrate 1 through diffusion or ion implantation to improve Memory performance, such as p-well (n-well) and EPM injection.

In the specific embodiment of the present invention, the ferroelectric layer 4 is a thin layer made of a material with ferroelectric properties, located above the substrate 1 and covering the middle part of the channel. The lower surface of the ferroelectric layer 4 is connected to the substrate 1, and the upper surface is connected to the memory gate 6. A buffer medium or a buffer medium can be added between the lower surface of the ferroelectric layer 4 and the substrate 1, and between the upper surface and the memory gate 6. Insulating layer to improve interface properties.

In addition, the material of the ferroelectric layer 4 has residual polarization when there is no electric field, and its polarization state can be reversed. The materials for the ferroelectric layer 4 can include metal oxides, such as hafnium oxide, doped hafnium oxide, zirconium oxide, Hafnium zirconium oxide (HZO), hafnium aluminum oxide (HAlO), hafnium lanthanum oxide; salts, such as lead titanate, PZT, SBT, BLT, etc. The method of forming the ferroelectric layer 4 on the substrate 1 includes atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), plasma chemical deposition (PECVD) and other materials. of one or more.

In addition, a buffer medium is provided on the upper and lower surfaces of the ferroelectric layer 4 respectively. The buffer medium includes at least one layer of silicon dioxide or silicon carbide or aluminum oxide or hafnium oxide or HfAlO or HfSiO or Ta2O5 or TaSiO. The buffer medium forms a dielectric layer.

As an example, the ferroelectric layer is a thin layer composed of hafnium zirconium oxide (HZO), which is located above the substrate and covers part of the middle area of the channel. The lower surface of the ferroelectric layer is connected to the substrate, and the upper surface is connected to the memory gate; there is a thin silicon dioxide layer between the lower surface of the ferroelectric layer and the substrate to improve the interface properties. In addition, the ferroelectric layer can pass through the atomic layer Deposition (ALD) formation.

In the specific embodiment of the present invention, the memory gate 6 is located directly above the ferroelectric layer 4, and its cross section coincides with the ferroelectric layer 4. The left and right sides of the memory gate 6 and the ferroelectric layer 4 are source-side control gates 7 respectively. and the drain side control gate 5. The control gate and the storage gate 6 are respectively isolated by an insulating layer. The memory gate 6 serves as a gate electrode for applying a large voltage to the upper surface of the ferroelectric layer 4. Available materials for the memory gate 6 include semiconductors, such as doped polysilicon; metals, such as tantalum and neodymium; metal nitrides and oxides. Such as titanium nitride, tungsten nitride, tantalum nitride; metal silicide (Silicide), etc.

In addition, the formation method of the memory gate 6 on the ferroelectric layer 4 includes low-pressure chemical vapor deposition (LPCVD), plasma chemical deposition (PECVD), etc. If a polysilicon gate is used, in-situ doping can be performed during deposition. After the ferroelectric layer 4 and the memory gate 6 are formed successively, they can be patterned. The patterning process includes wet etching (WE) after photolithography, reactive ion etching (RIE) after photolithography, etc. Furthermore, the materials that can be used for the insulating layer include one or more layers of silicon dioxide, silicon nitride and other insulating media, as well as common compounds and organic compound isolation materials. The insulating layer can be formed by forming a thin layer of insulating dielectric through chemical deposition methods such as LPCVD and PECVD after forming the ferroelectric layer 4 and the memory gate 6 and then etching it in a short time. The etching method can be dry etching or reactive ion etching. (RIE) etc.

As a specific example, the memory gate uses an N+ polysilicon gate, which is located directly above the ferroelectric layer. The cross section coincides with the ferroelectric layer. On both sides of the memory gate and the ferroelectric layer are control gates. There is silicon nitride insulation between the two and the two control gates. layer isolation. In the preparation process, low-pressure chemical vapor deposition (LPCVD) technology is first used to deposit a polysilicon film, and N+ in-situ doping (In-situ Doping) is performed during deposition. The memory gate pattern is then defined on the photoresist by photolithography, followed by reactive ion etching (RIE), which stops and removes the photoresist when the silicon dioxide is exposed. After that, a thin layer of silicon nitride is deposited by LPCVD and etched using RIE for a short time until the silicon dioxide is exposed to form an insulating layer. The side wall isolation can be formed by the same method after the ferroelectric layer, memory gate, control gate, and insulating layer are all formed.

In the specific embodiment of the present invention, the source-side control gate 7 and the drain-side control gate 5 are located above the substrate 1 and the gate dielectric, covering the remaining area of the channel edge, and controlling the opening and closing of the channel below. In the embodiment shown in the drawings, the control gate covers the left and right sides of the channel and is located on both sides of the memory gate 6 and the ferroelectric layer 4. There is a gate dielectric between the lower surface of the control gate and the upper surface of the substrate 1. One side of the control gate One side is a side-wall spacer, and the other side is isolated from the memory gate 6 by an insulating layer. Among them, the available materials for the gate dielectric include one or more layers of silicon dioxide; silicon nitride; high dielectric constant metal oxide materials, such as titanium dioxide, hafnium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, etc.

In addition, the gate dielectric is formed before each gate is formed, using deposition techniques such as LPCVD, PECVD, HDP-CVD, and ALD. If silicon dioxide is used as the gate dielectric, thermal oxidation can be used to form a better quality gate dielectric. Available materials for the control gate are similar to the memory gate 6, including polysilicon, metal, metal oxide or nitride, etc. The process flow for forming the control gate includes deposition, planarization, and patterning. Deposition can use chemical vapor deposition such as LPCVD, PECVD, HDP-CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), etc., planarization can use techniques such as chemical mechanical polishing (CMP), and patterning can After photolithography masking, etching techniques such as reactive ion etching (RIE) are used to complete the process.

Further, the control gate can be formed after the memory gate 6 is formed and before the spacer isolation is formed. The side wall isolation can be formed by the same method after the ferroelectric layer 4, memory gate 6, control gate, and insulating layer are all formed; available materials include one or more layers of silicon dioxide, silicon nitride and other insulating media, and common compounds , Organic compound isolation materials, for details, please refer to the insulation materials in the aforementioned content.

As a specific example, the source-side control gate and the drain-side control gate are also N+ polysilicon gates, located above the substrate and the gate dielectric, respectively covering the remaining areas on both sides of the channel. There is a thin layer of silicon dioxide between the lower surface of the two control gates and the upper surface of the substrate. The source side control gate is isolated from the source side and the drain control gate is isolated from the drain side, and the other side is insulated by silicon nitride. layer to insulate it from the memory gate. During the preparation process, a thin layer of silicon dioxide is first formed by thermal oxidation, and then a polysilicon film is deposited using LPCVD, with in-situ doping performed during the process. Thereafter, chemical mechanical polishing (CMP) technology is used for planarization, and the control gate pattern is defined by photolithography. After photolithography, RIE is used to etch until the silicon substrate is exposed, and the photoresist is removed to form two control gates. The two control gates may be formed after the storage gate is formed and before the spacer isolation is formed. The materials and formation methods of sidewall isolation and inter-gate insulating layers have been described.

In the specific embodiment of the present invention, the source region and the drain region are located on both sides of the channel of the substrate 1, the doping concentration is relatively high, and the doping type is opposite to that of the channel. It can be formed using doping processes such as diffusion and ion implantation. The source and drain regions can be doped before or after the formation of the gate stack and sidewalls. If they are doped after formation, self-aligned ion implantation can be used. Furthermore, short-time diffusion, low-concentration ion implantation or oblique ion implantation can be performed after the gate stack is formed and before the sidewalls are formed to form source-drain epitaxy to alleviate the short channel effect.

Specifically, the source region and drain region are located in the substrate, on both sides of the channel, and have N+ doping. After the gate stack is formed, low-concentration ion implantation and oblique ion implantation (Halo Implant) are first performed to form source-drain epitaxy. After the sidewall isolation is formed, source and drain doping are formed using self-aligned ion implantation.

When using the ferroelectric non-volatile memory of the embodiment of the present invention to write data, a positive voltage greater than the polarization flip threshold can be applied to the memory gate and drain of the memory cell to be written, and the drain side control gate and source The voltages of the side control gates are all 0V; except for the WL where the selected memory cell is located, the voltage is 0V, and the remaining WLs apply voltages greater than the leakage control gate threshold voltage; the channel of the selected memory cell is turned off, and the ferroelectric layer is polarized The state changes. After the voltage is removed, the ferroelectric layer has residual polarization in the downward direction, and "1" is written into the memory cell.

Specifically, as shown in Figure 2, according to the writing principle of the ferroelectric non-volatile memory according to the embodiment of the present invention, at this time, a positive voltage greater than the polarization flip threshold is applied to the MG and drain (where the BL is located) of the memory cell to be written. The voltage, CGD (where WL is located) voltage and CGS voltage are all 0V. Except for the WL voltage of the selected memory cell, which is 0V, the remaining WL needs to apply a voltage greater than the CGD threshold voltage, such as a logic high level. At this time, the channel of the selected memory cell is turned off, the voltage on the lower surface of the ferroelectric layer is close to the substrate voltage 0V, and the voltage on the upper surface is the larger positive voltage applied by MG. Therefore, there is a downward direction in the ferroelectric layer. With a stronger electric field, the polarization state changes; after the voltage is removed, the ferroelectric layer has residual polarization in the downward direction, and the unit is written as "1".

In addition, FIG. 3 shows the crosstalk cancellation principle of the ferroelectric non-volatile memory according to an embodiment of the present invention.

As shown in Figure 3, when the remaining memory cells sharing BL with the programmed memory cell are half-selected, a positive voltage greater than the polarization flip threshold is applied to the MG and drain, the CGS voltage is 0, and the CGD voltage is greater than its threshold voltage. At this time, the MG lower inversion layer is connected to the drain through the CGD lower inversion layer, but the turned-off CGS channel isolates it from the source, and the channel surface potential under MG is close to the drain voltage. The voltage on the upper surface of the ferroelectric layer is the MG positive voltage, and the voltage on the lower surface is the drain positive voltage. Since the voltage applied to the MG and the drain is the same during use, the electric field inside the ferroelectric layer is very weak. The large positive voltage applied to the MG and the drain falls on the reverse-biased P-N junction between the drain, the inversion layer and the substrate. The ferroelectric layer is shielded by the inversion layer below, and the polarization state does not change. Therefore, memory cells half-selected by BL are not affected. For the rest of the memory cells, the CGS, MG, drain, and source voltages are all 0V. Therefore, regardless of whether CGD applies a positive voltage, the voltage on the upper and lower surfaces of the ferroelectric layer is 0V, the polarization state does not change, and the memory cells are not affected, so Eliminate memory crosstalk.

When erasing data using the ferroelectric non-volatile memory according to the embodiment of the present invention, the voltages of the drain-side control gate and the source-side control gate are set to 0V, and an amplitude greater than the voltage is applied to the memory gate of the memory cell to be erased. The negative voltage of the flip threshold; at this time, the potential of the upper surface of the ferroelectric layer is a negative voltage, and the voltage of the lower surface is the substrate voltage 0V, which can withstand a stronger power plant in the upward direction; after the voltage is removed, the ferroelectric layer will remain With residual polarization in the upward direction, the memory cell is erased to "0". Since erasure is only controlled by the MG voltage, the voltage on the entire BL is erased, thereby achieving a block-by-block erasure effect.

When using the ferroelectric non-volatile memory according to the embodiment of the present invention to read data, a voltage greater than the threshold voltage is applied to the drain-side control gate and the source-side control gate, and a read voltage is applied to the storage gate. The read voltage is between the ferroelectric The layer is located between the threshold voltages corresponding to the two polarization states; since the channels under CGS and CGD are turned on, whether the source to drain is turned on is determined by the channel under the ferroelectric layer. If the polarization direction of the ferroelectric layer Downward, the voltage of the storage gate is greater than the threshold voltage, the channel is turned on, and "1" is read; otherwise, the channel is turned off, and "0" is read.

Corresponding to the above-mentioned ferroelectric non-volatile memory, the present invention also provides a method for preparing a ferroelectric non-volatile memory. Specifically, FIG. 4 shows the flow of a method for preparing a ferroelectric non-volatile memory according to an embodiment of the present invention. .

As shown in Figure 4, the method for preparing a ferroelectric non-volatile memory according to an embodiment of the present invention includes:

S100: Form a gate dielectric and a buffer dielectric under the ferroelectric layer on the substrate through thermal oxidation or chemical vapor deposition;

Before step A100, a doped substrate may first be formed, and each memory unit may be formed through shallow trench isolation or field oxidation segmentation to form a memory array; then, the gate dielectric of the two control gates may be formed through thermal oxidation or chemical vapor deposition. Buffer layer under the ferroelectric layer.

S200: Form a ferroelectric layer on the buffer medium and a memory gate on the ferroelectric layer, and pattern them by reactive ion etching or wet etching;

S300: Deposit an insulating layer material on the gate dielectric, and expose the gate dielectric through dry etching or reactive ion etching to form an insulating layer;

S400: Deposit the control gate material on the insulating layer, and pattern it through dry etching or reactive ion etching until the substrate is exposed, forming a source-side control gate and a drain-side control gate located on both sides of the storage gate;

S500: Form source-drain epitaxy on the substrate through lightly doped implantation or oblique implantation, deposit sidewall isolation material on the source-drain epitaxy, and etch until the substrate is exposed to form the source-side control gate and the drain-side control gate. side wall;

S600: Form heavily doped source and drain regions on the substrate through ion implantation or diffusion.

As a specific example, the method for preparing a ferroelectric non-volatile memory according to an embodiment of the present invention may include:

1) Substrate doping is formed through diffusion, ion implantation, etc., and the material is divided into memory cell substrates through isolation technologies such as shallow trench isolation (STI) and field oxide;

2) Use LPCVD, PECVD, HDP-CVD, ALD and other deposition technologies to form the control gate dielectric and the buffer layer under the ferroelectric layer;

3) Use atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), plasma chemical deposition (PECVD) and other technologies to deposit ferroelectric layer materials;

4) Use low-pressure chemical vapor deposition (LPCVD), plasma chemical deposition (PECVD) and other technologies to deposit memory gate materials;

5) Use photolithography to define the memory gate and ferroelectric layer patterns on the photoresist, use wet etching (WE), reactive ion etching (RIE) and other etching techniques to pattern, and then remove the photoresist;

6) Deposit the insulating layer material through chemical deposition methods such as LPCVD and PECVD, and then use dry etching, reactive ion etching (RIE) and other technologies to etch for a short time until the gate dielectric deposited in step 2 is exposed to form The insulation layer between the two control gates and the storage gate;

7) Use LPCVD, PECVD, HDP-CVD and other chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition (ALD) and other technologies to deposit control gate materials;

8) Planarize using techniques such as chemical mechanical polishing (CMP);

9) Use photolithography to define a control gate pattern on the photoresist, pattern it using etching techniques such as reactive ion etching (RIE), and then remove the photoresist to form a source-side control gate and a drain-side control gate;

10) Use CVD, ALD and other technologies to deposit side wall isolation materials, and then use dry etching, RIE and other technologies to etch until the substrate is exposed in step 1 to form side wall isolation;

11) Use diffusion, ion implantation and other doping processes to heavily dope. The doping type is opposite to the substrate doping type described in step 1 to form the source and drain regions.

Furthermore, a high doping concentration region can be further formed in the substrate through diffusion or ion implantation to improve device performance, such as p-well (n-well) and EPM implantation.

It should be noted that, for the embodiments of the ferroelectric non-volatile memory preparation method described above, reference may be made to the description in the ferroelectric non-volatile memory embodiments, which will not be described again here.

According to the above-mentioned scheme of the ferroelectric non-volatile memory and the preparation method of the present invention, CG can be used to realize cross-selection during programming. Compared with FeFET with extra transistors or transmission gates, the storage density is improved and compared with FeFET without extra transistors. The write crosstalk is eliminated and the reliability is enhanced. Using CG to cut off the leakage current, a lower threshold voltage and read voltage can be used. The impact of the read operation on the data is reduced, resulting in enhanced reliability and reduced power consumption.

The ferroelectric nonvolatile memory and the preparation method according to the present invention are described above by way of example with reference to the accompanying drawings. However, those skilled in the art should understand that various improvements can be made to the above-mentioned ferroelectric non-volatile memory and preparation method proposed by the present invention without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the contents of the appended claims.

Claims (10)

1. The ferroelectric nonvolatile memory is characterized by comprising a substrate, a source side control gate, a storage gate and a drain side control gate which are sequentially arranged above the substrate; wherein,

providing a source electrode and a drain electrode on the substrate, wherein a substrate region between the source electrode and the drain electrode forms a channel for isolating the source electrode and the drain electrode;

a ferroelectric layer is arranged between the channel and the storage gate, and the storage gate is used for applying voltage to the upper surface of the ferroelectric layer so as to change the polarization state of the ferroelectric layer;

the source side control gate and the drain side control gate are used for controlling the channel to be conducted or closed;

by controlling the voltages of the storage gate, the source electrode, the source side control gate, the drain side control gate and the drain electrode, writing, reading and erasing of data are realized.

2. The ferroelectric nonvolatile memory according to claim 1, wherein,

the substrate is of a first doping type and the source and drain are of a second doping type opposite to the first doping type.

3. The ferroelectric nonvolatile memory according to claim 1, wherein,

the channel comprises a source side control gate lower channel, a storage gate lower channel and a drain side control gate lower channel;

the material of the substrate comprises at least one of silicon, germanium, gallium nitride, gallium arsenide, indium phosphide, silicon carbide, indium antimonide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide and indium tin oxide;

the forming mode of the channel on the substrate comprises the following steps: shallow trench isolation or field oxide isolation.

4. The ferroelectric nonvolatile memory according to claim 1, wherein,

the ferroelectric layer comprises hafnium oxide, zirconium oxide, hafnium aluminum oxide, hafnium lanthanum oxide, lead titanate and PZT, SBT, BLT, and is formed by single layers of any one of the materials or multiple layers of multiple materials; and the ferroelectric layer is formed on the substrate in a manner comprising: atomic layer deposition, physical vapor deposition, low pressure chemical vapor deposition, and plasma chemical deposition.

5. The ferroelectric nonvolatile memory according to claim 1 or 4, wherein,

buffer mediums are respectively arranged on the upper surface and the lower surface of the ferroelectric layer;

the buffer medium comprises at least one dielectric layer of silicon dioxide or silicon carbide or aluminum oxide or hafnium oxide or HfAlO or HfSiO or Ta2O5 or TaSiO.

6. The ferroelectric nonvolatile memory according to claim 1, wherein,

the material of the storage gate comprises: doped polysilicon, tantalum, neodymium, titanium nitride, tungsten nitride, tantalum nitride, and metal silicide;

insulating mediums are respectively arranged between the storage gate and the source side control gate and between the storage gate and the drain side control gate.

7. The ferroelectric nonvolatile memory according to claim 1, wherein when writing of data is realized, a positive voltage larger than a polarization inversion threshold is applied to a memory gate and a drain of a memory cell to be written, and voltages of the drain side control gate and the source side control gate are each 0V;

removing the WL voltage of the selected memory cell to be 0V, and applying voltages larger than the drain control gate threshold voltage to other WLs;

the channel of the selected memory cell is turned off, the polarization state of the ferroelectric layer is changed, after the voltage is removed, the ferroelectric layer has a downward-directed remnant polarization, and the memory cell is written with a "1".

8. The ferroelectric nonvolatile memory according to claim 1, wherein when erasing data is achieved, voltages of the drain side control gate and the source side control gate are set to 0V, and a negative voltage having a magnitude larger than a polarization inversion threshold is applied to a memory gate of a memory cell to be erased;

the potential of the upper surface of the ferroelectric layer is the negative voltage, the voltage of the lower surface is the substrate voltage of 0V, after the voltage is removed, the ferroelectric layer retains the remnant polarization in the upward direction, and the memory cell is erased to be 0.

9. The ferroelectric nonvolatile memory according to claim 1, wherein when reading data is realized, a voltage larger than a threshold voltage is applied to the drain side control gate and the source side control gate, and a read voltage is applied to the memory gate, the read voltage being between threshold voltages corresponding to two polarization states of the ferroelectric layer;

if the polarization direction of the ferroelectric layer is downward, the voltage of the storage gate is larger than the threshold voltage, the channel is conducted, and '1' is read out; otherwise, the channel is turned off, and "0" is read out.

10. A method of fabricating a ferroelectric nonvolatile memory, the method comprising:

forming a gate dielectric and a buffer dielectric under the ferroelectric layer on the substrate by thermal oxidation or chemical vapor deposition;

forming a ferroelectric layer and a storage gate positioned on the ferroelectric layer on the buffer medium, and patterning by reactive ion etching or wet etching;

depositing an insulating layer material on the gate dielectric, and forming an insulating layer by dry etching or reactive ion etching until the gate dielectric is exposed;

depositing a control gate material on the insulating layer, and patterning the control gate material by dry etching or reactive ion etching until the substrate is exposed, so as to form a source side control gate and a drain side control gate which are positioned at two sides of the storage gate;

forming a source-drain epitaxy on the substrate through light doping injection or oblique injection, depositing a side wall isolation material on the source-drain epitaxy, and etching until the substrate is exposed to form side walls of the source-side control gate and the drain-side control gate;

heavily doped source and drain regions are formed on the substrate by ion implantation or diffusion.