CN117293105A - Chip packaging structure for improving wire bonding bearing capacity - Google Patents
Chip packaging structure for improving wire bonding bearing capacity Download PDFInfo
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- CN117293105A CN117293105A CN202210690423.5A CN202210690423A CN117293105A CN 117293105 A CN117293105 A CN 117293105A CN 202210690423 A CN202210690423 A CN 202210690423A CN 117293105 A CN117293105 A CN 117293105A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4502—Disposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a chip packaging structure for improving wire bonding tolerance, wherein at least one conducting wire of the chip packaging structure is a structure body with a thickness, the thickness of each conducting wire is set to be 4.5-20 microns, so that the structural strength of each conducting wire is improved to bear positive pressure generated during wire bonding operation or forming a first welding point, at least one inner wire of a chip is not damaged by the positive pressure, and each inner wire can be allowed to pass through or be arranged below the first welding point, the problem that the cost of a manufacturing end is increased due to the design of the inner wire of the chip is required to be rearranged at the manufacturing end is effectively solved, and the cost of the manufacturing end is reduced.
Description
Technical Field
The present invention relates to a chip package, and more particularly to a chip package with improved wire bonding capability.
Background
In the field of chip packaging, the chip packaging and the electronic device are electrically connected by Wire Bonding (Wire Bonding) technology, that is, a Bonding Wire is used to form a solder joint on the chip packaging structure and another solder joint on the electronic device, so that the chip packaging structure and the electronic device are electrically connected together. However, when performing wire bonding operation, the conventional chip package structure receives positive pressure generated during wire bonding operation or forming the solder joint, so that the internal circuit of the chip is damaged due to the positive pressure, and the internal circuit cannot easily pass or is not arranged below each die pad in the chip.
Therefore, a chip package structure for improving the wire bonding tolerance, which effectively solves the problem of increased cost of the manufacturing end due to the need of rearranging the internal circuit design of the chip at the manufacturing end, is an urgent need of the related industry at present.
Disclosure of Invention
The present invention provides a chip package structure for improving Wire Bonding tolerance, wherein at least one conductive trace of the chip package structure is a structure body having a thickness, and the thickness of each conductive trace is set to 4.5-20 micrometers (μm), so as to improve the structural strength of each conductive trace to bear positive pressure generated from Wire Bonding or forming a first Bonding pad, so that at least one internal trace of a chip is not damaged by the positive pressure, and each internal trace can be allowed to pass through or be arranged under the first Bonding pad, thereby effectively solving the problem of increased manufacturing cost caused by the need of re-arranging the design of the internal trace of the chip at the manufacturing end.
In order to achieve the above-mentioned objective, the present invention provides a chip package structure for improving wire bonding tolerance, the chip package structure comprises a chip, at least one first dielectric layer, at least one first bump, at least one first protective layer, at least one second dielectric layer, at least one conductive line, at least one second bump, at least one second protective layer and at least one solder mask layer; the chip is provided with a first surface and at least one internal circuit, wherein the first surface is provided with at least one Die Pad (Die Pad) and at least one protection layer, and the chip is formed by being divided on a wafer; each first dielectric layer is provided with a second surface and at least one first groove, each first dielectric layer is correspondingly covered on the first surface of the chip, and each first groove corresponds to each crystal pad of the chip; each first bump is provided with a third surface, each first bump is arranged in a corresponding first groove of each first dielectric layer, and each first bump is electrically connected and arranged on each crystal pad of the chip; each first protection layer is provided with a fourth surface, each first protection layer is arranged in the corresponding first groove of each first dielectric layer, and each first protection layer is electrically connected to the third surface of each first bump; each second dielectric layer is provided with a fifth surface and at least one second groove, each second dielectric layer is correspondingly covered on the second surface of each first dielectric layer, and each second groove covers each crystal pad of the chip; each conducting wire is arranged in the corresponding second groove of each second dielectric layer, and each conducting wire is arranged on the second surface of each first dielectric layer, the fourth surface of each first protective layer and the fifth surface of each second dielectric layer, wherein each conducting wire is electrically connected with each first protective layer; each second bump is provided with a seventh surface and a peripheral edge, and each second bump is electrically connected and arranged on the sixth surface of each conductive connection circuit; each second protection layer is provided with an eighth surface, each second protection layer is arranged on the seventh surface of each second bump, the circumferential edge of each second bump and the fifth surface of each second dielectric layer, and each second protection layer is electrically connected with each second bump; each solder mask layer is provided with at least one first opening, each solder mask layer is arranged on the eighth surface of each second protection layer, each first opening of each solder mask layer is used for exposing each second protection layer, and each conductive circuit is correspondingly formed with at least one bonding Pad (Pad) in each first opening area for external electric connection; when Wire Bonding (Wire Bonding) is performed, a first welding point is formed on each second protection layer and a second welding point is formed on an electronic element through a welding Wire, so that the chip packaging structure and the electronic element are electrically connected together; the manufacturing method of the chip packaging structure comprises the following steps: step S1: providing a wafer, wherein a plurality of chips arranged in an array are arranged on the wafer, each chip is provided with a first surface and at least one internal circuit, and at least one Die Pad (Die Pad) and at least one protection layer are arranged on the first surface; step S2: providing at least one first dielectric layer on the first surface of the chip to cover the first surface correspondingly, wherein each first dielectric layer has a second surface; step S3: forming at least one first groove on each first dielectric layer, wherein each first groove corresponds to each crystal pad of the chip; step S4: at least one first bump is arranged in each first groove of each first dielectric layer, and each first bump is electrically connected and arranged on each crystal pad of the chip, and each first bump is provided with a third surface; step S5: at least one first protection layer is arranged in each first groove of each first dielectric layer, and each first protection layer is electrically connected to the third surface of each first bump and is provided with a fourth surface; step S6: providing at least one second dielectric layer on the second surface of each first dielectric layer to correspondingly cover the second surface, wherein each second dielectric layer has a fifth surface; step S7: forming at least one second groove on each second dielectric layer, wherein each second groove covers each crystal pad of the chip; step S8: at least one conducting circuit is arranged in each second groove of each second dielectric layer, and each conducting circuit is arranged on the second surface of each first dielectric layer, the fourth surface of each first protective layer and the fifth surface of each second dielectric layer, wherein each conducting circuit is electrically connected with each first protective layer; step S9: removing the redundant part of each conductive line by using a line grinding technology, wherein each conductive line is provided with a sixth surface; step S10: at least one second bump is arranged on the sixth surface of each conductive circuit and is electrically connected with each conductive circuit, and each second bump is provided with a seventh surface and a circumferential edge; step S11: at least one second protection layer is arranged on the seventh surface of each second bump and is electrically connected with each second bump, each second protection layer is also arranged on the periphery of each second bump and the fifth surface of each second dielectric layer, and each second protection layer is provided with an eighth surface; step S12: at least one solder mask layer is arranged on the eighth surface of each second protective layer; step S13: forming at least one first opening on each solder mask layer, wherein the first opening of each solder mask layer is used for exposing each second protection layer, and each conductive circuit correspondingly forms at least one bonding Pad (Pad) in each first opening area for external electrical connection; step S14: dividing the plurality of chips on the wafer into independent chip packaging structures; step S15: wire bonding is carried out on each independent chip packaging structure, and a first welding point and a second welding point are formed on each second protection layer through a welding wire so that the chip packaging structure and the electronic element are electrically connected together; wherein each of the conductive traces is a structure having a thickness of 4.5-20 μm, so as to enhance the structural strength of each of the conductive traces to withstand the positive pressure generated during the wire bonding operation or the formation of the first bonding pads, so that each of the internal traces of the chip is not damaged by the positive pressure, and each of the internal traces is allowed to pass through or be arranged under the first bonding pads, thereby facilitating the reduction of the cost of the manufacturing end.
In another preferred embodiment of the present invention, the thickness of each of the conductive traces is further set to 4.5-5 micrometers (μm).
In another preferred embodiment of the present invention, each of the solder masks further has a ninth surface; the chip packaging structure further comprises at least one outer protective layer, each outer protective layer is provided with a second opening, and each second opening is communicated with each first opening of each solder mask layer; each outer protective layer is correspondingly covered on the ninth surface of each solder mask layer, and each second opening of each outer protective layer is exposed by each second protective layer.
In another preferred embodiment of the present invention, a total thickness of the stacked first dielectric layers, the first bumps, the first protective layers, the second dielectric layers, the conductive traces, the second bumps, the second protective layers, the solder mask layers and the outer protective layers is 25 micrometers (μm).
In another preferred embodiment of the present invention, in step S12, at least one outer passivation layer is further disposed on a ninth surface of each solder mask layer and correspondingly covers the ninth surface of each solder mask layer.
In another preferred embodiment of the present invention, in step S13, at least one second opening is further formed along with each of the outer passivation layers while forming each of the first openings on each of the solder masks, wherein each of the first openings is in communication with each of the second openings.
Drawings
FIG. 1 is a schematic side sectional plan view of an embodiment of the present invention.
Fig. 2 is a schematic side view of a chip of the first embodiment divided from a wafer.
Fig. 3 is a schematic side view of a chip package structure of the present invention.
Fig. 4 is a schematic side cross-sectional plan view of a chip of the present invention.
Fig. 5 is a schematic diagram of a first dielectric layer on the chip in fig. 4.
Fig. 6 is a schematic diagram of forming a first recess on the first dielectric layer in fig. 5.
Fig. 7 is a schematic view of a first bump disposed in the first recess in fig. 6.
Fig. 8 is a schematic view of the first protection layer disposed in the first recess in fig. 7.
Fig. 9 is a schematic diagram of a second dielectric layer disposed on a second surface of the first dielectric layer in fig. 8.
Fig. 10 is a schematic diagram of forming a second recess on the second dielectric layer in fig. 9.
Fig. 11 is a schematic view of a conductive trace disposed in the second recess in fig. 10.
FIG. 12 is a schematic diagram of the conductive trace of FIG. 11 with the excess portion removed by the technique of trace polishing.
Fig. 13 is a schematic view illustrating a second bump disposed on a sixth surface of the conductive trace in fig. 12.
Fig. 14 is a schematic view of a second passivation layer disposed on the second bump in fig. 13.
Fig. 15 is a schematic view of a solder mask layer disposed on an eighth surface of the second passivation layer in fig. 14.
FIG. 16 is a schematic view of a first opening formed in the solder mask layer of FIG. 15.
FIG. 17 is a schematic view of the outer protective layer on the solder mask layer of FIG. 16.
Fig. 18 is a top plan view of the internal circuitry of the present invention.
Fig. 19 is a schematic top plan view of a chip package of the present invention.
Fig. 20 is a schematic cross-sectional side view of a first dielectric layer, a first bump, a first protective layer, a second dielectric layer, a conductive trace, a second bump, a second protective layer, a solder mask layer, and an outer protective layer stacked to form a total thickness of 25 micrometers (μm).
Fig. 21 is a schematic cross-sectional plan view of a conductive trace of the present invention with a thickness set to 4.5 to 20 micrometers (μm).
Reference numerals illustrate: 1-a chip packaging structure; 10-chip; 10 a-a first surface; 11-die pad; 12-a protective layer; 13-internal wiring; 20-a first dielectric layer; 20 a-a second surface; 21-a first groove; 30-first bumps; 30 a-a third surface; 40-a first protective layer; 40 a-fourth surface; 50-a second dielectric layer; 50 a-fifth surface; 51-a second groove; 60-connecting a circuit; 60 a-sixth surface; 61-bonding pads; 70-a second bump; 70 a-seventh surface; 70 b-a circumferential rim; 80-a second protective layer; 80 a-eighth surface; 81-a first welding spot; 90-welding-proof layer; 90 a-ninth surfaces; 91-a first opening; 100-an outer sheath; 101-a second opening; 2-wafer; 3-welding wires; 4-electronic components; 4 a-second solder joint.
Detailed Description
The structure and features of the present invention will be described in detail below with reference to the accompanying drawings, wherein the drawings are for illustrating the structural relationships and related functions of the present invention, and thus the dimensions of the elements in the drawings are not drawn to actual scale and are not intended to limit the present invention.
Referring to fig. 1 and 3, the present invention provides a chip package structure 1 with improved wire bonding tolerance, wherein the chip package structure 1 includes a chip 10, at least one first dielectric layer 20, at least one first bump 30, at least one first protective layer 40, at least one second dielectric layer 50, at least one conductive trace 60, at least one second bump 70, at least one second protective layer 80 and at least one solder mask layer 90.
The chip 10 has a first surface 10a and at least one internal circuit 13, wherein the first surface 10a is provided with at least one Die Pad (Die Pad) 11 and at least one passivation layer 12 as shown in fig. 3; wherein the die 10 are singulated from a wafer 2 as shown in fig. 2.
Each of the internal circuits 13 includes a 13a Array region (Array), a 13b circuit region (circuit Array), or a circuit Cell (Cell) (not shown), but is not limited to those shown in fig. 18 and 19.
Each of the first dielectric layers 20 has a second surface 20a and at least one first recess 21, each of the first dielectric layers 20 is correspondingly covered on the first surface 10a of the chip 10, and each of the first recesses 21 corresponds to each of the die pads 11 of the chip 10 as shown in fig. 3.
Each of the first bumps 30 has a third surface 30a, each of the first bumps 30 is disposed in each of the first grooves 21 of each of the first dielectric layers 20, and each of the first bumps 30 is electrically connected to each of the die pads 11 of the chip 10 as shown in fig. 3.
Each of the first protection layers 40 has a fourth surface 40a, each of the first protection layers 40 is disposed in each of the first grooves 21 of each of the first dielectric layers 20, and each of the first protection layers 40 is electrically connected to the third surface 30a of each of the first bumps 30, as shown in fig. 3.
Each second dielectric layer 50 has a fifth surface 50a and at least one second recess 51, each second dielectric layer 50 correspondingly covers the second surface 20a of each first dielectric layer 20, and each second recess 51 covers each die pad 11 of the chip 10 as shown in fig. 3.
Each of the conductive traces 60 has a sixth surface 60a, each of the conductive traces 60 is disposed in each of the second recesses 51 of each of the second dielectric layers 50, and each of the conductive traces 60 is disposed on the second surface 20a of each of the first dielectric layers 20, the fourth surface 40a of each of the first protective layers 40, and the fifth surface 50a of each of the second dielectric layers 50, wherein each of the conductive traces 60 is electrically connected to each of the first protective layers 40 as shown in fig. 3.
Each of the second bumps 70 has a seventh surface 70a and a peripheral edge 70b, and each of the second bumps 70 is electrically connected to the sixth surface 60a of each of the conductive traces 60 as shown in fig. 3.
Each of the second passivation layers 80 has an eighth surface 80a, each of the second passivation layers 80 is disposed on the seventh surface 70a of each of the second bumps 70, the peripheral edge 70b of each of the second bumps 70, and the fifth surface 50a of each of the second dielectric layers 50, and each of the second passivation layers 80 is electrically connected to each of the second bumps 70 as shown in fig. 3.
Each solder mask layer 90 has at least one first opening 91, each solder mask layer 90 is disposed on the eighth surface 80a of each second passivation layer 80, and each first opening 91 of each solder mask layer 90 is exposed to the outside of each second passivation layer 80 as shown in fig. 3, wherein each conductive trace 60 correspondingly forms at least one Pad (Pad) 61 in the area of each first opening 91 for external electrical connection.
Wherein each of the pads 61 is protected by each of the second bumps 70 and each of the second protection layers 80.
When Wire Bonding (Wire Bonding) is performed (as shown in fig. 1), a first Bonding pad 81 is formed on each of the second passivation layers 80 and a second Bonding pad 4a is formed on an electronic component 4 by a Bonding Wire 3, so that the chip package structure 1 and the electronic component 4 are electrically connected together as shown in fig. 1.
Referring to fig. 1, 2, and 4 to 17, the method for manufacturing the chip package structure 1 of the present invention includes the following steps:
step S1: a wafer 2 is provided, and a plurality of chips 10 arranged in an array are disposed on the wafer 2 as shown in fig. 2, each of the chips 10 has a first surface 10a and at least one internal circuit 13, and at least one Die Pad (Die Pad) 11 and at least one passivation layer 12 are disposed on the first surface 10a as shown in fig. 4.
Step S2: at least one first dielectric layer 20 is disposed on the first surface 10a of the chip 10 to cover the first surface 10a correspondingly, and each first dielectric layer 20 has a second surface 20a as shown in fig. 5.
Step S3: at least one first recess 21 is formed on each of the first dielectric layers 20, and each of the first recesses 21 corresponds to the position of each die pad 11 of the chip 10 as shown in fig. 6.
Step S4: at least one first bump 30 is disposed in each first recess 21 of each first dielectric layer 20, and each first bump 30 is electrically connected to each die pad 11 of the chip 10, and each first bump 30 has a third surface 30a as shown in fig. 7.
Step S5: at least one first protection layer 40 is disposed in each first recess 21 of each first dielectric layer 20, and each first protection layer 40 is electrically connected to the third surface 30a of each first bump 30, and each first protection layer 40 has a fourth surface 40a as shown in fig. 8.
Step S6: at least one second dielectric layer 50 is disposed on the second surface 20a of each first dielectric layer 20 to cover the second surface 20a correspondingly, and each second dielectric layer 50 has a fifth surface 50a as shown in fig. 9.
Step S7: at least one second recess 51 is formed on each second dielectric layer 50, and each second recess 51 covers each die pad 11 of the chip 10 as shown in fig. 10.
Step S8: at least one conductive trace 60 is disposed in each second recess 51 of each second dielectric layer 50, and each conductive trace 60 is disposed on the second surface 20a of each first dielectric layer 20, the fourth surface 40a of each first protective layer 40, and the fifth surface 50a of each second dielectric layer 50, wherein each conductive trace 60 is electrically connected to each first protective layer 40 as shown in fig. 11.
Step S9: the excess portion of each of the conductive traces 60 is removed by a trace polishing technique, and each of the conductive traces 60 has a sixth surface 60a as shown in fig. 12.
Step S10: at least one second bump 70 is disposed on the sixth surface 60a of each conductive trace 60 and electrically connected to each conductive trace 60, and each second bump 70 has a seventh surface 70a and a peripheral edge 70b as shown in fig. 13.
Step S11: at least one second passivation layer 80 is disposed on the seventh surface 70a of each second bump 70 and electrically connected to each second bump 70, and each second passivation layer 80 is also disposed on the peripheral edge 70b of each second bump 70 and the fifth surface 50a of each second dielectric layer 50, and each second passivation layer 80 has an eighth surface 80a as shown in fig. 14.
Step S12: at least one solder mask layer 90 is disposed on the eighth surface 80a of each of the second passivation layers 80 as shown in fig. 15.
Step S13: at least one first opening 91 is formed on each solder mask layer 90, wherein the first opening 91 of each solder mask layer 90 is exposed to the outside by each second passivation layer 80 as shown in fig. 16, and at least one Pad (Pad) 61 is correspondingly formed on each conductive trace 60 in the area of each first opening 91 for external electrical connection as shown in fig. 16.
Step S14: the plurality of chips 10 on the wafer 2 are subjected to a dicing operation to separate the chips from the wafer 2 into individual chip packages 1 as shown in fig. 2.
Step S15: wire Bonding (Wire Bonding) is performed on each of the individual chip packages 1, and a first Bonding pad 81 and a second Bonding pad 4a are formed on each of the second passivation layers 80 by a Bonding Wire 3, so that the chip packages 1 and the electronic components 4 are electrically connected together as shown in fig. 1.
Wherein, each of the conductive lines 60 is a structure having a thickness, and the thickness of each of the conductive lines 60 is set to 4.5-20 micrometers (μm), so as to enhance the structural strength of each of the conductive lines 60 to withstand the positive pressure N generated from the wire bonding operation or the formation of the first bonding pads 81, as shown in fig. 1, so that each of the internal lines 13 of the chip 10 is not damaged by the positive pressure N (as shown in fig. 1), and each of the internal lines 13 can be allowed to pass through or be arranged under the first bonding pads 81, as shown in fig. 19.
Wherein the thickness of each of the conductive lines 60 is further set to 4.5-5 micrometers (μm) without limitation.
Referring to fig. 3, each of the solder masks 90 further has a ninth surface 90a, but is not limited thereto; wherein the chip package structure 1 further comprises at least one outer passivation layer 100, each outer passivation layer 100 has a second opening 101, each second opening 101 is in communication with each first opening 91 of each solder mask layer 90; each of the outer passivation layers 100 is correspondingly disposed on the ninth surface 90a of each solder mask layer 90, and each of the second openings 101 of each of the outer passivation layers 100 is exposed by each of the second passivation layers 80.
The total thickness of the first dielectric layers 20, the first bumps 30, the first protective layers 40, the second dielectric layers 50, the conductive traces 60, the second bumps 70, the second protective layers 80, the solder masks 90, and the outer protective layers 100 is 25 micrometers (μm), but is not limited to that shown in fig. 20.
Referring to fig. 17, in step S12, at least one outer passivation layer 100 is further disposed on a ninth surface 90a of each solder mask layer 90 to cover the ninth surface 90a of each solder mask layer 90.
Referring to fig. 3, in step S13, at least one second opening 101 is further formed along with each outer passivation layer 100 at the same time when each first opening 91 is formed on each solder mask layer 90, wherein each first opening 91 is in communication with each second opening 101.
Compared with the existing chip packaging structure, the chip packaging structure 1 has the following advantages:
each of the conductive traces 60 of the chip package structure 1 of the present invention is a structure having a thickness, and the thickness of each of the conductive traces 60 is set to 4.5-20 micrometers (μm) as shown in fig. 21, so as to enhance the structural strength of each of the conductive traces 60 to withstand the positive pressure N (shown in fig. 1) generated from the wire bonding operation or the formation of the first bonding pad 81, so that each of the internal traces 13 of the chip 10 is not damaged by the positive pressure N (shown in fig. 1), and each of the internal traces 13 can be allowed to pass through or be arranged under the first bonding pad 81 as shown in fig. 19, thereby effectively solving the problem of increased manufacturing cost caused by the need of rearranging the design of the internal traces of the chip at the manufacturing end, and being beneficial to reducing the manufacturing cost.
The foregoing is merely a preferred embodiment of the present invention, which is intended to be illustrative and not limiting; it will be appreciated by those skilled in the art that many changes, modifications and even equivalents may be made thereto without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (6)
1. A chip packaging structure for improving wire bonding tolerance is characterized by comprising:
the chip is provided with a first surface and at least one internal circuit, wherein the first surface is provided with at least one crystal pad and at least one protection layer; wherein the chip is formed by dividing a wafer;
each first dielectric layer is provided with a second surface and at least one first groove, each first dielectric layer is correspondingly covered on the first surface of the chip, and each first groove corresponds to each crystal pad of the chip;
at least one first bump, each first bump having a third surface, each first bump being disposed in each first recess of each first dielectric layer, and each first bump being electrically connected to each die pad of the chip;
at least one first protection layer, each first protection layer has a fourth surface, each first protection layer is arranged in each first groove of each first dielectric layer, and each first protection layer is electrically connected and arranged on the third surface of each first bump;
at least one second dielectric layer, each second dielectric layer has a fifth surface and at least one second groove, each second dielectric layer is correspondingly covered on the second surface of each first dielectric layer, and each second groove covers each crystal pad of the chip;
at least one conductive line, each conductive line having a sixth surface, each conductive line being disposed in each second recess of each second dielectric layer, each conductive line being disposed on the second surface of each first dielectric layer, the fourth surface of each first protective layer, and the fifth surface of each second dielectric layer, wherein each conductive line is electrically connected to each first protective layer;
at least one second bump, each second bump having a seventh surface and a peripheral edge, each second bump being electrically connected to the sixth surface of each conductive trace;
at least one second protection layer, each second protection layer having an eighth surface, each second protection layer being disposed on the seventh surface of each second bump, the peripheral edge of each second bump, and the fifth surface of each second dielectric layer, and each second protection layer being electrically connected to each second bump; and
Each solder mask layer is provided with at least one first opening, each solder mask layer is arranged on the eighth surface of each second protection layer, each first opening of each solder mask layer is used for exposing each second protection layer, and each conductive circuit correspondingly forms at least one welding pad in each first opening area for external electric connection;
when wire bonding operation is performed, a first welding point is formed on each second protection layer and a second welding point is formed on an electronic element through a welding wire, so that the chip packaging structure and the electronic element are electrically connected together;
the manufacturing method of the chip packaging structure comprises the following steps:
step S1: providing a wafer, wherein a plurality of chips arranged in an array are arranged on the wafer, each chip is provided with a first surface and at least one internal circuit, and at least one wafer pad and at least one protection layer are arranged on the first surface;
step S2: providing at least one first dielectric layer on the first surface of the chip to cover the first surface correspondingly, wherein each first dielectric layer has a second surface;
step S3: forming at least one first groove on each first dielectric layer, wherein each first groove corresponds to each crystal pad of the chip;
step S4: at least one first bump is arranged in each first groove of each first dielectric layer, and each first bump is electrically connected and arranged on each crystal pad of the chip, and each first bump is provided with a third surface;
step S5: at least one first protection layer is arranged in each first groove of each first dielectric layer, and each first protection layer is electrically connected to the third surface of each first bump and is provided with a fourth surface;
step S6: providing at least one second dielectric layer on the second surface of each first dielectric layer to correspondingly cover the second surface, wherein each second dielectric layer has a fifth surface;
step S7: forming at least one second groove on each second dielectric layer, wherein each second groove covers each crystal pad of the chip;
step S8: at least one conducting circuit is arranged in each second groove of each second dielectric layer, and each conducting circuit is arranged on the second surface of each first dielectric layer, the fourth surface of each first protective layer and the fifth surface of each second dielectric layer, wherein each conducting circuit is electrically connected with each first protective layer;
step S9: removing the redundant part of each conductive line by using a line grinding technology, wherein each conductive line is provided with a sixth surface;
step S10: at least one second bump is arranged on the sixth surface of each conductive circuit and is electrically connected with each conductive circuit, and each second bump is provided with a seventh surface and a circumferential edge;
step S11: at least one second protection layer is arranged on the seventh surface of each second bump and is electrically connected with each second bump, each second protection layer is also arranged on the periphery of each second bump and the fifth surface of each second dielectric layer, and each second protection layer is provided with an eighth surface;
step S12: at least one solder mask layer is arranged on the eighth surface of each second protective layer;
step S13: forming at least one first opening on each solder mask layer, wherein the first opening of each solder mask layer is used for exposing each second protection layer, and each conductive circuit correspondingly forms at least one welding pad in each first opening area for external electrical connection;
step S14: dividing the plurality of chips on the wafer into independent chip packaging structures; and
Step S15: wire bonding is carried out on each independent chip packaging structure, and a first welding point and a second welding point are formed on each second protection layer through a welding wire so that the chip packaging structure and the electronic element are electrically connected together;
wherein each of the conductive traces is a structure having a thickness of 4.5-20 μm, so as to enhance the structural strength of each of the conductive traces to withstand the positive pressure generated from the wire bonding operation or the formation of the first bonding pads, so that each of the internal traces of the chip is not damaged by the positive pressure and is allowed to pass through or be arranged under the first bonding pads.
2. The chip package according to claim 1, wherein a thickness of each of the conductive traces is set to 4.5-5 μm.
3. The chip package structure of claim 1, wherein each solder mask layer further has a ninth surface; the chip packaging structure further comprises at least one outer protective layer, each outer protective layer is provided with a second opening, and each second opening is communicated with each first opening of each solder mask layer; each outer protective layer is correspondingly covered on the ninth surface of each solder mask layer, and each second opening of each outer protective layer is exposed by each second protective layer.
4. The chip package structure of claim 3, wherein a total thickness of the stacked first dielectric layers, the first bumps, the first protective layers, the second dielectric layers, the conductive traces, the second bumps, the second protective layers, the solder masks, and the outer protective layers is 25 μm.
5. The chip package structure of claim 1, wherein in step S12, at least one outer passivation layer is further disposed on a ninth surface of each solder mask layer to cover the ninth surface of each solder mask layer.
6. The chip package structure of claim 5, wherein in step S13, at least one second opening is further formed along with each of the outer passivation layers simultaneously with forming each of the first openings on each of the solder masks, wherein each of the first openings is in communication with each of the second openings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210690423.5A CN117293105A (en) | 2022-06-17 | 2022-06-17 | Chip packaging structure for improving wire bonding bearing capacity |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210690423.5A CN117293105A (en) | 2022-06-17 | 2022-06-17 | Chip packaging structure for improving wire bonding bearing capacity |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117293105A true CN117293105A (en) | 2023-12-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210690423.5A Pending CN117293105A (en) | 2022-06-17 | 2022-06-17 | Chip packaging structure for improving wire bonding bearing capacity |
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| Country | Link |
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| CN (1) | CN117293105A (en) |
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- 2022-06-17 CN CN202210690423.5A patent/CN117293105A/en active Pending
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