CN117290549A - Data processing method and coding circuit - Google Patents

Abstract

The present disclosure provides a data processing method and encoding circuit, which can be applied to the technical fields of time measurement, computer technology and other technical fields. The method includes: grouping multiple data in the original data sequence to obtain multiple target subsequences; inputting each target subsequence into a lookup table array set corresponding to the target subsequence to obtain multiple target subsequences Each corresponding target value, where the target value represents the sum of the position information of data with adjacent positions and different data values in the target subsequence; based on the target values corresponding to the multiple target subsequences, determine the target value of the original data sequence.

Description

Data processing method and encoding circuit

Technical field

The present disclosure relates to the technical fields of time measurement, computer technology and other technical fields, and in particular, to a data processing method and encoding circuit.

Background technique

Time-to-Digital Converter (TDC) can convert time interval information into high-resolution digital signals. Tap delay chain interpolation time-to-digital converter is the current mainstream time-to-digital converter type, which has significant advantages in measurement accuracy and other aspects. In the tap delay chain interpolation time-to-digital converter, the signal to be measured passes through the tap delay chain, and then each tap of the tap delay chain is latched with the system clock cycle based on the D flip-flop sequence, and the tap delay chain data sequence can be obtained. The size of the time interval information of the signal to be measured can be determined by the value of the edge position information of the tap delay chain data sequence.

In the process of realizing the concept of the present disclosure, the inventor found that there are at least the following problems in the related art: in the scheme of determining the edge position information of the tap delay chain data sequence, there are "bubbles" that make it difficult to determine the true edge position. Problems: There are high condition restrictions on the tap delay chain data sequence length, pulse width, etc.; and more hardware resources are used, resulting in long development cycles, increased power consumption and cost.

Contents of the invention

In view of the above problems, the present disclosure provides data processing methods, devices, equipment, media program products, and encoding circuits.

According to one aspect of the present disclosure, a data processing method is provided, which includes: grouping multiple data in the original data sequence to obtain multiple target subsequences; inputting each of the above target subsequences into the corresponding target subsequence. In the lookup table array set corresponding to the sequence, target values corresponding to multiple above-mentioned target sub-sequences are obtained, wherein the above-mentioned target value represents the sum of position information of data with adjacent positions and different data values in the above-mentioned target sub-sequence; based on multiple The target values corresponding to each of the above target subsequences are determined to determine the target value of the above original data sequence.

According to an embodiment of the present disclosure, the above-mentioned grouping of multiple data in the original data sequence to obtain multiple target subsequences includes: based on the multiple data in the above-mentioned original data sequence, determining the number of groups of the above-mentioned original data sequence; based on the multiple data in the above-mentioned original data sequence; The above-mentioned number of groups and the respective position identifiers of the multiple data in the above-mentioned original data sequence are used to group the above-mentioned multiple data to obtain multiple target sub-sequences.

According to an embodiment of the present disclosure, determining the number of groups of the above-mentioned original data sequence based on the plurality of data in the above-mentioned original data sequence includes: determining at least one target data group from the plurality of data in the above-mentioned original data sequence, wherein, The above-mentioned target data group includes a plurality of target data with continuous positions and the same data value; based on the above-mentioned target data group, determine the target adjacent edge change distance, wherein the above-mentioned target adjacent edge change distance is in at least one of the above-mentioned target data groups. The data amount of the target data group including the minimum amount of data; from the multiple data of the above-mentioned original data sequence, determine the existence of multiple area information of edge changes; based on the above-mentioned multiple area information, determine multiple target areas; based on the above-mentioned multiple area information The target area length is determined by the respective area lengths of the target areas, where the above-mentioned target area length represents the maximum area length among the respective area lengths of the above-mentioned multiple target areas; based on the above-mentioned target adjacent edge change distance and the above-mentioned target area length, Determine the number of packets of the original data sequence, wherein the number of packets is less than or equal to the distance between adjacent adjacent edges of the target and the number of packets is greater than or equal to the length of the target region.

According to an embodiment of the present disclosure, the above-mentioned lookup table array set includes multiple lookup table arrays, and the above-mentioned lookup table array includes multiple lookup tables; each of the above-mentioned target subsequences is input into the lookup corresponding to the above-mentioned target subsequence. In the table array set, obtaining target values corresponding to multiple above-mentioned target sub-sequences includes: for each above-mentioned target sub-sequence, based on the number of input terminals of the look-up tables in the above-mentioned look-up table array, determine multiple targets from the above-mentioned target sub-sequences. Subsequence fragmentation; input the above multiple subsequence fragments into the corresponding lookup table array respectively to obtain the corresponding target values of the above multiple subsequence fragments; based on the corresponding target values of the above multiple subsequence fragments, obtain The target value of the above target subsequence.

According to an embodiment of the present disclosure, when the number of data bits included in the sub-sequence fragment is less than the number of input terminals of the lookup table, the target input data of the input terminal where there is no input data is set as predetermined data.

According to an embodiment of the present disclosure, based on multiple sub-sequence fragments of the above-mentioned target sub-sequence, the maximum target value of each of the multiple above-mentioned sub-sequence fragments is determined; based on the maximum target value of each of the multiple above-mentioned sub-sequence fragments, the maximum target value of each sub-sequence fragment is determined. The number of lookup tables included in the lookup table array corresponding to the above subsequence fragments.

According to an embodiment of the present disclosure, determining the target value of the original data sequence based on the target values corresponding to the plurality of target subsequences includes: inputting the target values corresponding to the plurality of target subsequences into an adder, Obtain the target value of the above original data sequence.

According to an embodiment of the present disclosure, the above-mentioned original data sequence includes a tap delay chain data sequence.

Another aspect of the present disclosure provides an encoding circuit, including: a plurality of dedicated logic circuits for converting a target subsequence corresponding to each of the above dedicated logic circuits into a target value, wherein the above target subsequence is based on The original data sequence is obtained by grouping; the first adder is respectively connected to the plurality of dedicated logic circuits, and is used to add a plurality of the above target values to obtain the target value of the above original data sequence.

According to an embodiment of the present disclosure, the above-mentioned dedicated logic circuit includes: a look-up table array set for converting sub-sequence slices corresponding to each look-up table array in the above-mentioned look-up table array set into sub-target values, wherein the above-mentioned The sub-sequence fragmentation is obtained based on the above-mentioned target sub-sequence grouping, the above-mentioned sub-target value is the target value of the above-mentioned sub-sequence fragmentation, the above-mentioned look-up table array set includes multiple look-up table arrays; the second adder, and the above-mentioned multiple look-up tables The arrays are connected respectively and used to add the above sub-target values to obtain the target value of the above-mentioned target sub-sequence.

Another aspect of the present disclosure provides a data processing device, including: a target subsequence determination module, used to group multiple data in the original data sequence to obtain multiple target subsequences; a first target value determination module, Used to input each of the above-mentioned target subsequences into a set of lookup table arrays corresponding to the above-mentioned target subsequences, and obtain target values corresponding to multiple above-mentioned target subsequences, wherein the above-mentioned target values represent positions in the above-mentioned target subsequences. The sum of the position information of adjacent data with different data values; the second target value determination module is used to determine the target value of the above-mentioned original data sequence based on the corresponding target values of multiple above-mentioned target sub-sequences.

According to the data processing method provided by the present disclosure, by grouping multiple data in the original data sequence, multiple target subsequences can be obtained, and the multiple target subsequences are respectively input into the lookup table array set corresponding to the target subsequence. , the target value corresponding to each target subsequence can be obtained. Based on the target values of multiple target subsequences, the target value of the tap delay chain data can be obtained. Since multiple data in the original data sequence are grouped to obtain multiple target subsequences, the subsequences contain at most one bubble error, because some subsequences do not contain bubble errors. Therefore, the difficulty is at least partially solved. The problem of determining the true edge change position achieves the technical effect of determining the accuracy of the edge change position. Since each target subsequence is input into the lookup table array set corresponding to the target subsequence, multiple target subsequences are processed in parallel, and the target value corresponding to each target subsequence is quickly obtained, and based on The target value of multiple target subsequences is determined to determine the target value of the original data sequence, which at least partially solves the problems of relatively high condition restrictions and the use of more hardware resources in related technologies, achieving the goal of saving hardware resources, high universality, and The technical effects include fewer conditional limits, short encoding time for the original data sequence, and high accuracy of the target value of the original data sequence.

Description of drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

Figure 1 schematically shows a flow chart of a data processing method according to an embodiment of the present disclosure;

Figure 2 schematically shows a schematic diagram of acquiring an original data sequence according to an embodiment of the present disclosure;

Figure 3 schematically illustrates a flow chart for determining a target subsequence target value according to an embodiment of the present disclosure;

Figure 4 schematically shows a schematic diagram of a lookup table array according to an embodiment of the present disclosure;

Figure 5 schematically shows a schematic diagram of a data processing method according to another embodiment of the present disclosure;

Figure 6 schematically shows a schematic diagram of an encoding circuit according to an embodiment of the present disclosure;

Figure 7 schematically illustrates a schematic diagram of a dedicated logic circuit according to an embodiment of the present disclosure;

Figure 8 schematically illustrates a timing diagram according to an embodiment of the present disclosure; and

Figure 9 schematically shows a structural block diagram of a data processing device according to an embodiment of the present disclosure.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for convenience of explanation, numerous specific details are set forth to provide a comprehensive understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. Furthermore, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The terms "comprising," "comprising," and the like, as used herein, indicate the presence of stated features, steps, operations, and/or components but do not exclude the presence or addition of one or more other features, steps, operations, or components.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art, unless otherwise defined. It should be noted that the terms used here should be interpreted to have meanings consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

Where an expression similar to "at least one of A, B, C, etc." is used, it should generally be interpreted in accordance with the meaning that a person skilled in the art generally understands the expression to mean (e.g., "having A, B and C "A system with at least one of" shall include, but is not limited to, systems with A alone, B alone, C alone, A and B, A and C, B and C, and/or systems with A, B, C, etc. ).

In the technical solution of this disclosure, the collection, storage, use, processing, transmission, provision, disclosure and application of the data involved (including but not limited to user personal information) comply with the provisions of relevant laws and regulations, and adopt Necessary confidentiality measures must be taken without violating public order and good customs.

During the research process, it was discovered that the time-to-digital converter can convert time interval information into high-resolution digital signals and is widely used in positron emission tomography (PET), lidar (light detection and ranging, LiDAR (LiDAR for short), autonomous vehicles, time-of-flight imaging, cutting-edge particle physics experiments and space experiments, and has broad application prospects in aerospace, deep space exploration, geological mapping, medical imaging, radar scanning and other fields.

The tap delay chain interpolation time-to-digital converter is the current mainstream type of time-to-digital converter. It uses a method of combining coarse time and fine time and has significant advantages in measurement accuracy, measurement dead time, and measurement dynamic range. The accuracy of ordinary tap delay chain interpolation time-to-digital converters is limited by the delay size of the interpolation unit. In order to further improve the accuracy and break through the delay time limit of a single delay unit, some improved delay chain interpolation time-to-digital converters are "Wave Union A" technology is applied, that is, a signal to be measured generates or releases one or more periodic narrow pulse sequences in the trigger circuit, and after multiple measurements of multiple edges of this narrow pulse sequence, the obtained The average of multiple measurement results is calculated to obtain a measurement accuracy higher than that of the delay unit.

In an ordinary delay chain interpolation time-to-digital converter, the delay chain has only one edge, and the tap delay chain data sequence latched by the D flip-flop array has a form similar to...11111111100000..., which is a typical thermometer code . It can directly accumulate the number of "1"s in the thermometer code and efficiently convert the thermometer code into binary code. It can also eliminate "bubble" errors in the form of...11111100100000... caused by the out-of-synchronization of the D flip-flop array clock.

However, when there are multiple edges in the carry chain, the tap delay chain data sequence has a form similar to...000001111110000000111111110000.... In actual circumstances, each edge change also contains "bubble" errors, making the tap delay chain data The sequence becomes similar to...0000010111110100000000000000001011111111110011000000..., where the "bubble" error can represent multiple 0s mixed with 1s, and multiple 1s mixed with 0s. The "bubble" errors will make the edge information blurry and difficult to extract. And due to the use of "Wave Union A", the edge change position cannot be obtained by adding "1".

In addition, in the related art, a method of slicing XOR to find edge transitions has also been proposed to solve this problem. Based on the logic elements in the programmable logic device (Field Programmable Gate Array, FPGA for short), the data in the tap delay chain data sequence is Find edge changing positions one by one in the clip.

Although this method solves the basic edge position encoding problem, the sliced XOR structure has strict upper and lower limits on pulse width, requires a large amount of preliminary testing, and cannot be adapted to many types of FPGA devices. Its logic is complex, consumes a lot of logic resources, reduces system integration, and increases system power consumption and cost.

Based on the above, it can be known that in the scheme of determining the edge position information of the tap delay chain data sequence in the related technology, there is a problem that it is difficult to determine the true edge position due to "bubbles"; for the length and pulse width of the tap delay chain data sequence There are problems such as higher condition restrictions; and the use of more hardware resources, resulting in long development cycles, increased power consumption and cost, making the delay chain interpolation time-to-digital converter have low universality and multiple edge problems. Changing the position consumes a lot of logic resources and has a complex structure, which leads to problems such as long system development cycle, increased power consumption and cost.

In view of this, embodiments of the present disclosure provide a data processing method, which includes: grouping multiple data in the original data sequence to obtain multiple target subsequences; inputting each target subsequence to the target subsequence respectively. In the lookup table array set corresponding to the sequence, the target values corresponding to multiple target subsequences are obtained, where the target value represents the sum of position information of data with adjacent positions in the target subsequence and different data values; based on multiple target subsequences The target value corresponding to each sequence determines the target value of the original data sequence.

Figure 1 schematically shows a flow chart of a data processing method according to an embodiment of the present disclosure.

As shown in Figure 1, the data processing method according to the embodiment of the present disclosure includes operations S110 to S130.

In operation S110, multiple data in the original data sequence are grouped to obtain multiple target subsequences.

According to embodiments of the present disclosure, multiple data included in the original data sequence can be position-marked. For example, the original delay chain data with a length of m bits can be marked in order as the 0th bit, the 1st bit, ... m-1 bits, and then group them, for example: divide the original data sequence with a length of m bits into n groups, that is, group 0, group 1... group n-1, each group has a length of m/n bits, Counted as l bit.

According to embodiments of the present disclosure, when grouping the original data sequence, the kn+i-th bit data can be grouped into the k-th bit of the i-th group of tap data subsequences, where n is the number of groups, for example: the original data sequence is 0001110010. If the original data sequence is divided into two groups, the first target subsequence is 00101 and the second target subsequence is 01100. The 1st, 3rd, 5th, 7th, and 9th bits of the original data sequence are the first target. subsequence, the 2nd, 4th, 6th, 8th, and 10th bits are the second target subsequence.

According to embodiments of the present disclosure, the data type of the original data sequence is not limited. For example, it may be a tap delay chain data sequence, where the tap delay chain data sequence may be obtained through a delay chain consisting of multiple delay units; There are no restrictions on the type of delay unit. You can choose an appropriate delay unit according to actual needs, for example: CARRY4.

Figure 2 schematically shows a schematic diagram of a delay chain interpolation time-to-digital converter using a technology related to obtaining original data sequences.

According to embodiments of the present disclosure, when the original data sequence is a tap delay chain data sequence, the original data sequence can be obtained in the following manner: the time signal to be measured generates a periodic narrow pulse sequence through a trigger circuit, and the periodic narrow pulse The sequence passes through a tap delay chain composed of multiple delay units. The D flip-flop sequence uses the system clock cycle to sample and latch the results of each tap of the tap delay chain to obtain the original data sequence.

According to the embodiment of the present disclosure, the tap delay chain data sequence can obtain edge position information through the encoding circuit. The edge position information can also be called edge position information because there is a rising edge or a falling edge in the tap delay chain data sequence. The location information, or the location information of two adjacent data with different values. According to embodiments of the present disclosure, by grouping and rearranging the original data sequence, it is possible to eliminate "bubble" errors in the tap data subsequences, so that the position of the edge change in each tap data subsequence in the target subsequence is clear and accurate. .

In operation S120, each target subsequence is input into a lookup table array set corresponding to the target subsequence, and target values corresponding to each of the multiple target subsequences are obtained, where the target value represents the adjacent and adjacent positions in the target subsequence. The sum of location information of data with different data values.

According to the embodiment of the present disclosure, each target subsequence has a corresponding Look-Up-Table (LUT) array set. The LUT array set includes multiple LUT arrays, and in the LUT array It also includes multiple LUTs.

According to embodiments of the present disclosure, the number of input terminals of the lookup table is not limited, and lookup tables with different numbers of input terminals may be used according to specific circumstances.

According to embodiments of the present disclosure, positions with adjacent positions and different data values can be called edge-changing edge positions, and the target value can be characterized as the sum of position information where edge-changing edges occur, that is, the sum of edge-changing position information, and edge-changing edge positions. The sum of the position information is obtained from the position information of the edge change. For example, if the position information of the edge change is 7 and 9, then the sum of the edge change position information is 16, the sum of 7 and 9.

According to the embodiment of the present disclosure, the number of data bits that need to be input for each LUT can be input according to the actual situation, and data with edge changes can be input. For example: for a 6-input LUT array, The number of input data bits per time is 6, but the input data of each LUT in the LUT array is not necessarily 6 bits. It can be optimized and adjusted according to the input and output conditions to reduce resource consumption.

According to embodiments of the present disclosure, the number of data bits of the input data of each LUT in the LUT array is not limited, and may be the same or different.

According to embodiments of the present disclosure, the number of input terminals of each LUT in the LUT array is not limited. They can all be LUTs with the same number of input terminals, or they can all be LUT arrays with different numbers of input terminals. Similarly, they can also be LUT arrays with the same number of input terminals. There are LUTs with the same number of input terminals and LUTs with different numbers of input terminals in the array.

According to an embodiment of the present disclosure, the target value of the target subsequence can be obtained by inputting the data included in the target subsequence to the input end of the lookup table array respectively. .

According to an embodiment of the present disclosure, each group of l-bit target subsequences contains l-1 positions where edge changes may occur. An edge change may occur at position 0, which is between the 0th and 1st bits of the target subsequence data. An edge change may occur at an edge position 1, which is between the 1st and 2nd bits of the target subsequence data... An edge change may occur. Position l-2 is between the l-2nd and l-1th bits of the target subsequence data. Specifically, for example: if the x-th bit and the x+1-th bit of the subsequence are not equal, that is, when the x-th bit is 0 and the x+1-th bit is 1 or the x-th bit is 1 and the x+1-th bit is 0, then An edge change occurs, and the position where the edge change occurs is the x-th position. If the data of bit x and bit x+1 of the subsequence are equal, that is, bit x=0, bit x+1=0 or bit x=1, bit x+1=1, then no edge change occurs. .

According to embodiments of the present disclosure, to calculate the target value of each target subsequence, a parallel computing method may be used to input each target subsequence into the corresponding lookup table array in parallel. Similarly, serial processing can also be used, that is, after inputting a target subsequence into the lookup table array to obtain the target value of the target subsequence, the next target subsequence is input to obtain the target value of the target subsequence, until Get the target values of multiple target subsequences.

According to embodiments of the present disclosure, by inputting the target subsequences into the lookup table array set corresponding to the target subsequences, the target values corresponding to the multiple target subsequences can be obtained, thereby achieving the acquisition of the target value, that is, the variable position information. The summing process uses less hardware resources, short encoding time, and high positioning accuracy. And the target value of each target subsequence can be obtained in parallel or serial manner according to the needs, with more selectivity. When the parallel method is used to obtain each target subsequence, there are advantages of fast processing speed, simple structure, and small dead time. However, when the serial method is used to obtain the target value of each target subsequence, there is a logical problem. The structure can run at a higher clock frequency, has the advantages of small dead time and high throughput rate.

In operation S130, the target value of the original data sequence is determined based on the corresponding target values of the plurality of target sub-sequences.

According to embodiments of the present disclosure, the target values corresponding to the multiple target sub-sequences are subjected to a first calculation process to obtain the target value of the original data sequence, where the first calculation process may be an addition calculation or the like.

According to the embodiment of the present disclosure, the size of the target value of the original data sequence is positively related to the size of the delay value. The target value can be converted into a delay time value through a first calculation method, such as a code density statistical method, that is, The fine time data, combined with the second calculation method, such as the coarse time data obtained by the high-speed clock counting method, can be used to obtain the measured size of the time interval value of the time signal to be measured, and the measured time interval value has higher measurement accuracy. technical effects.

According to the data processing method provided by the present disclosure, by grouping multiple data in the original data sequence, multiple target subsequences can be obtained, and the multiple target subsequences are respectively input into the lookup table array set corresponding to the target subsequence. , the target value corresponding to each target subsequence can be obtained. Based on the target values of multiple target subsequences, the target value of the tap delay chain data can be obtained. Since multiple data in the original data sequence are grouped, multiple target subsequences are obtained, so that the subsequence contains at most one bubble error, because some subsequences do not contain bubble errors and have two-bit data with "bubble" errors. will not appear in the same target subsequence. Therefore, the problem of difficulty in determining the true edge change position is at least partially solved, and the technical effect of determining the accuracy of the edge change position is achieved. Since each target subsequence is input into the lookup table array set corresponding to the target subsequence, multiple target subsequences are processed in parallel, and the target value corresponding to each target subsequence is quickly obtained, and Determining the target value of the original data sequence based on the target values of multiple target subsequences at least partially solves the problems of relatively high condition restrictions and the use of more hardware resources in related technologies, achieving hardware resource saving and high universality. , few conditional limits, short encoding time for the original data sequence, and high accuracy of the original data sequence target value.

FIG. 3 schematically illustrates a flowchart of determining multiple target subsequences according to an embodiment of the present disclosure.

As shown in Figure 3, determining multiple target subsequence target values includes operations S111 to S112.

In operation S111, the number of packets of the original data sequence is determined based on the plurality of data in the original data sequence.

In operation S112, multiple data are grouped to obtain multiple target subsequences based on the number of groups and respective position identifiers of the multiple data in the original data sequence.

According to embodiments of the present disclosure, the target adjacent edge change distance in the narrow pulse sequence can be determined based on the time signal to be measured based on multiple data in the original data sequence, that is, the target of at least one narrow pulse included in the narrow pulse sequence is determined. Pulse width, where the narrow pulse sequence can be determined from multiple data in the original data sequence, including a target data group of multiple consecutive target data with the same data value, and the fuzzy area of the original data sequence can be determined, and the fuzzy area is Due to the "bubble" error, the length of the region can be determined based on the fuzzy region, and the number of groups of the original data sequence can be determined using the region depth and the distance between adjacent edges of the target.

According to embodiments of the present disclosure, multiple data can be grouped based on the number of groups and the respective position identifiers of the multiple data in the original data sequence, thereby obtaining multiple target subsequences, where the grouping method is not limited, and can Any two-bit data that can change the "bubble" error of the same edge will not exist in any grouping method within the same target sub-sequence.

According to an embodiment of the present disclosure, the grouping method may be a method of grouping the kn+i-th bit data of the original data sequence into the k-th bit data of the i-th group of target subsequences, that is, each bit of data of the original data sequence is divided into order. into each target subsequence, for example: the original data sequence includes 111000111000 and the number of groups is 4, then the first data of the first target subsequence is 1, the first data of the second target subsequence is 1, and the first data of the second target subsequence is 1. The first bit of data in the three-target subsequence is 1, and the first bit of data in the fourth target subsequence is 0. Similarly, the second bit of data in the first target subsequence is 0, and the second bit of the second target subsequence is 0. The data is 0, the second bit of data of the third target subsequence is 1, the second bit of data of the fourth target subsequence is 1, and the third bit of data of the first target subsequence is 1, and the data of the second bit of the second target subsequence is 1. The third bit of data is 0, the third bit of data of the third target subsequence is 0, the third bit of data of the fourth target subsequence is 0, and finally the first target subsequence is 101, and the second target subsequence is 100...The fourth target subsequence is 010.

According to embodiments of the present disclosure, the target adjacent edge change distance and the region length can be determined based on multiple data in the original data sequence. The region length and the target adjacent edge change distance can be used to determine the number of groups of the original data sequence, and then Grouping the original data sequence can quickly eliminate "bubble" errors. At the same time, when determining the edge position of the original data sequence, that is, encoding, the number of pulses, changes in pulse width, and changes in the delay value of the delay unit can be reduced. , tap delay chain length are not sensitive, and have strong universality, expandability and portability.

According to an embodiment of the present disclosure, determining the number of groups of the original data sequence based on multiple data in the original data sequence includes the following operations.

Determine at least one target data group from multiple data in the original data sequence, where the target data group includes multiple target data with continuous positions and the same data value; determine the target adjacent edge change distance based on the target data group, where , the target adjacent edge-changing edge distance is the data amount of the target data group including the minimum data amount in at least one target data group; from multiple data of the original data sequence, determine the presence of multiple area information of edge-changing edges; based on multiple area information, determine multiple target areas; determine the length of the target area based on the respective area lengths of the multiple target areas, where the target area length represents the maximum area length among the respective area lengths of the multiple target areas; based on the adjacent edges of the target The changing edge distance and the target area length determine the number of packets of the original data sequence, where the number of groups is less than or equal to the target adjacent edge changing edge distance and the number of groups is greater than or equal to the target area length.

According to embodiments of the present disclosure, the original data sequence may include multiple target data groups with the same and continuous data values. The target data group may include multiple target data. The target data is not limited. For example, the target data may be Data with a data value of 1.

According to embodiments of the present disclosure, the target data group may be a narrow pulse sequence. Based on the data amount of the target data included in the target data group, the distance between adjacent edges, that is, the pulse width, may be determined. The target data group may be multiple , or it can be 1. The data amount of the target data group with the smallest data amount among multiple target data groups can be the target adjacent edge change edge distance. When there is one target data group, the data amount of the target data group is the target adjacent edge change distance.

According to embodiments of the present disclosure, when the target data group is a narrow pulse sequence, the process of determining the target adjacent edge change distance based on the data amount of the target data may be, for example: the original data sequence is 01111111111110110000000000000110111111110100, and the delay unit starts from the original data sequence. The data sequence can determine the two target data groups, that is, the two pulse sequences are 111111111111 and 11111111. The data amounts of the two target data groups can be determined to be 12 and 8 respectively. Then the distance between adjacent edges in the data sequence is The pulse widths are 12 and 8 respectively. Among them, the data amount of the target data group with the smallest data amount is the target adjacent edge-to-edge distance. Therefore, the target adjacent edge-to-edge distance is 8. The calculation method for the data amount is not carried out. The limit can be determined based on the number of data bits included in the data set.

According to an embodiment of the present disclosure, the area information may be area information in which there is an edge change. The edge change is a situation where data with adjacent positions and different data values exist. For example, 01 and 10 both indicate that there are edge changes.

According to embodiments of the present disclosure, the target area can be determined based on multiple area information. For example: in the case where the original data sequence is 0001001111111111101100000000000001101111111101000, the multiple area information can be determined based on edge changes and can be...00100...,...0011...,... 10110…,…00110…,…110100…,…110…. The target area can be a fuzzy area, it can be an area where multiple 1s are mixed with 0s, or multiple 0s are mixed with 1s. For a normal edge-to-edge area where multiple 0s transform into multiple 1s or multiple 1s transform into multiple 0s, It is not considered to be a target area. For example: based on the above target area, it can be...100...,...011...,...110...,...01...

According to embodiments of the present disclosure, the length of the target area can be the number of data bits included in the area, which can also be called bubble depth. For example: in the above target area, the area lengths can be determined to be 3, 3, 3, 2, and the target area length is the largest area length among them, which can be 3.

According to embodiments of the present disclosure, based on the target area length and the target adjacent edge change distance, the number of groups can be determined, that is, the number of groups is less than or equal to the target adjacent edge change distance and the number of groups is greater than or equal to the target area length. Based on the above For example, when the target adjacent edge-to-edge distance is 8 and the target area length is 3, the number of groups can be any integer value between [3, 8], such as: 3, 4, 5, 6, 7, 8 .

According to embodiments of the present disclosure, the number of groups determined based on the target adjacent edge change distance and the target area length can make each pulse of the narrow pulse sequence sampled in all target subsequences, and the same edge change Bubble error means that no two bits of data appear in the same target subsequence, so that the edge-to-edge position information in the target subsequence is clear and accurate, and there is no bubble error. At the same time, when determining the edge position information of the target subsequence, it is not sensitive to the number of pulses, pulse width changes, delay unit delay value changes, and tap delay chain length. It ensures that the number of groups is less than or equal to the target adjacent When the distance between edges changes and the number of groups is greater than or equal to the length of the target area, the data processing method of the present disclosure can be used for any number of pulses, pulse width changes, delay unit delay value changes, and tap delay chain lengths. Therefore, it has It has strong universality and scalability. When using it, you can easily add or remove modules according to your needs.

According to an embodiment of the present disclosure, the lookup table array set includes multiple lookup table arrays, and the lookup table array includes multiple lookup tables; each target subsequence is input into the lookup table array set corresponding to the target subsequence. , obtaining the target values corresponding to multiple target subsequences includes the following operations.

For each target subsequence, based on the number of input terminals of the lookup table in the lookup table array, determine multiple subsequence fragments from the target subsequence; input the multiple subsequence fragments into the corresponding lookup table array respectively, and obtain Target values corresponding to multiple subsequence fragments; based on target values corresponding to multiple subsequence fragments, the target value of the target subsequence is obtained.

According to an embodiment of the present disclosure, multiple subseries fragments can be determined from the target subsequence based on the number of input terminals of the lookup table in the lookup table array. For example: for a 6-input lookup table, the 0th of the target subsequence can be ~5 bits of data are connected to the first group of configured LUT arrays, 5~10 bits of data are connected to the second group of configured LUT arrays, and 10~15 bits of data are connected to the third group of configured LUT arrays. , connect the l-6th to l-1th bits of the subsequence to the LUT array l/5, where l represents the number of data bits of the target subsequence. The number of LUTs in each group of configured LUT arrays can be selected according to specific circumstances, that is, when the target subsequence is 000111000011110, the subsequences can be 000111, 100001, and 11110 respectively.

According to embodiments of the present disclosure, each subsequence fragment contains a corresponding lookup table array. The number of lookup tables included in the lookup table array corresponding to each subsequence fragment is not limited. It can be based on each subsequence fragment. Determine each.

According to embodiments of the present disclosure, the output of each LUT may be a one-bit binary code representing 0 or 1. Since the LUT array corresponding to each sub-sequence slice may contain multiple LUTs, multiple bits output by one LUT array Binary code can be used to obtain the target value of the subsequence fragments included in the target subsequence. For example, if the output of a LUT array is 0010000, then its target value is 0010000. Similarly, the target value can also be converted into decimal data, which is 16.

According to an embodiment of the present disclosure, the target value of the target subsequence can be obtained by dividing the target values corresponding to each of the multiple subsequences into slices and adding them through an adder respectively.

According to the embodiment of the present disclosure, each target subsequence is divided into multiple subsequence fragments, and the target value of each subsequence fragment is calculated respectively, and finally the target value of the target subsequence is obtained, which can make it possible to determine the target subsequence. During the target value process, only the intermediate data of the target value of the subsequence fragments is generated, and the target value of the target subsequence can be obtained by adding the target values of multiple subsequence fragments. The calculation method is also relatively simple, so that The determination of the target value of the target subsequence is efficient and can achieve the same accuracy as determining the edge position information one by one. At the same time, a small amount of hardware resources can be used to determine the target value of the target subsequence, to a certain extent. Resource saving is achieved, and the input end of the lookup table is not limited. When the number of input data bits is small, a lookup table with fewer input ends can be used to achieve resource saving.

According to embodiments of the present disclosure, it is possible to input sub-sequence slices into the lookup table array in parallel to obtain target values, thereby speeding up the calculation rate and minimizing the dead time. The subsequences can also be sliced serially or input one by one into the corresponding lookup table array, which can make the decoding logic run at a very high clock frequency, with small overall dead time and high throughput.

Figure 4 schematically shows a schematic diagram of a lookup table array according to an embodiment of the present disclosure.

As shown in Figure 4, the LUT array includes multiple LUTs. Taking a 6-input LUT as an example, each LUT has 6 input terminals. Each LUT outputs a bit of binary code. By dividing the sub-sequence into multiple slices, By inputting into the LUT array, multiple-bit binary codes can be obtained at the same time. By sorting the multiple-bit binary codes in order, the target value of the sub-sequence fragmentation can be obtained. For example, you can specify the most significant bit (MSB) of any data in the binary code as needed, and the least significant bit (LSB) of any data in the binary code as needed.

According to an embodiment of the present disclosure, in the case where the number of data bits included in the subsequence slice is less than the number of input terminals of the lookup table, the target input data of the input terminal where there is no input data is set to the predetermined data.

According to the embodiment of the present disclosure, the number of input digits of the input data of the LUT is not limited. It can be determined according to the number of input terminals of the LUT, so that each input terminal has its own input data, or it can be determined according to the requirements. There is an edge change, that is, data with adjacent positions and different data values is input into the LUT.

According to an embodiment of the present disclosure, based on the target subsequence, when the number of data bits in the obtained subsequence fragment does not meet the LUT input number of bits, that is, when the number of input data bits is less than the number of input terminals of the lookup table, The input data of the remaining input terminals can be set to predetermined data. The predetermined data can be 0 or 1, which can be determined by the actual situation. For example: if the output data when the tap delay chain has no input is all 0, the predetermined data can be set to 0. The data is set to 0. If the data when the tap delay chain is not input are all 1, the predetermined data can be set to 1.

According to an embodiment of the present disclosure, when the number of input data bits is less than the number of input terminals of the current lookup variable, the lookup table can also be updated to a lookup table with the number of input terminals mod (l, 5) + 1.

According to embodiments of the present disclosure, subsequence fragmentation may include a situation where the number of data bits does not satisfy the LUT input number of bits, which may include a situation where the number of data bits of the target subsequence cannot be divisible by the number of LUT input terminals.

According to an embodiment of the present disclosure, based on multiple sub-sequence fragments of the target sub-sequence, the maximum target value of each of the multiple sub-sequence fragments is determined; based on the maximum target value of each of the multiple sub-sequence fragments, the corresponding maximum target value of each sub-sequence fragment is determined. The number of lookup tables included in the lookup table array.

According to an embodiment of the present disclosure, the maximum target value of each of the multiple subsequence fragments can be determined based on the multiple subsequence fragments of the target subroutine, wherein the maximum target value can be calculated according to possible edge changes of the subsequence fragments. The maximum target value obtained is the sum of the maximum edge position information. For example: for the zeroth subsequence fragment of the target subsequence, there may be a sequence containing the maximum target value of 010101. Since there are 5 edge-changing edge positions, they are 1, 2, 3, 4, 5, then the maximum target value of the zeroth subsequence fragment is 15. Similarly, if it is the first subsequence fragment, the possible sequence including the maximum target value is 010101. Since there are The five edge-changing positions are 6, 7, 8, 9, and 10 respectively. Therefore, the maximum target value of the first sub-sequence fragment is 40.

According to an embodiment of the present disclosure, the number of lookup table arrays corresponding to the subsequence fragment can be determined based on the maximum target value of the subsequence fragment. The determination method is not limited. For example, the maximum target value can be used to make the maximum target value less than or equal to 2. ^r -1 and greater than or equal to 2 ^r-1 to determine, r represents the number of lookup tables contained in the lookup table array. For example, for a subsequence fragment with a maximum target value of 40, if 2 ^{6 -1} <= 40 < = 2 ⁶ -1, then the number of lookup tables in the lookup table array corresponding to the subsequence fragment is 6.

According to an embodiment of the present disclosure, the LUT array contains at most r LUTs with s input. In most cases, r LUTs with less than or equal to s input can be used to complete the sharding conversion task.

According to an embodiment of the present disclosure, determining the target value of the original data sequence based on the target values corresponding to the multiple target subsequences includes: inputting the target values corresponding to the multiple target subsequences into an adder to obtain the original data sequence. target value.

According to embodiments of the present disclosure, the target values corresponding to each target subsequence are input into the adder at the same time to obtain the target value of the original data sequence. For example, the target values of each target subsequence are 33, 34, and 31 respectively. , 33, then the target value of the original data sequence is 32+34+31+33=130.

According to embodiments of the present disclosure, the original data sequence is divided into multiple target subsequences, the target values are determined respectively by dividing the target subsequences into multiple subsequence fragments, and then the original data can be obtained by adding the target values respectively. The target value of the sequence, based on the above, can achieve the same accuracy as positioning one by one. At the same time, it is not sensitive to the number of pulses, pulse width changes, delay unit delay value changes, and tap delay chain length. It ensures that the number of groups is less than or equal to When the target adjacent edge changes edge distance and the number of groups is greater than or equal to the length of the target area, any number of pulses, pulse width changes, delay unit delay value changes, and tap delay chain length will not have an impact. Therefore, it has a lot of advantages. It has strong universality and scalability. When using it, you can easily add or remove modules according to your needs.

FIG. 5 schematically shows a schematic diagram of a data processing method according to another embodiment of the present disclosure.

As shown in Figure 5, for a tap delay chain composed of 60 delay units, the original data sequence output is the tap delay chain data sequence, with 60 bits. When there is no pulse input, the pulse has not arrived, or the pulse has passed For the delay chain part, the delay chain output data is 0.

According to the embodiment of the present disclosure, when a signal to be measured passes through a trigger and generates a narrow pulse sequence and enters the delay chain, a valid tap delay chain data sequence will be output. For example, the output 60-bit tap delay chain data sequence is 00000000010011111111111101100000000000001101111111010000000. The output data of the delay unit where the pulse is located is 1, so the example data contains two narrow pulses.

According to the embodiment of the present disclosure, there are target areas of...100...,...011...,...110...,...01... at the pulse edge changing positions. This target area is caused by the "bubble" error. The length of the target area is defined as the number of bits where both 0 and 1 exist, which is the bubble depth. The bubble depths at the above four edge-changing positions are 3, 3, 3, and 2 respectively, and the maximum bubble depth is 3.

According to an embodiment of the present disclosure, the target data groups corresponding to the two narrow pulse sequences included in the above-mentioned tap delay chain data sequence are 111111111111 and 11111111 respectively. The data amount or pulse width is 12 and 8 respectively. The target pulse width is also called the target. The distance between adjacent edges is 8. By determining the distance between two adjacent edges, the corresponding data of the narrow pulse sequence in the target data group can be determined. The distance between two adjacent edges is determined by each target The amount of data in the data set is determined.

According to the embodiment of the present disclosure, based on the number of groups, it is ensured that each pulse of the narrow pulse sequence is sampled in all tap data sub-sequences, and the "bubble" error of the same edge change does not appear in the same In the tap data subsequence; that is, the minimum pulse width is greater than the number of groups and is greater than the maximum bubble depth. The number of groups needs to be greater than or equal to 3 and less than or equal to 8. For example: select the number of groups as 4, where the minimum pulse width is the target adjacent edge change distance.

According to the embodiment of the present disclosure, for the example output 60-bit tap delay chain data sequence "0000000001001111111111111011000000000000011011111111010000000", the kn+ith bit of the original code of the tap delay chain data is grouped into the kth bit of the i-th group of tap data subsequences. For grouping, for example, when n=4, the original sequence is divided into 4 groups of 15-bit tap data sub-sequences. They are respectively recorded as the 0th group of target subsequences, the 1st group of target subsequences, the 2nd group of target subsequences, and the 3rd group of target subsequences. The 15-bit data in each target subsequence is recorded as bit 0, bit 1...bit 14 in order.

According to an embodiment of the present disclosure, for example, the 11th bit of the tap delay chain data sequence, that is, the (2*4+3) bit is grouped into the 2nd bit of the third group of target subsequences. Obtained according to the above grouping scheme:

The target subsequence of group 0 is: 000111000011110; the target subsequence of group 1 is: 001111100011100; the target subsequence of group 2 is: 000111100001100; the target subsequence of group 3 is: 000111000011000.

According to the embodiment of the present disclosure, as shown in Figure 5, a plurality of dedicated logic circuits are included. The professional logic circuit can be a Wave Union A-type TDC encoding dedicated logic circuit, and a Wave Union A-type TDC encoding dedicated logic circuit 0~WaveUnion A Type TDC coding dedicated logic circuit 4 corresponds to each group of target sub-sequences respectively.

According to an embodiment of the present disclosure, each Wave Union A-type TDC encoding dedicated logic circuit includes its own LUT array. For example, the Wave Union A-type TDC encoding dedicated logic circuit 0 includes LUT array 0 to LUT array 2 .

According to embodiments of the present disclosure, the LUT array corresponds to each subsequence slice.

According to the embodiment of the present disclosure, taking the 0th group of target subsequences and a 6-input LUT array as an example, the subsequence slicing operation is performed, then the 0th subsequence slicing is the 0th to 5th bits of the target subsequence: 000111, then The first subsequence fragment is the 5th to 10th bits of the target subsequence: 100001, and the second subsequence fragment is the 10th to 14th bits of the target subsequence: 11110.

According to the embodiment of the present disclosure, taking the first subsequence fragment 100001 of the 0th group of target subsequences as an example, connect it to the configured LUT array 1; since the first subsequence fragment 100001 of the 0th group of target subsequences The data corresponds to two edge positions, which are 6 and 10 respectively; then the configured LUT array 1 outputs data 16(O), which is 0010000(B), which is all edge positions and data in the slice. In the same way, all edge-changing positions and data in the 0th slice are 3(O), and all edge-changing positions and data in the 2nd slice are 14(O), where O represents decimal and B represents binary.

According to embodiments of the present disclosure, the above steps are all executed in parallel in hardware, and all edge positions and data in the obtained subsequence slices are directly added to obtain the sum of edge position information of each group of target subsequences. For the 0th group of tap data subsequences, the sum of their edge change positions is 33; for the 1st to 3rd groups of tap data subsequences, the sum of their edge change position information is 34, 31, and 32 respectively;

According to an embodiment of the present disclosure, by adding the sum of the edge position information of each group of target subsequences, the target value of the original data sequence can be obtained as 32+34+31+33=130.

According to the embodiment of the present disclosure, the sum information of all edge-changing positions of the narrow pulse sequence in the tap delay chain is directly related to the fine time of the arrival time of the signal to be measured, and the time interval to be measured can be measured by integrating the coarse time information. .

Figure 6 schematically shows a schematic diagram of an encoding circuit according to an embodiment of the present disclosure.

As shown in FIG. 6 , the encoding circuit includes a plurality of dedicated logic circuits 610 and a first adder 620 .

A plurality of dedicated logic circuits 610 are used to convert the target subsequence corresponding to each dedicated logic circuit into a target value, where the target subsequence is obtained based on the original data sequence grouping.

The first adder 620 is respectively connected to a plurality of dedicated logic circuits, and is used to add a plurality of target values to obtain the target value of the original data sequence.

According to an embodiment of the present disclosure, the encoding circuit includes a plurality of dedicated logic 610 and a first adder 620. Based on the plurality of dedicated logic circuits 610, multiple target subsequences obtained by grouping the original data sequence can be converted into respective target subsequences. The target value, wherein for different target sub-sequences can correspond to exactly the same or similar dedicated logic circuits.

According to an embodiment of the present disclosure, the first adder 620 is respectively connected to a plurality of dedicated logic circuits, and can add the output value of each dedicated logic circuit, that is, the target value of the target subsequence, to obtain the original data sequence. target value.

According to embodiments of the present disclosure, there may be multiple dedicated logic circuits or one dedicated logic circuit. If there are multiple dedicated logic circuits, the target subsequences can be processed in parallel. If there is one patented logic circuit, the target subsequences can be processed in a pipeline manner. , process the target subsequences one by one.

According to an embodiment of the present disclosure, the original data sequence includes a tap delay chain data sequence.

According to embodiments of the present disclosure, the encoding circuit uses multiple dedicated logic circuits and the first adder to determine the target value of the original data sequence, that is, the sum of edge position information of the original data sequence, effectively saving hardware resources and greatly The encoding time is shortened and the same accuracy as positioning one by one can be achieved.

According to embodiments of the present disclosure, parallel processing of target subsequences based on dedicated logic circuits can achieve the effects of simple structure and small dead time. Pipeline processing based on dedicated logic circuits can realize that the entire encoding logic can run at a very high clock frequency, with a small overall dead time and a high throughput rate.

According to the embodiments of the present disclosure, in order to verify the feasibility, the following experiments are conducted. After the data processing method is instantiated in the FPGA, behavioral level simulation is performed. The simulation is run on the Vivado software platform, where the Vivado software platform includes a highly integrated design environment and A new generation of system-to-IC-level tools built on a shared extensible data model and common debugging environment. The input data is a 352-bit raw data sequence. The 11-bit binary data can be encoded as required to represent the sum of all edge positions in the original data sequence, and the enable signal is accurate. Finally, the time-to-digital converter tap delay chain encoding method disclosed in the present invention is used in the XC7K410T-2FFG900I FPGA of Xilinx, and the encoding circuit can operate stably under a 400MHz clock.

The dedicated logic circuit includes: a lookup table array set 611 for converting a subsequence slice corresponding to each lookup table array in the lookup table array set into a subtarget value, wherein the subsequence slice is based on the target subsequence Obtained by grouping, the sub-target value is the target value of the sub-sequence fragmentation. The look-up table array set includes multiple look-up table array second adders 612, which are respectively connected to multiple look-up table arrays and are used to add the sub-target values. Obtained The target value of the target subsequence.

According to an embodiment of the present disclosure, the dedicated logic circuit includes a lookup table array set and a second adder. By inputting the subsequence slices into the corresponding lookup table array, each subsequence's respective target value can be obtained. The target The value can be binary data, for example: the first output can be the most significant, and the last output can be the least significant. By adding the target values through the second adder, the target value of each target subsequence can be obtained.

Figure 7 schematically illustrates a schematic diagram of a dedicated logic circuit according to an embodiment of the present disclosure.

As shown in Figure 7, taking a six-input lookup table as an example, the dedicated logic circuit includes a lookup table array and an adder. The lookup table array includes multiple lookup tables. Each lookup table can output a binary code. A lookup table can output the target value of the subsequence fragments. By adding the target values of each subsequence through the second adder, the target value of the target subsequence can be obtained, that is, the sum of the edge position information.

According to embodiments of the present disclosure, the number of input terminals of the lookup table is only illustrative, and lookup tables with different numbers of input terminals may be used according to actual conditions.

Figure 8 schematically shows a timing diagram according to an embodiment of the present disclosure.

As shown in Figure 8, for recording valid data in the clock cycle and marking it in the original data sequence, valid data 0 and valid data 1 can be obtained. Due to the process of determining from the original data sequence to the target subsequence, The main purpose is to group the data included in the original data sequence to obtain the target subsequence. Therefore, the clock cycles of valid data 0 and valid data 1 in the target subsequence are the same. In the process of determining the sum of edge position information based on the target subsequence, it is necessary to use the LUT array set and the adder for calculation. Therefore, the effective data 0 and the valid data 1 in the timing diagram of the edge position data of the target subsequence go to After delaying one clock cycle, the edge position information of the original data sequence is obtained. In the same way, the edge position information sum of the original data sequence is still obtained by adding the edge position information and the respective edge positions of the target subsequence. Therefore, the original data The edge position data of the sequence is delayed by one clock cycle. Finally, the data storage control signal can be used. Data storage tools, such as First Input First Output (FIFO), are used to control data storage. The above original The timing of the data sequence is recorded.

The above-mentioned specific embodiments further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above-mentioned are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Based on the above data processing method, the present disclosure also provides a data processing device. The device will be described in detail below with reference to FIG. 9 .

Figure 9 schematically shows a structural block diagram of a data processing device according to an embodiment of the present disclosure.

As shown in FIG. 9 , the data processing apparatus 900 of this embodiment includes a target subsequence determination module 910 , a first target value determination module 920 and a second target value determination module 930 .

The target subsequence determination module 910 is used to group multiple data in the original data sequence to obtain multiple target subsequences. In an embodiment, the target subsequence determination module 910 may be configured to perform the operation S110 described above, which will not be described again here.

The first target value determination module 920 is used to input each target subsequence into a lookup table array set corresponding to the target subsequence, and obtain target values corresponding to the multiple target subsequences, where the target value represents the target subsequence. The sum of the position information of data with adjacent positions and different data values in the sequence. In an embodiment, the first target value determination module 920 may be configured to perform the operation S120 described above, which will not be described again here.

The second target value determination module 930 is configured to determine the target value of the original data sequence based on the corresponding target values of the multiple target subsequences. In an embodiment, the second target value determination module 930 may be configured to perform the operation S130 described above, which will not be described again here.

According to an embodiment of the present disclosure, the target subsequence determining module 910 may include a packet number determining submodule and a target subsequence determining submodule.

The group number determination submodule is used to determine the number of groups of the original data sequence based on multiple data in the original data sequence.

The sub-sequence determination submodule is used to group multiple data to obtain multiple target sub-sequences based on the number of groups and the respective position identifiers of the multiple data in the original data sequence.

According to an embodiment of the present disclosure, the group number determination sub-module may include a target data group determination unit, a target adjacent edge change edge distance determination unit, an area information determination unit, a target area determination unit, a target area length determination unit, and a group number determination unit. .

The target data group determination unit is used to determine at least one target data group from multiple data in the original data sequence, wherein the target data group includes multiple target data with consecutive positions and the same data value.

The target adjacent edge-changing edge distance determination unit is used to determine the target adjacent edge-changing edge distance based on the target data group, wherein the target adjacent edge-changing edge distance is a target data group including a minimum amount of data in at least one target data group. amount of data.

The area information determination unit is used to determine, from multiple data in the original data sequence, multiple area information with edge changes.

The target area determination unit is used to determine multiple target areas based on respective area lengths of the multiple area information.

The target area length determining unit is configured to determine the target area length based on the respective area lengths of multiple target areas, wherein the target area length represents the maximum area length among the respective area lengths of the multiple target areas.

A group number determination unit, used to determine the number of groups of the original data sequence based on the target adjacent edge change distance and the length of the target area, wherein the number of groups is less than or equal to the target adjacent edge change distance and the number of groups is greater than or equal to the target area length.

According to an embodiment of the present disclosure, the lookup table array set includes multiple lookup table arrays, and the lookup table array includes multiple lookup tables; the first target value determination module includes a subsequence fragmentation determination submodule, a subsequence fragmentation target a value determination sub-module and a first target value determination sub-module.

The subsequence fragment determination submodule is used for determining, for each target subsequence, a plurality of subsequence fragments from the target subsequence based on the number of input terminals of the lookup table in the lookup table array.

The sub-sequence fragment target value determination sub-module inputs multiple sub-sequence fragments into the corresponding lookup table array to obtain the corresponding target values of the multiple sub-sequence fragments.

The first target value determination submodule is used to obtain the target value of the target subsequence based on the corresponding target values of multiple subsequence fragments.

According to an embodiment of the present disclosure, the data processing device 900 further includes an input processing module.

The input end processing module is used to set the target input data of the input end where there is no input data as predetermined data when the number of data bits included in the subsequence fragment is less than the number of input ends of the lookup table.

According to an embodiment of the present disclosure, the data processing apparatus 900 further includes a maximum target value determination module and a lookup table number determination module.

The maximum target value determination module is used to determine the maximum target value of each of the multiple subsequence fragments based on the multiple subsequence fragments of the target subsequence.

The lookup table quantity determination module is configured to determine the number of lookup tables included in the lookup table array corresponding to each subsequence fragment based on respective maximum target values of the plurality of subsequence fragments.

According to an embodiment of the present disclosure, the second target value determination module includes a target value input sub-module.

The target value input submodule is used to input the corresponding target values of multiple target subsequences into the adder to obtain the target value of the original data sequence.

According to embodiments of the present disclosure, any multiple modules of the target subsequence determination module 910, the first target value determination module 920, and the second target value determination module 930 may be combined and implemented in one module, or any one of the modules may be is split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules may be combined with at least part of the functionality of other modules and implemented in one module. According to an embodiment of the present disclosure, at least one of the target subsequence determination module 910, the first target value determination module 920, and the second target value determination module 930 may be at least partially implemented as a hardware circuit, such as a field programmable gate array ( FPGA), programmable logic array (PLA), system-on-a-chip, system-on-substrate, system-on-package, application-specific integrated circuit (ASIC), or any other reasonable means by which circuits can be integrated or packaged To be implemented, or to be implemented in any one of the three implementation methods of software, hardware and firmware or in an appropriate combination of any of them. Alternatively, at least one of the target subsequence determination module 910, the first target value determination module 920, and the second target value determination module 930 may be at least partially implemented as a computer program module that, when executed, may execute Corresponding functions.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operations of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code that contains one or more logic functions that implement the specified executable instructions. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown one after another may actually execute substantially in parallel, or they may sometimes execute in the reverse order, depending on the functionality involved. It will also be noted that each block in the block diagram or flowchart illustration, and combinations of blocks in the block diagram or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or operations, or may be implemented by special purpose hardware-based systems that perform the specified functions or operations. Achieved by a combination of specialized hardware and computer instructions.

Those skilled in the art will understand that the features described in the various embodiments and/or claims of the present disclosure may be combined or/or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, various combinations and/or combinations of features recited in the various embodiments and/or claims of the disclosure may be made without departing from the spirit and teachings of the disclosure. All such combinations and/or combinations fall within the scope of this disclosure.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment is described separately above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (10)

1. A data processing method, comprising:

grouping a plurality of data in an original data sequence to obtain a plurality of target subsequences;

inputting each target subsequence into a lookup table array set corresponding to the target subsequence respectively to obtain target values corresponding to the target subsequences, wherein the target values represent the sum of position information of data with adjacent positions and different data values in the target subsequence;

and determining the target value of the original data sequence based on the target values corresponding to the target subsequences.

2. The method of claim 1, wherein the grouping the plurality of data in the original data sequence to obtain the plurality of target subsequences comprises:

Determining a number of packets of the original data sequence based on a plurality of data in the original data sequence;

and grouping the plurality of data based on the grouping number and the position identification of each of the plurality of data in the original data sequence to obtain a plurality of target subsequences.

3. The method of claim 2, wherein the determining the number of packets of the original data sequence based on the plurality of data in the original data sequence comprises:

determining at least one target data group from a plurality of data of the original data sequence, wherein the target data group comprises a plurality of target data with continuous positions and identical data values;

determining a target adjacent edge distance based on the target data sets, wherein the target adjacent edge distance is the data amount of a target data set comprising the minimum data amount in the at least one target data set;

determining a plurality of region information with edge from a plurality of data of the original data sequence;

determining a plurality of target areas based on the plurality of area information;

determining a target region length based on the respective region lengths of the plurality of target regions, wherein the target region length characterizes a maximum region length of the respective region lengths of the plurality of target regions;

And determining the number of packets of the original data sequence based on the target adjacent edge distance and the target area length, wherein the number of packets is less than or equal to the target adjacent edge distance and the number of packets is greater than or equal to the target area length.

4. The method of claim 1, wherein the set of look-up table arrays includes a plurality of look-up table arrays, the look-up table arrays including a plurality of look-up tables;

inputting each target subsequence into a lookup table array set corresponding to the target subsequence respectively to obtain target values corresponding to the target subsequences, wherein the method comprises the following steps:

for each of the target subsequences, determining a plurality of subsequence slices from the target subsequence based on a number of inputs to a lookup table in the lookup table array;

inputting the plurality of sub-sequence fragments into corresponding lookup table arrays respectively to obtain target values corresponding to the plurality of sub-sequence fragments respectively;

and obtaining the target value of the target subsequence based on the target values corresponding to the subsequence fragments.

5. The method of claim 4, further comprising:

And setting target input data of the input end without input data as preset data under the condition that the number of data bits included in the sub-sequence fragments is smaller than the number of the input ends of the lookup table.

6. The method of claim 1, further comprising:

determining a respective maximum target value of a plurality of sub-sequence fragments based on the plurality of sub-sequence fragments of the target sub-sequence;

and determining the number of the lookup tables included in the lookup table array corresponding to each sub-sequence slice based on the respective maximum target values of the sub-sequence slices.

7. The method of claim 1, wherein the determining the target value of the original data sequence based on the target values for each of the plurality of target subsequences comprises:

and inputting the target values corresponding to the target subsequences into an adder to obtain the target value of the original data sequence.

8. The method of claim 1, wherein the original data sequence comprises a tapped delay chain data sequence.

9. An encoding circuit, comprising:

a plurality of special logic circuits, which are used for converting a target subsequence corresponding to each special logic circuit into a target value, wherein the target subsequence is obtained based on the grouping of the original data sequence;

And the first adder is respectively connected with the plurality of special logic circuits and is used for adding the plurality of target values to obtain the target value of the original data sequence.

10. The encoding circuit of claim 9, wherein the dedicated logic circuit comprises:

a set of lookup table arrays for converting sub-sequence slices corresponding to each lookup table array in the set of lookup table arrays into sub-target values, wherein the sub-sequence slices are grouped based on the target sub-sequence, the sub-target values are target values of the sub-sequence slices, and the set of lookup table arrays comprises a plurality of lookup table arrays;

and the second adder is respectively connected with the plurality of lookup table arrays and is used for adding the sub-target values to obtain the target value of the target sub-sequence.