CN117276087A - Packaging method of chip - Google Patents

Abstract

Embodiments of the present invention provide a chip packaging method. The chip packaging method includes providing a frame, and the frame includes a first pin area and a second pin area arranged oppositely; processing the second pin area to obtain at least A second pin pair, the size of the pin in the second pin pair is larger than the first preset required size; a chip is provided, and the chip is packaged on the frame. This application can enhance the strength of the lead frame and reduce the risk of deformation by designing the size of the pin to be larger than the required size when designing the lead frame; in addition, the pin is designed with an oversized size, so during production, it is necessary to Use a cutting die to cut off the excess part. In this way, by modifying the position and size of the cutting die and processing the same set of lead frames, products with different pin sizes and positions can be produced. When the pin position and size need to be changed, it only needs to be modified to cut off the mold, which greatly reduces development time and costs.

Description

A chip packaging method

Technical field

The present invention relates to the field of semiconductors, and in particular, to a chip packaging method.

Background technique

When designing the lead frame of similar products currently on the market, the size and position of the pins will be designed according to the requirements of the upper board of the terminal. If the terminal wants to modify the position of the upper board, the lead frame and corresponding mold design must be modified. Therefore, additional mold costs will be incurred, and the production of new molds will also take up a lot of time, resulting in low development efficiency. And the frame strength is low and easy to deform.

Therefore, how to solve the above problems is an urgent problem that needs to be solved at present.

Contents of the invention

The technical problem to be solved by the present invention is to provide a chip packaging method to solve the above problems.

In order to solve the above technical problems, the present invention provides the following technical solutions:

In a first aspect, this application provides a chip packaging method, which method includes:

Provide a frame, the frame including a first pin area and a second pin area arranged oppositely;

Process the second pin area to obtain at least one second pin pair, and the size of the pin in the second pin pair is greater than the first preset required size;

A chip is provided, and the chip is packaged on the frame.

In a possible embodiment, the method further includes:

The first pin area is processed to obtain a plurality of first pin pairs, and the size of the pins in the first pin pairs is larger than the second preset required size.

In a possible embodiment, the method further includes:

The first pin area is processed to obtain a plurality of first pin pairs and at least one third pin pair. The size of the pins in the first pin pair and the third pin pair is greater than Second preset required size.

In a possible embodiment, the size of the pins in the third pair of pins is larger than the size of the pins in the first pair of pins.

In a possible embodiment, the size of the pin in the second pair of pins is three times the first preset required size.

In a possible embodiment, the size of the pin in the second pair of pins is greater than three times the first preset required size.

In the second aspect, this application provides a chip framework, including:

The frame body, the first pin area and the second pin area;

The first pin area and the second pin area are arranged oppositely on the frame body;

Wherein, the second pin area includes at least one second pin pair, and the size of the pins in the second pin pair is larger than the first preset required size.

In a possible embodiment, the size of the pin in the second pair of pins is three times the first preset required size.

In a possible embodiment, the size of the pin in the second pair of pins is greater than three times the first preset required size.

In a possible embodiment, the first pin area includes a plurality of first pin pairs, and the size of the pins in the first pin pairs is larger than the second preset required size.

In a possible embodiment, the first pin area further includes: at least one third pin pair, the pins in the third pin pair are larger in size than the pins in the first pin pair. Foot size.

In a possible embodiment, the second preset required size is smaller than the first preset required size.

In a third aspect, this application also provides a packaged chip, including: a chip and a frame as described in any one of the second aspects; the chip is packaged on the frame.

Beneficial effects:

In the above-mentioned chip packaging method provided by the present application, the present application obtains at least one second pin pair by processing the second pin area of the frame, and the size of the pin in the second pin pair is larger than that of the first predetermined pin. Set the required size; then package the chip on the frame. This application can enhance the strength of the lead frame and reduce the risk of deformation by designing the size of the pins to be larger than the required size when designing the lead frame; in addition, the pins are designed with an oversized size, so during production, it is necessary to Use a cutting die to cut off the excess part. In this way, by modifying the position and size of the cutting die and processing the same set of lead frames, products with different pin sizes and positions can be produced. When the pin position and size need to be changed, it only needs to be modified to cut off the mold, which greatly reduces development time and costs.

Description of the drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, further serve to explain the principles of the disclosure and enable any person skilled in the relevant art to make and use the disclosure.

Figure 1 is a schematic design diagram of a frame in the prior art;

Figure 2 is a schematic design diagram of a framework provided by an embodiment of the present application;

Figure 3 is a schematic diagram comparing the connection area of the frame provided by the present application and the frame in the prior art;

Figure 4 is a schematic diagram of the cutting process of the frame shown in Figure 2 in a cutting die;

Figure 5 is a structural schematic diagram of a frame in the frame design diagram shown in Figure 2;

Figure 6 is another structural schematic diagram of the frame shown in Figure 5;

Figure 7 is another structural schematic diagram of the frame shown in Figure 5;

Figure 8 is another structural schematic diagram of the frame shown in Figure 5;

Figure 9 is another structural schematic diagram of the frame shown in Figure 5;

FIG. 10 is a schematic flowchart of a chip packaging method provided by an embodiment of the present application.

As shown in the figures, in order to clearly realize the structure of the embodiments of the present invention, specific structures and devices are marked in the figures, but this is only for illustration and is not intended to limit the present invention to the specific structures, devices and environments. , according to specific needs, those of ordinary skill in the art can adjust or modify these devices and environments, and the adjustments or modifications made are still included in the scope of the appended claims.

Detailed ways

The chip packaging method provided by the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. At the same time, it is explained here that in order to make the embodiments more detailed, the following embodiments are the best and preferred embodiments. For some well-known technologies, those skilled in the art can also adopt other alternative ways to implement them; and the drawings It is only for the purpose of describing the embodiments more specifically, and is not intended to specifically limit the present invention.

Example

As shown in Figure 1, the lead frame is designed for similar products currently on the market. Among them, the connecting ribs 1 between the frames become pins after being broken. If the frame is designed according to the width of the finished pins, the width will be too small, resulting in low frame strength. If the terminal wants to modify the position of the upper board, the lead frame and corresponding mold design must be modified. Therefore, additional mold costs will be incurred, and the production of new molds will also take up a considerable amount of time, resulting in low development efficiency. And the frame strength is low and easy to deform.

In order to overcome the above problems, the present application provides a chip frame 100. Please refer to FIGS. 2 to 9. The chip frame 100 includes: a frame body 110, a first pin area 120 and a second pin area 130.

Wherein, the first pin area 120 and the second pin area 130 are arranged oppositely on the frame body 110;

Wherein, the second pin area 130 includes at least one second pin pair.

One pin pair includes two pins, that is, the second pin pair includes two second pins 131; the size of the second pins 131 is larger than the first preset required size.

It should be understood that the first preset required size is the required size provided by the developer (or user) during the design and development of the framework 100, and this application does not limit the specific size.

As shown in FIG. 4 , the second pin 131 can be cut using the rectangular mold shown in the middle view of FIG. 4 .

It should be understood that the cutting mold in Figure 4 is only an example and not a limitation.

Optionally, the size of the pin in the second pair of pins is three times the first preset required size. That is, the size of the second pin 131 is three times the first preset required size.

As another implementation manner, the size of the pin in the second pair of pins is greater than three times the first preset required size. That is, the size of the second pin 131 is greater than three times the first preset required size.

For example, as shown in Figure 1-6, since the size of the second pin 131 is enlarged, it can be cut into different shapes according to actual needs during actual use. The specific shape is not specified here. limited.

It can be understood that by enlarging the size of the second pin 131 to three times or more (length and width) of the first preset required size, the pin is cut and formed by cutting the mold. When the position of the second pin 131 is changed, it only needs to be modified to cut off the mold. On the one hand, it can enhance the strength of the lead frame and reduce the risk of deformation. On the other hand, it can greatly reduce development time and costs.

Optionally, as shown in FIG. 5 , the first pin area 120 includes a plurality of first pin pairs, and the size of the pins in the first pin pairs is larger than the second preset required size.

Wherein, one first pin pair includes two first pins 121, that is, the size of the first pins 121 is larger than the second preset required size.

Wherein, the second preset required size is smaller than the first preset required size.

In a possible embodiment, as shown in FIG. 7 , the first pin area 120 further includes: at least one third pin pair, the size of the pin in the third pin pair is larger than that of the third pin pair. The size of the pins in a pin pair.

Among them, a third pin pair includes two third pins 123 , that is, the third pin 123 is larger in size than the first pin 121 .

It should be noted that the shape of each pin in Figures 2 to 9 of this application is not used to limit the protection scope of the frame 100, but is only used as an example.

That is to say, the shapes of the first pin 121, the third pin 123 and the second pin 131 in this application can also be other shapes than those shown in the drawings of this application.

It can be understood that in this embodiment, by designing the size of the pins (such as the first pin 121, the third pin 123, and the second pin 131) to be larger than the required size when designing the frame 100 of the chip, the lead frame can be enhanced. 100 strength to reduce the risk of deformation; in addition, the pins are designed with an oversized size, so during production, a cutting die needs to be used to cut off the excess part. In this way, by modifying the position and size of the cutting die , by processing the same set of lead frames 100, products with different pin sizes and positions can be produced. When the pin position and size need to be changed, it only needs to be modified to cut off the mold, which greatly reduces development time and costs.

It can be understood that, as shown in FIG. 3 , with the frame 100 designed in this application, the connection area is significantly larger than that of the existing design, which can increase the strength here and reduce the risk of lead frame deformation.

Based on the same inventive concept, as shown in Figure 10, this application also provides a chip packaging method, which specifically includes the following steps:

Step S201, provide a frame, the frame including a first pin area and a second pin area arranged oppositely;

Step S202, process the second pin area to obtain at least one second pin pair, the size of the pin in the second pin pair is larger than the first preset required size;

Step S203: Provide a chip and package the chip on the frame.

In a possible embodiment, the chip packaging method further includes:

The first pin area is processed to obtain a plurality of first pin pairs, and the size of the pins in the first pin pairs is larger than the second preset required size.

In a possible embodiment, the chip packaging method further includes:

The first pin area is processed to obtain a plurality of first pin pairs and at least one third pin pair. The size of the pins in the first pin pair and the third pin pair is greater than Second preset required size.

It should be noted that for the specific implementation of this method embodiment, please refer to the foregoing description, which will not be described again here.

Based on the same inventive concept, this application also provides a packaged chip, including: a chip and a frame; the chip is packaged on the frame.

It should be understood that the term "and/or" in this article is only an association relationship describing related objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A alone exists, and A and B exist simultaneously. , there are three cases of B alone, where A and B can be singular or plural. In addition, the character "/" in this article generally indicates that the related objects are an "or" relationship, but it may also indicate an "and/or" relationship. For details, please refer to the previous and later contexts for understanding.

In this application, "at least one" refers to one or more, and "plurality" refers to two or more. "At least one of the following" or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items). For example, at least one of a, b, or c can mean: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple .

It should be understood that in the various embodiments of the present application, the size of the sequence numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its functions and internal logic, and should not be used in the embodiments of the present application. The implementation process constitutes any limitation.

The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be made. regarded as the protection scope of the present invention.

Claims (10)

1. A method of packaging a chip, the method comprising:

providing a frame, wherein the frame comprises a first pin area and a second pin area which are oppositely arranged;

processing the second pin area to obtain at least one second pin pair, wherein the size of a pin in the second pin pair is larger than a first preset required size;

a chip is provided and packaged on the frame.

2. The method according to claim 1, wherein the method further comprises:

and processing the first pin area to obtain a plurality of first pin pairs, wherein the sizes of the pins in the first pin pairs are larger than a second preset required size.

3. The method according to claim 2, wherein the method further comprises:

and processing the first pin area to obtain a plurality of first pin pairs and at least one third pin pair, wherein the sizes of the pins in the first pin pairs and the third pin pairs are larger than a second preset required size.

4. A method according to claim 3, wherein the size of the pins in the third pin pair is larger than the size of the pins in the first pin pair.

5. The method of claim 1, wherein the size of the pins in the second pin pair is three times the first preset desired size.

6. The method of claim 1, wherein the size of the pins in the second pair of pins is greater than three times the first predetermined desired size.

7. A frame for a chip, comprising:

the frame body, the first pin area and the second pin area;

the first pin area and the second pin area are oppositely arranged on the frame body;

the second pin area comprises at least one second pin pair, and the size of a pin in the second pin pair is larger than the first preset required size.

8. The frame of a chip as claimed in claim 7, wherein,

the size of the pins in the second pin pair is three times the first preset required size.

9. The die frame of claim 7, wherein the size of the pins in the second pair of pins is greater than three times the first predetermined desired size.

10. The die frame of claim 7, wherein the first pin field includes a plurality of first pin pairs, the pins in the first pin pairs having a size greater than a second predetermined desired size.