CN117254806B - Analog-to-digital converter and reference voltage providing circuit and processor thereof - Google Patents
Analog-to-digital converter and reference voltage providing circuit and processor thereof Download PDFInfo
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- CN117254806B CN117254806B CN202311264483.1A CN202311264483A CN117254806B CN 117254806 B CN117254806 B CN 117254806B CN 202311264483 A CN202311264483 A CN 202311264483A CN 117254806 B CN117254806 B CN 117254806B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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Abstract
The invention discloses an analog-to-digital converter, a reference voltage providing circuit and a processor thereof, wherein the reference voltage providing circuit comprises a voltage providing unit, a buffer unit and a switching unit, wherein the voltage providing unit is suitable for providing a first reference voltage, the buffer unit is suitable for buffering the first reference voltage and outputting a second reference voltage, and the switching unit is configured to switch the second reference voltage to provide charges for an ADC sampling channel of the analog-to-digital converter when a high-order capacitance group of the analog-to-digital converter is switched, and switch the first reference voltage to provide charges for the ADC sampling channel of the analog-to-digital converter when a low-order capacitance group of the analog-to-digital converter is switched. The circuit does not cause the voltage on the off-chip capacitor to be greatly reduced, so that the accuracy of the ADC is not reduced.
Description
Technical Field
The present application relates to the field of analog-to-digital converters, and in particular, to an analog-to-digital converter, a reference voltage providing circuit thereof, and a processor.
Background
The ADC (Analog to Digital Converter, analog-to-digital converter), especially the SAR ADC (Successive-Approximation REGISTER ADC, successive approximation analog-to-digital converter), has very wide application in industry, measurement, automobile, etc. due to its low power consumption, high speed, high accuracy.
The SAR ADC realizes the quantification of input voltage through capacitance switching, and in the capacitance switching process, the reference voltage needs to be accurate enough to ensure the accuracy of successive approximation of the SAR ADC. However, during each capacitor switching process, a disturbance is caused to the reference voltage, so in practical application, a high-precision ADC circuit usually needs to use an off-chip capacitor (on the order of 10 uF), and when the capacitors are switched, transient charges are provided, and the reference voltage providing circuit provides an average current. When the capacitor is switched, the voltage on the off-chip capacitor drops, and the reference voltage supply circuit needs a long time to supplement charges to the off-chip capacitor, so that the reference voltage drops, and the accuracy of the ADC is reduced.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. Therefore, a first object of the present invention is to provide a reference voltage supply circuit of an analog-to-digital converter, in which each ADC sampling channel is provided with a redundant bit capacitor, so that the reference voltage does not need to be very accurate, and when the high-order capacitor bank is switched, the buffer unit supplies charges to the ADC sampling channels, and when the low-order capacitor bank is switched, the first reference voltage supplies charges to the ADC sampling channels, so that the voltage on the off-chip capacitor is not greatly reduced, and thus the accuracy of the ADC is not reduced.
A second object of the present invention is to provide an analog-to-digital converter.
A third object of the invention is to propose a processor.
To achieve the above object, according to a first aspect of the present invention, a reference voltage providing circuit of an analog-to-digital converter includes a voltage providing unit adapted to provide a first reference voltage, a buffer unit adapted to buffer the first reference voltage and output a second reference voltage, and a switching unit configured to switch the second reference voltage to provide charges to an ADC sampling channel of the analog-to-digital converter when a high-order capacitor bank of the analog-to-digital converter is switched, and switch the first reference voltage to provide charges to the ADC sampling channel of the analog-to-digital converter when a low-order capacitor bank of the analog-to-digital converter is switched.
The reference voltage supply circuit of the analog-to-digital converter comprises a voltage supply unit, a buffer unit and a switching unit, wherein the switching unit is configured to switch the second reference voltage to supply charges to the ADC sampling channel of the analog-to-digital converter when the high-order capacitance group of the analog-to-digital converter is switched, and to switch the first reference voltage to supply charges to the ADC sampling channel of the analog-to-digital converter when the low-order capacitance group of the analog-to-digital converter is switched. Therefore, since each ADC sampling channel is provided with a redundant bit capacitor, the reference voltage does not need to be very accurate when the high-order capacitor bank is switched, and the buffer unit provides charges to the ADC sampling channels, and when the low-order capacitor bank is switched, the first reference voltage provides charges to the ADC sampling channels, and since the capacitance of the low-order capacitor bank is smaller, the charges required by the low-order capacitor bank are less, and the voltage on the off-chip capacitor is not greatly reduced, so that the accuracy of the ADC is not reduced.
According to one embodiment of the invention, the switching unit comprises a first switching switch and a second switching switch, wherein a first end of the first switching switch is connected with an output end of the buffer unit, a first end of the second switching switch is connected with an output end of the voltage supply unit, a second end of the first switching switch is connected with a second end of the second switching switch to form a first node, and the first node is an output end of the reference voltage supply circuit.
According to one embodiment of the invention, the second reference voltage provides charge to the ADC sampling channel when the first switch is closed and the second switch is open, and the first reference voltage provides charge to the ADC sampling channel when the first switch is open and the second switch is closed.
According to one embodiment of the invention, the buffer unit comprises a buffer, a first input end of the buffer is connected with the output end of the voltage supply unit, a second input end of the buffer is connected with the output end of the buffer, and the output end of the buffer is used as the output end of the buffer unit.
According to one embodiment of the invention, the voltage providing unit comprises a band gap reference, a first resistor, an off-chip capacitor and a voltage providing unit, wherein one end of the first resistor is connected with the band gap reference, one end of the off-chip capacitor is grounded, and the other end of the off-chip capacitor is connected with the other end of the first resistor and serves as an output end of the voltage providing unit.
According to an embodiment of the present invention, when the number of ADC sampling channels is plural, the number of switching units and the number of buffer units are plural, respectively, and each ADC sampling channel corresponds to one switching unit and one buffer unit.
According to one embodiment of the invention, the bandgap reference, the first resistor, each switching unit and each buffer unit are integrated in the chip of the analog-to-digital converter, respectively.
According to one embodiment of the present invention, the analog-to-digital converter further includes an auxiliary ADC sampling channel, the auxiliary ADC sampling channel is correspondingly provided with an auxiliary capacitor array, and after the auxiliary ADC sampling channel obtains a comparison result based on capacitance switching of the auxiliary capacitor array, the comparison result is loaded into the ADC sampling channel to be used as a high-order comparison result of the ADC sampling channel.
According to one embodiment of the invention, the second reference voltage provides charge to the ADC sampling channel during loading of the comparison result by the auxiliary ADC sampling channel to the ADC sampling channel.
According to one embodiment of the invention, the capacitance of the auxiliary capacitance array is smaller than the capacitance of the capacitance array of the analog-to-digital converter.
According to one embodiment of the present invention, the capacitance of the redundant capacitor of the analog-to-digital converter is between the last capacitor capacitance of the high-order capacitor bank and the first capacitor capacitance of the low-order capacitor bank.
To achieve the above object, according to a second aspect of the present invention, an analog-to-digital converter is provided, which includes the reference voltage providing circuit of any one of the foregoing embodiments.
According to the analog-to-digital converter of the embodiment of the invention, by adopting the reference voltage supply circuit, since each ADC sampling channel is provided with the redundant bit capacitor, the reference voltage does not need to be very accurate, when the high-order capacitor bank is switched, the buffer unit supplies charges to the ADC sampling channels, and when the low-order capacitor bank is switched, the first reference voltage supplies charges to the ADC sampling channels, so that the voltage on the off-chip capacitor is not greatly reduced, and the accuracy of the ADC is not reduced.
To achieve the above object, an embodiment of the present invention provides a processor including the aforementioned analog-to-digital converter.
According to the processor provided by the embodiment of the invention, by adopting the analog-to-digital converter, since each ADC sampling channel is provided with the redundant bit capacitor, the reference voltage is not required to be very accurate, when the high-order capacitor bank is switched, the buffer unit supplies charges to the ADC sampling channels, and when the low-order capacitor bank is switched, the first reference voltage supplies charges to the ADC sampling channels, so that the voltage on the off-chip capacitor is not greatly reduced, and the accuracy of the ADC is not reduced.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a circuit diagram of a SAR ADC in the related art;
FIG. 2 is a schematic voltage diagram of the upper plate of the capacitive array of the SAR ADC in the related art;
FIG. 3 is a circuit diagram of a reference voltage circuit of a SAR ADC in the related art;
FIG. 4 is a graph of the voltage across the off-chip capacitor of a SAR ADC in the related art;
fig. 5 is a schematic diagram of ringing of a SAR ADC in the related art;
FIG. 6 is a circuit diagram of an analog to digital converter according to one embodiment of the invention;
FIG. 7 is a schematic diagram of a reference voltage supply circuit according to one embodiment of the invention;
FIG. 8 is a circuit diagram of a buffer unit and a switching unit according to one embodiment of the present invention;
fig. 9 is a schematic diagram of a structure of a voltage supply unit and a plurality of ADC sampling channels according to one embodiment of the invention;
FIG. 10 is a circuit diagram of an auxiliary ADC sampling channel according to one embodiment of the invention;
FIG. 11 is a circuit diagram of an auxiliary ADC sampling channel and ADC sampling channel in accordance with one embodiment of the present invention;
FIG. 12 is a system diagram of an analog-to-digital converter according to one embodiment of the invention;
FIG. 13 is a system diagram of a processor according to one embodiment of the invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
The present application has been made in view of the following problems:
As shown in fig. 1, the SAR ADC includes a capacitor array 10, where a capacitor c1:c2:c3 in the capacitor array 10 is equal to or greater than cn=1024:512:256 is equal to or greater than about 1, a lower plate of the capacitor array 10 is connected to a reference voltage vref or ground gnd, and each capacitor in the capacitor array 10 is switched to be connected to the reference voltage vref or ground gnd, so that the voltage of an upper plate of the capacitor array 10 changes as shown in fig. 2, where MSB (Most Significant Bit ) is the most significant capacitor, i.e., capacitor C1, MSB-1 is the next-highest capacitor, i.e., capacitor C2, and so on, thereby generating a quantization result.
Therefore, in the capacitive switching process, the reference voltage vref needs to be accurate enough to ensure the accuracy of the successive approximation of the SAR ADC. In practical applications, each capacitor switches to a disturbance of the reference voltage vref, which normally needs to be recovered in the next beat of comparison, for example, in a voltage range of 1lsb in 10ns, and for a 16bit ADC, taking the reference voltage vref of 4.4V as an example, the reference voltage vref needs to be recovered to 4.4V/2 16 =67 uV in 10 ns. Currently, few amplifiers are able to reach such high bandwidths (or the power consumption needs to be very large) that the reference voltage vref voltage builds up to a sufficient accuracy on the order of 10 ns.
Therefore, in practical applications, as shown in fig. 3, an off-chip capacitor C (on the order of 10 uF) is generally required to provide transient charge during capacitor switching, and a reference voltage circuit 40, typically a buffer, provides an average current, whose output impedance R needs to be small enough to avoid slow recovery of the reference voltage during successive approximation conversion.
Although off-chip capacitor C may provide a transient current during successive approximation, the capacitance value of off-chip capacitor C may not be infinite due to the fact that it is not. In the successive approximation ADC, the capacitance of the high-order capacitor is relatively large, so that more transient current is pumped from the off-chip capacitor C during the switching process of the high-order capacitor, resulting in a drop in the voltage on the capacitor. The buffer bandwidth in the reference voltage circuit 40 is limited, and the output impedance R cannot be infinitely small, so that a long time is required to charge the off-chip capacitor C.
Assuming that the capacitance switched by the ADC is c_adc, after the switching is completed, the voltage VC across the off-chip capacitor C is calculated according to the following formula (1):
As shown in fig. 4, assuming that the off-chip capacitor C is 10uF, if the capacitance of the MSB (i.e., the capacitance C1) is 20pF, when the first capacitance C1 is switched, c_adc=20 pF, and the voltage VC across the off-chip capacitor C will drop to 99.9998% of the reference voltage vref. For the multiple ADC sampling channels 100 switched at the same time, the voltage VC at two ends of the off-chip capacitor C will drop more proportionally, and the multiple ADC sampling channels 100 will have different channel connections with different input signals vin and different drop conditions of the voltage VC at two ends of the off-chip capacitor C due to different flip conditions of the highest-order capacitor, so that the different channels will interfere with each other due to the change of the voltage VC at two ends of the off-chip capacitor C, and the gain error on each channel is different due to the fact that the wiring from each channel to the off-chip capacitor C is different.
In addition, since the off-chip capacitor C is connected to the chip, there is a parasitic capacitance effect caused by chip routing, when the capacitor is switched, the on-chip voltage will generate ringing as shown in fig. 5, the larger the switched capacitor is, the larger the ringing amplitude is, and the longer the time required for stabilization is.
Accordingly, in the related art, a reference voltage circuit of the SAR ADC provides a transient charge using an off-chip capacitor, and the reference voltage circuit provides an average current. The voltage on the off-chip capacitor is reduced when the capacitor is switched, the bandwidth of the reference voltage circuit is smaller, the off-chip capacitor can be supplemented for a long time, the accuracy of the final ADC is reduced, and the voltage in the high-order capacitor is also ringing when the capacitor is switched, and the accuracy of the ADC is reduced. When the ADC has multiple channels, interference between channels occurs due to gain error of each channel.
Based on this, the embodiment of the invention provides an analog-to-digital converter, a reference voltage providing circuit and a processor thereof, because each ADC sampling channel is provided with a redundant bit capacitor, the reference voltage does not need to be very accurate, when a high-order capacitor bank is switched, a buffer unit provides charges for the ADC sampling channel, and when a low-order capacitor bank is switched, a first reference voltage provides charges for the ADC sampling channel, so that the voltage on an off-chip capacitor is not greatly reduced, and the accuracy of the ADC is not reduced.
The analog-to-digital converter and the reference voltage providing circuit and the processor thereof according to the embodiments of the present invention are described below with reference to the accompanying drawings.
Fig. 6 is a circuit diagram of an analog-to-digital converter according to one embodiment of the invention. As shown in fig. 6, the analog-to-digital converter includes at least one ADC sampling channel 100, and each ADC sampling channel 100 is correspondingly provided with a capacitor array 10 and a redundant bit capacitor Cr, where the redundant bit capacitor Cr is adapted to divide the capacitor array 10 into a high-order capacitor group 11 and a low-order capacitor group 12.
Specifically, the ratio of the capacitors in the capacitor array 10 is 2, as shown in fig. 6, a redundancy bit capacitor Cr is added between the fifth capacitor C5 and the sixth capacitor C6, the upper plates of the capacitor array 10 and the redundancy bit capacitor Cr are connected to the positive input terminal of the comparator 20, the upper plates of the capacitor array 10 and the redundancy bit capacitor Cr are connected to the reference voltage vref or the ground gnd, and the capacitors C1-C5 of the high-order capacitor bank 11 are also suitable for being connected to the input signal vin. The negative input of the comparator 20 is adapted to input a common mode voltage vcm, the positive and negative input of the comparator 20 are provided with switches S, and the output of the comparator 20 is connected to the control unit 30. The control unit 30 is configured to switch the capacitances C1-Cn in the capacitor array 10 and the redundancy bit capacitance Cr to be connected to the reference voltage vref or to ground gnd so as to vary the voltage of the upper plate of the capacitor array 10.
In the sampling phase, the switch S is closed, the capacitors C1-C5 of the high-order capacitor bank 11 are connected with the input signal vin, and the rest of the capacitors are grounded gnd. In the case of sampling, the sampling method is not limited to that shown in fig. 6, and all the capacitors C1 to Cn in the capacitor array 10 may be connected to the input signal vin. After the sampling is completed, the switch S is turned off, and the connection between the capacitance of the high-order capacitance group 11 and the input signal vin is disconnected.
In the conversion phase, the lower plate of the capacitor of the MSB (i.e. the capacitor C1) is first connected to the reference voltage vref, the lower plates of the remaining capacitors are grounded gnd, the voltage of the upper plate of the capacitor array 10 is vcm-vin+vref/2, the voltage of the positive input terminal of the comparator 20 is vcm-vin+vref/2, the voltage of the negative input terminal of the comparator 20 is vcm, if vcm-vin+vref/2-vcm >0, the output result of the comparator 20 is1, the control unit 30 switches the lower plate of the capacitor of the MSB (i.e. the capacitor C1) to the ground gnd, so that the first bit is 0, and the output result of the comparator 20 is 0 if vcm-vin+vref/2-vcm is less than 0, and the control unit 30 keeps the lower plate of the capacitor of the MSB (i.e. the capacitor C1) connected to the reference voltage vref, so that the first bit is 1.
The lower plate of the capacitor of MSB-1 (i.e. capacitor C2) is then connected to the reference voltage vref, if the lower plate of the capacitor of MSB (i.e. capacitor C1) is grounded gnd, the voltage of the upper plate of the capacitor array 10 is Vcm-vin+vref/4, the voltage of the negative input terminal of the comparator 20 is Vcm, if Vcm-vin+vref/4-Vcm >0, the output of the comparator 20 is 1, the control unit 30 switches the lower plate of the capacitor of MSB-1 (i.e. capacitor C2) to ground gnd so that the second bit is 0, if Vcm-vin+vref/4-Vcm is less than or equal to 0, the output of the comparator 20 is 0, and the control unit 30 keeps the lower plate of the capacitor of MSB-1 (i.e. capacitor C2) connected to the reference voltage vref so that the second bit is 0. If the lower plate of the capacitor of MSB (i.e. capacitor C1) is connected to the reference voltage vref, the voltage of the upper plate of the capacitor array 10 is vcm-vin+vref/2+vref/4, the voltage of the negative input terminal of the comparator 20 is vcm, if vcm-vin+vref/2+vref/4-vcm >0, the output of the comparator 20 is 1, the control unit 30 switches the lower plate of the capacitor of MSB-1 (i.e. capacitor C2) to ground gnd, and thus the second bit is 0, and if vcm-vin+vref/2+vref/4-vcm is 0, the output of the comparator 20 is 0, and the control unit 30 keeps the lower plate of the capacitor of MSB-1 (i.e. capacitor C2) connected to the reference voltage vref, and thus the second bit is 0. The comparison of the latter capacitance is the same as the comparison of the capacitance of the MSB (i.e. capacitance C1) and the capacitance of the MSB-1 (i.e. capacitance C2), and will not be described again here.
The redundant bit capacitor Cr is added to the ADC sampling channel 100, so that the ratio of the capacitors in the capacitor array 10 is less than 2, and after the redundant bit capacitor Cr is added, if a problem occurs in the conversion process of the high-order capacitor bank 11, the redundant bit capacitor Cr can remedy the result to obtain a correct output.
For example, taking the capacitor array 10 without the redundant bit capacitor Cr, and the capacitor array 10 with four capacitors as an example, the weights of the four capacitors are 8, 4, 2, and 1, if the digital code output by the control unit 30 according to the comparison result of the comparator 20 is 1000, the digital code is recovered to have a value of 1×8+0×4+0×2+0×1=8 after digital conversion, when the first bit digital code is wrong, the output digital code is changed to 0111, and the digital code is recovered to have a value of 0×8+1×4+1×2+1×1=7 after digital conversion, so that the digital code after digital conversion differs by 1, and the result output by the control unit 30 is wrong. In the capacitor array 10, there is a redundant bit capacitor Cr, the redundant bit capacitor Cr is located between the second capacitor C2 and the third capacitor C3, and when the capacitance value of the redundant bit capacitor Cr is the second capacitor C2, the weights of the five capacitors are 8, 4, 2, and 1, when no error occurs in the conversion process, the digital code output by the control unit 30 is 10000, the digital code is restored to the value of 1×8+0×4+0×4+0×2+0×1=8 after the digital conversion, and when the first digital code is in error, the output digital code is 01111, and the digital code is restored to the value of 0×8+1×4+1×4+0×2+1=8 after the digital conversion, so that the digital code is the same, and the control unit 30 can obtain a correct result.
It should be noted that the positions of the redundant bit capacitors Cr are not limited to the positions between the fifth capacitor C5 and the sixth capacitor C6 shown in fig. 6, but may be other capacitors, the number of the redundant bit capacitors Cr is not limited to one, and may be plural, and the plural redundant bit capacitors Cr are respectively located at different positions, for example, two redundant bit capacitors Cr are provided, one of which is located between the fifth capacitor C5 and the sixth capacitor C6, and the other of which is located between the n-1 capacitor Cn-1 and the n-th capacitor Cn. The larger the number of redundant bit capacitors Cr in the capacitor array 10 is, the larger the redundancy amount of the ADC is, and the larger the fault tolerance amount is, which can be set according to practical situations. After adding the redundant bit capacitor Cr, the weights of the capacitor array 10 and the redundant bit capacitor Cr are not limited to binary, but may be other values, and are not limited thereto.
In the above embodiment, after adding the redundant bit capacitor, a different digital code exists in one digital value, so as to realize the effect of error correction, so that the reference voltage does not need to be very accurate when the capacitor in the high-order capacitor group is switched after adding the redundant bit capacitor.
Fig. 7 is a schematic diagram of a reference voltage supply circuit according to an embodiment of the present invention. As shown in fig. 7, the reference voltage supply circuit 200 includes a voltage supply unit 50, a buffer unit 60, and a switching unit 70.
The voltage providing unit 50 is adapted to provide a first reference voltage vref1, the buffer unit 60 is adapted to buffer the first reference voltage vref1 and output a second reference voltage vref2, and the switching unit 70 is configured to switch the second reference voltage vref2 to provide charge to the ADC sampling channel 100 of the analog-to-digital converter when the high-order capacitor bank 11 of the analog-to-digital converter is switched and to switch the first reference voltage vref1 to provide charge to the ADC sampling channel 100 of the analog-to-digital converter when the low-order capacitor bank 12 of the analog-to-digital converter is switched.
Specifically, the buffer unit 60 may also provide charges to the ADC sampling channel 100, but the bandwidth of the buffer unit 60 is limited, and the charges provided by the buffer unit 60 cannot meet the actual requirements of the ADC sampling channel 100, so the reference voltage vref will change when the charges are provided by the buffer unit 60. However, since the redundant bit capacitor Cr is disposed in the capacitor array 10, the reference voltage vref is not required to be very accurate when the capacitors in the high-order capacitor bank 11 are switched, and thus the second reference voltage vref2 can be switched to provide charges to the ADC sampling channel 100. When the low-order capacitor set 12 is switched, there is no redundant capacitor Cr, so that an accurate reference voltage vref is required, so that the first reference voltage vref1 is switched to provide charges to the ADC sampling channel 100, however, the low-order capacitor set 12 has smaller capacitance, so that the low-order capacitor set 12 needs less charges, and the voltage on the off-chip capacitor C is not greatly reduced.
It should be noted that, when the redundancy bit capacitor Cr is switched, the switching unit 70 switches the first reference voltage vref1 to provide the charge to the ADC sampling channel 100.
For example, taking the example shown in fig. 6 as an example, if the redundancy bit capacitance Cr is equal to the fifth capacitance C5, the switching unit 70 switches the second reference voltage vref2 to provide charges to the ADC sampling channel 100 during the switching of the first capacitance C1-the fifth capacitance C5 in the conversion stage. The lower plate of the capacitor of the MSB (i.e. capacitor C1) is first connected to the second reference voltage vref2, the lower plates of the remaining capacitors are grounded gnd, the voltage of the upper plate of the capacitor array 10 is vcm-vin+vref/2, the voltage of the positive input terminal of the comparator 20 is vcm-vin+vref/2, the voltage of the negative input terminal of the comparator 20 is vcm, if vcm-vin+vref/2-vcm >0, the output result of the comparator 20 is 1, the control unit 30 switches the lower plate of the capacitor of the MSB (i.e. capacitor C1) to ground gnd so that the first bit is 0, if vcm-vin+vref/2-vcm is less than or equal to 0, the output result of the comparator 20 is 0, and the control unit 30 keeps the lower plate of the capacitor of the MSB (i.e. capacitor C1) connected to the second reference voltage vref2 so that the first bit is 1. The switching process of the second capacitor C5 to the fifth capacitor is similar to the switching process of the first capacitor C1, and will not be described here again.
When the redundancy bit capacitor Cr and the capacitors in the low-order capacitor set 12 are switched, the switching unit 70 switches the first reference voltage vref1 to provide charges to the ADC sampling channel 100. Firstly, the lower plate of the capacitor of MSB (i.e. the capacitor C1) is connected to the first reference voltage vref1, the lower plates of the other capacitors are grounded, the voltage of the upper plate of the capacitor array 10 is vref/2 5 added on the basis of the voltage compared by the fifth capacitor C5, if the output result of the comparator 20 is 1, the control unit 30 switches the lower plate of the redundant bit capacitor Cr to the ground gnd, if the output result of the comparator 20 is 0, the control unit 30 keeps the lower plate of the redundant bit capacitor Cr connected to the first reference voltage vref1, and the switching process is similar to that of the redundant bit capacitor Cr, which is not repeated here.
In the above embodiment, since each ADC sampling channel is provided with a redundant bit capacitor, the reference voltage does not need to be very accurate when the high-order capacitor bank is switched, the second reference voltage provides charges to the ADC sampling channel, and the first reference voltage provides charges to the ADC sampling channel when the low-order capacitor bank is switched, and since the capacitance of the low-order capacitor bank is small, the charges required by the low-order capacitor bank are small, and the voltage on the off-chip capacitor is not greatly reduced, and therefore the accuracy of the ADC is not reduced.
In some embodiments, as shown in FIG. 8, the switching unit 70 includes a first switching switch SW1 and a second switching switch SW2, a first terminal of the first switching switch SW1 is connected to the output terminal of the buffer unit 60, a first terminal of the second switching switch SW2 is connected to the output terminal of the voltage providing unit 50, and a second terminal of the first switching switch SW1 is connected to a second terminal of the second switching switch SW2 to form a first node J1, the first node J1 being the output terminal of the reference voltage providing circuit 200.
It is understood that the switching unit 70 may change the states of the first and second switching switches SW1 and SW2 according to the comparison process, thereby switching the first reference voltage vref1 or the second reference voltage vref2 output.
Further, in some embodiments, the second reference voltage vref2 provides charge to the ADC sampling channel 100 when the first switch SW1 is closed and the second switch SW2 is open, and the first reference voltage vref1 provides charge to the ADC sampling channel 100 when the first switch SW1 is open and the second switch SW2 is closed.
Specifically, when the capacitors in the high-order capacitor bank 11 are switched, the first switch SW1 is closed and the second switch SW2 is opened, the output end of the buffer unit 60 is connected to the first node J1, the second reference voltage vref2 provides charges to the ADC sampling channel 100, and when the capacitors in the low-order capacitor bank 12 are switched, the first switch SW1 is opened and the second switch SW2 is closed, the output end of the voltage providing unit 50 is connected to the first node J1, and the first reference voltage vref1 provides charges to the ADC sampling channel 100 to realize an accurate comparison process.
In the above embodiment, by changing the switching states of the first and second switches in the switching unit, the switching buffer unit or the voltage supply unit communicates with the ADC sampling channel, it is achieved that the ADC sampling channel is supplied with charges using different reference voltages.
In some embodiments, as shown in FIG. 8, the buffer unit 60 includes a buffer 61, a first input terminal of the buffer 61 is connected to an output terminal of the voltage supply unit 50, a second input terminal of the buffer 61 is connected to an output terminal of the buffer 61, and an output terminal of the buffer 61 serves as an output terminal of the buffer unit 60.
Specifically, the first input terminal of the buffer 61 is adapted to input the first reference voltage vref1, and the buffer 61 generates the second reference voltage vref2 according to the first reference voltage vref1 and provides the second reference voltage vref2 to the ADC sampling channel 100 when the first switch SW1 is closed and the second switch SW2 is opened.
In some embodiments, as shown in FIG. 9, the voltage providing unit 50 includes a bandgap reference 51, a first resistor R1, and an off-chip capacitor C, wherein one end of the first resistor R1 is connected to the bandgap reference 51, one end of the off-chip capacitor C is grounded gnd, and the other end of the off-chip capacitor C is connected to the other end of the first resistor R1 and serves as an output terminal of the voltage providing unit 50.
Specifically, since the redundancy bit capacitor Cr does not exist behind the low-order capacitor bank 12, when the capacitors in the low-order capacitor bank 12 of the ADC sampling channel 100 are switched, the off-chip capacitor C is still required to provide charges, so as to improve the accuracy of the reference voltage, and the off-chip capacitor C provides charges to the ADC sampling channel 100 when the first switch SW1 is opened and the second switch SW2 is closed.
In the above embodiment, when the capacitors in the high-order capacitor group are switched, the second reference voltage of the buffer unit provides the charge without using the off-chip capacitor, so no ringing occurs, and when the capacitors in the low-order capacitor group are switched, the voltage drop at two ends of the off-chip capacitor is less because the capacitors in the low-order capacitor group are smaller, and the ringing amplitude is also smaller, thereby further improving the accuracy of the ADC.
In some embodiments, as shown in fig. 9, when the ADC sampling channels 100 are plural, the switching unit 70 and the buffer unit 60 are plural, and each ADC sampling channel 100 corresponds to one switching unit 70 and one buffer unit 60.
It can be understood that each ADC sampling channel 100 corresponds to one switching unit 70 and one buffer unit 60, so that when each ADC sampling channel 100 performs capacitive switching, charges provided by the corresponding buffer unit 60 are used, and therefore, mutual interference of the multiple ADC sampling channels 100 does not occur, thereby further improving the accuracy of the ADC.
In some embodiments, as shown in fig. 9, the bandgap reference 51, the first resistor R1, each switching unit 70, and each buffer unit 60 are integrated within a chip 300 of the analog-to-digital converter, respectively.
That is, the remaining circuits are integrated in the chip 300 of the analog-to-digital converter except for the off-chip capacitor C, so that the buffer unit 60 does not generate ringing when the second reference voltage vref2 supplies charges to the ADC sampling channel 100.
In some embodiments, as shown in fig. 10 and 11, the analog-to-digital converter further includes an auxiliary ADC sampling channel 400, where the auxiliary ADC sampling channel 400 is correspondingly provided with the auxiliary capacitor array 80, and after the auxiliary ADC sampling channel 400 obtains a comparison result based on the capacitance switching of the auxiliary capacitor array 80, the comparison result is loaded to the ADC sampling channel 100 to be used as a high-order comparison result of the ADC sampling channel 100.
Specifically, the auxiliary ADC sampling channel 400 is similar to the ADC sampling channel 100 in structure, except that only the high-order capacitances C1s-C5s exist in the auxiliary capacitor array 80 of the auxiliary ADC sampling channel 400, and as shown in fig. 7, the redundant bit capacitance Cr is disposed between the fifth capacitance C5 and the sixth capacitance C6, and therefore, as shown in fig. 10, only 5 capacitances exist in the auxiliary capacitor array 80 as shown in the figure. The auxiliary ADC sampling channel 400 operates in the same manner as the ADC sampling channel 100.
It should be noted that the auxiliary ADC sampling channel 400 also corresponds to one switching unit 60 and one buffer unit 70, so that the auxiliary ADC sampling channel 400 does not interfere with the ADC sampling channel 100 during capacitive switching.
In the sampling stage, the auxiliary ADC sampling channel 400 and the ADC sampling channel 100 perform sampling simultaneously, that is, the switch S of the auxiliary ADC sampling channel 400 and the switch S of the ADC sampling channel 100 are closed simultaneously, the lower plate of the auxiliary capacitor array 80 is connected to the input signal vin, and the capacitors C1-C5 or the capacitor array 10 in the high-order capacitor group 11 in the ADC sampling channel 100 are connected to the input signal vin for sampling. After the sampling is finished, the switch S of the auxiliary ADC sampling channel 400 and the switch S of the ADC sampling channel 100 are simultaneously turned off, the lower plate of the auxiliary capacitor array 80 is disconnected from the input signal vin, and the capacitor C-C5 or the capacitor array 10 in the high-order capacitor bank 11 in the ADC sampling channel 100 is disconnected from the input signal vin.
In the conversion phase, the auxiliary ADC sampling channel 400 operates in the same way as the ADC sampling channel 100. The first switch SW1 of the switching unit 70 is closed and the second switch SW2 is opened, and the second reference voltage vref2 supplies charges to the auxiliary ADC sampling channel 400. The lower plate of the capacitor of the MSB (i.e. the capacitor C1 s) is connected to the second reference voltage vref2 at first, the lower plates of the remaining capacitors C2s-C5s are grounded, the voltage of the upper plate of the auxiliary capacitor array 80 is vcm-vin+vref/2, the voltage of the positive input terminal of the comparator is vcm-vin+vref/2, the voltage of the negative input terminal of the comparator is vcm, if vcm-vin+vref/2-vcm >0, the output result of the comparator is 1, the control unit switches the lower plate of the capacitor of the MSB (i.e. the capacitor C1 s) to the ground gnd, and therefore the first bit is 0, and if vcm-vin+vref/2-vcm is less than or equal to 0, the output result of the comparator is 0, and the control unit keeps the lower plate of the capacitor of the MSB (i.e. the capacitor C1 s) connected to the second reference voltage vref2, and therefore the first bit is 1. The lower plate of the capacitor of MSB-1, i.e. capacitor C2, is then connected to a second reference voltage vref2, if the lower plate of the capacitor of MSB, i.e. capacitor C1, is grounded, the voltage of the upper plate of capacitor array 10 is Vcm-vin+vref/4, the voltage of the negative input of comparator 20 is Vcm, if Vcm-vin+vref/4-Vcm >0, the comparator 20 outputs a result of 1, the control unit 30 switches the lower plate of the capacitor of MSB-1, i.e. capacitor C2, to ground gnd, and thus the second bit is 0, if Vcm-vin+vref/4-Vcm is less than or equal to 0, the comparator 20 outputs a result of 0, and the lower plate of the capacitor of MSB-1, i.e. capacitor C2s, remains connected to the second reference voltage vref2, and thus the second bit is 0. If the lower plate of the capacitor of MSB (i.e. capacitor C1 s) is connected to the second reference voltage vref2, the voltage of the upper plate of the capacitor array 10 is vcm-vin+vref/2+vref/4, the voltage of the negative input terminal of the comparator 20 is vcm, if vcm-vin+vref/2+vref/4-vcm >0, the output of the comparator 20 is 1, the control unit 30 switches the lower plate of the capacitor of MSB-1 (i.e. capacitor C2 s) to ground gnd, and thus the second bit is 0, and if vcm-vin+vref/2+vref/4-vcm is less than or equal to 0, the output of the comparator 20 is 0, and the control unit 30 keeps the lower plate of the capacitor of MSB-1 (i.e. capacitor C2 s) connected to the second reference voltage vref2, and thus the second bit is 0. The comparison of the latter capacitances is the same as the comparison of the capacitance of the MSB (i.e. capacitance C1 s) and the capacitance of the MSB-1 (i.e. capacitance C2 s), and will not be described again here. And so on until all of the capacitances C1s-C5s in the auxiliary capacitance array 80 are switched.
After all the capacitances C1s to C5s in the auxiliary capacitance array 80 are switched, the auxiliary ADC sampling channel 400 loads all the comparison results to the ADC sampling channel 100 as the high-order comparison result of the ADC sampling channel 100. For example, if the comparison result of the auxiliary ADC sampling channel 400 is 10000, the lower plate of the first capacitor C1s of the auxiliary capacitor array 80 is connected to the second reference voltage vref2, the lower plates of the second capacitor C2 s-fifth capacitor C5s are all grounded gnd, the high-order capacitor bank 11 of the ADC sampling channel 100 switches the capacitor connections in the high-order capacitor bank 11 according to the comparison result, the lower plate of the first capacitor C1 is connected to the first reference voltage vref1, and the lower plates of the second capacitor C2-fifth capacitor C5 are all grounded gnd.
The first switch SW1 of the switching unit 70 is opened and the second switch SW2 is closed, and the first reference voltage vref1 supplies charges to the ADC sampling channel 100. The ADC sampling path 100 starts from the redundancy bit capacitance Cr, which is connected to the first reference voltage vref1 at its lower plate, and the lower plate of the capacitance in the low-order capacitance set 12 is grounded gnd. If the output result of the comparator is 1, the control unit switches the lower plate of the redundancy bit capacitor Cr to the ground gnd while connecting the lower plate of the first bit capacitor C6 in the low bit capacitor bank 12 to the first reference voltage vref1 for the next comparison, and if the output result of the comparator is 0, the control unit keeps the lower plate of the redundancy bit capacitor Cr connected to the first reference voltage vref1 while connecting the lower plate of the first bit capacitor C6 in the low bit capacitor bank 12 to the first reference voltage vref1 for the next comparison.
In an alternative embodiment, as shown in fig. 11, the auxiliary ADC sampling channel 400 directly loads the comparison result of the auxiliary capacitor array 80 onto the high-order capacitor bank 11 of the ADC sampling channel 100 to control whether the lower plate of the capacitor in the high-order capacitor bank 11 is connected to the first reference voltage vref1 or to the ground gnd. The auxiliary ADC sampling channel 400 may also send the comparison result to the control unit 30 of the ADC sampling channel 100 through the control unit of the auxiliary ADC sampling channel 400, and the control unit 30 of the ADC sampling channel 100 controls whether the lower plate of the capacitor in the high-order capacitor bank 11 is connected to the first reference voltage vref1 or to the ground gnd according to the comparison result.
In some embodiments, the second reference voltage vref2 provides charge to the ADC sampling channel 100 during the loading of the comparison result by the auxiliary ADC sampling channel 400 to the ADC sampling channel 100.
Specifically, in the process of loading the comparison result to the ADC sampling channel 100 by the auxiliary ADC sampling channel 400, the capacitors in the high-order capacitor bank 11 need to be switched, which affects the voltage VC across the off-chip capacitor C, so that the second reference voltage vref2 is switched to provide the charge to the ADC sampling channel 100. When the voltage VC across the off-chip capacitor C is stable, the first reference voltage vref1 is switched to provide the charge to the ADC sampling channel 100, and the redundant bit capacitor Cr and the low bit capacitor set 12 are smaller, so that a larger voltage drop or severe ringing on the off-chip capacitor is not generated.
In some embodiments, the capacitance of auxiliary capacitance array 80 is less than the capacitance of capacitance array 10 of the analog-to-digital converter.
That is, the capacitance value of the auxiliary capacitance array 80 is small, and thus, the electric charge required for the capacitance of the auxiliary capacitance array 80 at the time of switching is small, and thus, the error of the second reference voltage vref2 is further reduced, thereby further improving the accuracy of the ADC.
In some embodiments, the capacitance of the redundant capacitor Cr of the analog-to-digital converter is between the last capacitor capacitance of the high-order capacitor bank 11 and the first capacitor capacitance of the low-order capacitor bank 12.
It can be appreciated that the larger the value of the redundancy bit capacitance Cr, the larger the redundancy amount. When the capacitance value of the redundant bit capacitor Cr is the last bit capacitor capacitance value in the high bit capacitor group 11, the redundancy amount is the weight corresponding to the last bit capacitor in the high bit capacitor group 11, and when the capacitance value of the redundant bit capacitor Cr is the first bit capacitor capacitance value in the low bit capacitor group 12, the redundancy amount is the weight corresponding to the first bit capacitor in the low bit capacitor group 12.
For example, taking the capacitor array 10 having four capacitors, the redundancy bit capacitor Cr is located between the second capacitor C2 and the third capacitor C3, if the capacitance value of the redundancy bit capacitor Cr is the same as the second capacitor C2, the redundancy amount is 4, and if the capacitance value of the redundancy bit capacitor Cr is the same as the third capacitor C3, the redundancy amount is 2.
In summary, the reference voltage providing circuit of the analog-to-digital converter according to the embodiments of the present invention includes a voltage providing unit, a buffer unit and a switching unit, wherein the switching unit is configured to switch the second reference voltage to provide the charge to the ADC sampling channel of the analog-to-digital converter when the high-order capacitor bank of the analog-to-digital converter is switched, and switch the first reference voltage to provide the charge to the ADC sampling channel of the analog-to-digital converter when the low-order capacitor bank of the analog-to-digital converter is switched. Therefore, since each ADC sampling channel is provided with a redundant bit capacitor, when the high-order capacitor bank is switched, the reference voltage does not need to be very accurate, the buffer unit supplies charges to the ADC sampling channels, when the low-order capacitor bank is switched, the first reference voltage supplies charges to the ADC sampling channels, and the low-order capacitor bank has smaller capacitance, so that the charges required by the low-order capacitor bank are less, the voltage on the off-chip capacitor is not greatly reduced, the precision of the ADC is not reduced, and when the capacitors in the high-order capacitor bank are switched, the second reference voltage supplies charges through the buffer unit, the off-chip capacitor is not used, ringing is not generated, and when the capacitors in the low-order capacitor bank are switched, the voltage drop at two ends of the off-chip capacitor is less because the capacitors in the low-order capacitor bank are smaller, and the ringing amplitude is also smaller, so that the precision of the ADC is further improved. In addition, each ADC sampling channel corresponds to one switching unit and one buffer unit, so that when each ADC sampling channel performs capacitance switching, the charge provided by the corresponding buffer unit is used, and therefore, mutual interference of a plurality of ADC sampling channels does not occur.
Corresponding to the above embodiment, the embodiment of the present invention further provides an analog-to-digital converter. As shown in fig. 12, the analog-to-digital converter 1000 includes the reference voltage supply circuit 200 of any of the foregoing embodiments.
According to the analog-to-digital converter of the embodiment of the invention, by adopting the reference voltage supply circuit, since each ADC sampling channel is provided with the redundant bit capacitor, the reference voltage does not need to be very accurate, when the high-order capacitor bank is switched, the buffer unit supplies charges to the ADC sampling channels, and when the low-order capacitor bank is switched, the first reference voltage supplies charges to the ADC sampling channels, so that the voltage on the off-chip capacitor is not greatly reduced, and the accuracy of the ADC is not reduced.
Corresponding to the above embodiment, the embodiment of the invention also provides a processor. As shown in fig. 13, the processor 2000 includes the aforementioned analog-to-digital converter 1000.
According to the processor provided by the embodiment of the invention, by adopting the analog-to-digital converter, since each ADC sampling channel is provided with the redundant bit capacitor, the reference voltage is not required to be very accurate, when the high-order capacitor bank is switched, the buffer unit supplies charges to the ADC sampling channels, and when the low-order capacitor bank is switched, the first reference voltage supplies charges to the ADC sampling channels, so that the voltage on the off-chip capacitor is not greatly reduced, and the accuracy of the ADC is not reduced.
It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered as a ordered listing of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include an electrical connection (an electronic device) having one or more wires, a portable computer diskette (a magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of techniques known in the art, discrete logic circuits with logic gates for implementing logic functions on data signals, application specific integrated circuits with appropriate combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, as used in embodiments of the present invention, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or as implying any particular number of features in the present embodiment. Thus, a feature of an embodiment of the invention that is defined by terms such as "first," "second," etc., may explicitly or implicitly indicate that at least one such feature is included in the embodiment. In the description of the present invention, the word "plurality" means at least two or more, for example, two, three, four, etc., unless explicitly defined otherwise in the embodiments.
In the present invention, unless explicitly stated or limited otherwise in the examples, the terms "mounted," "connected," and "fixed" as used in the examples should be interpreted broadly, e.g., the connection may be a fixed connection, a removable connection, or an integral, it should be understood that the connection may be a mechanical connection, an electrical connection, or the like, or of course, the connection may be direct, or indirect, through an intermediary, or may be a communication between two elements, or an interaction relationship between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to specific embodiments.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
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| US7408496B2 (en) * | 2006-08-21 | 2008-08-05 | Micron Technology, Inc. | Method, apparatus and system sharing an operational amplifier between two stages of pipelined ADC and/or two channels of signal processing circuitry |
| US8514114B2 (en) * | 2011-06-02 | 2013-08-20 | Analog Devices, Inc. | Measurement method and apparatus for ADC calibration |
| CN103023505B (en) * | 2012-12-18 | 2016-01-20 | 中国科学院微电子研究所 | Analog-digital converter capable of configuring multi-channel successive approximation structure |
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