CN117251266A

CN117251266A - Interrupt event processing method, device, electronic equipment, medium and chip

Info

Publication number: CN117251266A
Application number: CN202311206795.7A
Authority: CN
Inventors: 马俊; 张茜歌; 李政良; 赵豪; 王辰曦; 刘娇健
Original assignee: Beijing Smartchip Microelectronics Technology Co Ltd; Electric Power Research Institute of State Grid Shaanxi Electric Power Co Ltd; State Grid Corp of China SGCC
Current assignee: Beijing Smartchip Microelectronics Technology Co Ltd; Electric Power Research Institute of State Grid Shaanxi Electric Power Co Ltd; State Grid Corp of China SGCC
Priority date: 2023-09-18
Filing date: 2023-09-18
Publication date: 2023-12-19

Abstract

The invention discloses an interrupt event processing method, device, electronic equipment, medium and chip. The method for processing the interrupt event includes: in response to receiving an interrupt request for the first interrupt event, writing the first interrupt context information stored in the base register into the backup register, where the first interrupt context information is used to characterize the first interrupt event. On-site information of the central processing unit when an interrupt event occurs; in response to determining that writing the first interrupt context information stored in the base register to the backup register is completed, processing the first interrupt event; in the process of processing the first interrupt event, The first interrupt context information stored in the backup register is written to the memory in parallel. The invention shortens the interrupt response time and improves the processing efficiency of interrupt events.

Description

Interrupt event processing method and device, electronic equipment, medium and chip

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a method and apparatus for processing an interrupt event, an electronic device, a medium, and a chip.

Background

The interrupt mechanism is one of the basic mechanisms in a computer system, which is a reaction of a central processing unit (Central Processing Unit, CPU) to an event occurring at a certain moment in the system. An event that causes an Interrupt is called an Interrupt Source (Interrupt Source). Typically, the interrupt source is primarily from the peripheral hardware device. The request made by the interrupt source to the CPU is called an interrupt request (Interrupt Request). After receiving the interrupt request from the interrupt source, the CPU pauses the currently executing program, and processes the sudden interrupt event, which is also called executing interrupt service routine (Interrupt Service Routine, ISR). When an interrupt occurs, the point where the program is suspended is called an interrupt return address, and after the CPU completes executing the interrupt service program, the CPU needs to return to the interrupt return address to continue executing the program. In order for the CPU to return smoothly, a protection program site, called a protection site, is required before the interrupt service routine is executed. Also, after the CPU finishes processing the interrupt service routine, it is necessary to resume the program site before the interrupt occurs, which is called a resume site. The time spent in the middle from the interrupt request of the interrupt source to the actual processing of specific content in the interrupt service routine by the CPU is called interrupt response time. The interrupt response time of the related art interrupt mechanism is long, resulting in low efficiency of interrupt processing.

Disclosure of Invention

Embodiments of the present application aim to solve one of the technical problems in the related art at least to some extent. For this reason, an object of an embodiment of the present application is to provide a method, an apparatus, an electronic device, a storage medium, a chip, and a program product for processing an interrupt event.

The embodiment of the application provides a processing method of an interrupt event, which comprises the following steps: in response to receiving an interrupt request for a first interrupt event, writing first interrupt context information stored in a base register to a backup register, wherein the first interrupt context information is used to characterize field information of a central processing unit in the event of the first interrupt event; processing the first interrupt event in response to determining that writing first interrupt context information stored in the base register to the backup register is complete; first interrupt context information stored in the backup register is written to memory in parallel during processing of the first interrupt event.

Another embodiment of the present application provides an apparatus for processing an interrupt event, including: the device comprises a first writing module, a first processing module and a second writing module. A first writing module, configured to write first interrupt context information stored in a base register into a backup register in response to receiving an interrupt request for a first interrupt event, where the first interrupt context information is used to characterize field information of a central processing unit in a case where the first interrupt event occurs; a first processing module for processing the first interrupt event in response to determining that writing of the first interrupt context information stored in the base register to the backup register is complete; and the second writing module is used for writing the first interrupt context information stored in the backup register into a memory in parallel in the process of processing the first interrupt event.

Another embodiment of the present application provides an electronic device, including a memory storing a computer program and a processor implementing the steps of the method according to any of the above embodiments when the processor executes the computer program.

Another embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the method of any of the above embodiments.

Another embodiment of the present application provides a chip, including a central processing unit, where the central processing unit is configured to perform the steps of the method according to any one of the foregoing embodiments.

Another embodiment of the present application provides a computer program product comprising instructions that, when executed by a processor of a computer device, enable the computer device to perform the steps of the method according to any one of the embodiments above.

In the above embodiment, the first interrupt context information stored in the base register is written into the backup register in response to receiving the interrupt request for the first interrupt event; in response to determining that writing the first interrupt context information stored in the base register to the backup register is complete, processing a first interrupt event; during processing of the first interrupt event, the first interrupt context information stored in the backup register is written to memory in parallel. The embodiment shortens the interrupt response time and improves the processing efficiency of interrupt events.

Drawings

FIG. 1 is a schematic diagram of a base register and a backup register provided by an embodiment of the present application;

fig. 2 is a flow chart of a method for processing an interrupt event according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a method for handling interrupt events according to an embodiment of the present disclosure;

FIG. 4 is a flowchart illustrating a method for handling interrupt events according to another embodiment of the present disclosure;

FIG. 5 is a flowchart illustrating a method for handling interrupt events according to another embodiment of the present disclosure;

FIG. 6 is a flowchart illustrating a method for handling interrupt events according to another embodiment of the present disclosure;

FIG. 7 is a flowchart illustrating a method for handling interrupt events according to another embodiment of the present disclosure;

fig. 8 is a schematic diagram of an apparatus for processing an interrupt event according to an embodiment of the present application.

Detailed Description

Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.

The interrupt mechanism is one of the basic mechanisms in a computer system, which is a reaction of a central processing unit (Central Processing Unit, CPU) to an event occurring at a certain moment in the system. An event that causes an Interrupt is called an Interrupt Source (Interrupt Source). Typically, the interrupt source is primarily from the peripheral hardware device. The request made by the interrupt source to the CPU is called an interrupt request (Interrupt Request). After receiving the interrupt request from the interrupt source, the CPU pauses the currently executing program, and processes the sudden interrupt event, which is also called executing interrupt service routine (Interrupt Service Routine, ISR). When an interrupt occurs, the point where the program is suspended is called an interrupt return address, and after the CPU completes executing the interrupt service program, the CPU needs to return to the interrupt return address to continue executing the program. In order for the CPU to return smoothly, a protection program site, called a protection site, is required before the interrupt service routine is executed. Also, after the CPU finishes processing the interrupt service routine, it is necessary to resume the program site before the interrupt occurs, which is called a resume site. The time spent in the middle from the interrupt request of the interrupt source to the actual processing of specific content in the interrupt service routine by the CPU is called interrupt response time.

NVIC (Nested Vectored Interrupt Controller) is an interrupt controller in an ARM Cortex-M series processor, and the interrupt controller NVIC may be responsible for managing and handling all interrupt requests. An interrupt vector table is provided in the interrupt controller NVIC for storing the entry addresses of interrupt handlers (also referred to as interrupt handling functions). When an interrupt request is initiated, the interrupt controller NVIC searches the interrupt vector table according to the priority of the interrupt request, so as to find the corresponding interrupt handler and execute the interrupt handler.

The interrupt controller NVIC supports both hardware interrupts and software interrupts. A hardware interrupt is an interrupt request triggered by an external device, such as a timer overflow, an external interrupt, serial port reception, etc. A software interrupt is an interrupt request initiated by a software program, such as a scheduled interrupt of an operating system, a user-defined interrupt, etc.

The interrupt controller NVIC includes an interrupt enable register, an interrupt priority register, an interrupt waiting register, and the like. If the CPU has a secure extension mechanism, a configuration register may also be included in the interrupt controller NVIC to set the interrupt to an unsecure interrupt. For example, the CPU based on ARM v8-M architecture can realize safe expansion, after the safe expansion is realized, the running state of the CPU is divided into two states of safe state and unsafe state, and the safe state of the CPU can be switched through instructions. A secure state, for example, refers to all resources within a computer being accessible during processing of an interrupt event, and an unsecure state, for example, refers to only those resources within a computer that are set unsecure during processing of an interrupt event. After the secure extension is implemented, the NVIC may configure the interrupt to be a secure interrupt or a non-secure interrupt through the interrupt controller, and by default, all interrupts are secure interrupts. Secure interrupt handling means that interrupt handling needs to be performed in a CPU secure state, and non-secure interrupt handling means that interrupt handling needs to be performed in a CPU non-secure state. The CPU may generate interrupts in both the secure and non-secure states.

The interrupt controller NVIC is an inseparable part of the ARM Cortex-M series processor, and is tightly coupled with the logic of the CPU. In an example, the interrupt controller NVIC may be part of a CPU, e.g., the CPU includes at least a kernel and the interrupt controller NVIC. ARM Cortex-M series based processors take a CPU of ARM v8-M architecture as an example.

The application first proposes a reference embodiment, and the interrupt response procedure is as follows:

1. in the case of receiving an interrupt request, the currently executing program is stopped, and hardware (hardware referred to herein may include a CPU) automatically saves interrupt context information, which indicates the field information of the CPU at the time of occurrence of an interrupt event, into a stack memory, and after the interrupt is subsequently processed, the program field before the occurrence of the interrupt needs to be restored based on the interrupt context information. The content of the interrupt context information differs depending on whether the CPU contains a floating point extension and a secure extension.

a) In the case where the CPU contains neither a floating point extension nor a secure extension, the interrupt context information includes content stored in registers r0, r1, r2, r3, r12, lr, retaddress, xpsr. The registers typically include 49, 8 of which r0, r1, r2, r3, r12, lr, retaddress, xpsr,

r0, r1, r2, etc. represent the identity of the corresponding register. The registers of this example may refer to the underlying registers in fig. 1 below.

b) In the case where the CPU contains a floating point extension but does not contain a secure extension, when there is an outstanding floating point operation when an interrupt occurs, the interrupt context information includes, in addition to the contents stored in the 8 registers in the case of a), the contents in 17 registers related to the floating point operation, the 17 registers including s0 to s15 and fpscr, and the 17 registers may be configured such that the interrupt does not immediately store the corresponding interrupt context information on the stack memory when an interrupt occurs, but a storage space is reserved on the stack memory first, and the register contents (interrupt context information) related to the floating point are stored on the stack memory only when there is also a floating point operation in the interrupt handler; when no outstanding floating point operations occur at the time of the interrupt, the interrupt context information is consistent with the case of a).

c) Cases where the CPU contains a secure extension but no floating point extension

i. If the interrupt is generated in a secure state, but the processing of the interrupt is in an unsecure state, the interrupt context information includes the contents stored in registers r 0-r 12, lr, retaddress, xpsr.

if the interrupt is generated in a secure state, the processing of the interrupt is also in a secure state, or the interrupt is generated in an unsecure state, the processing of the interrupt is also in an unsecure state, or the interrupt is generated in an unsecure state, but the processing of the interrupt is in a secure state, the interrupt context information is consistent with the situation of a).

d) Cases where the CPU contains both secure and floating point extensions

i. If an interrupt is generated in an unsecure state, the interrupt context information is consistent with b).

if the interrupt is generated in a secure state, but no outstanding floating point operations are occurring when the interrupt occurs, the interrupt context information is consistent with c).

if an interrupt is generated in a secure state, but there are outstanding floating point operations when an interrupt occurs

(1) If the interrupt is generated in the secure state, but the processing of the interrupt is in the unsecure state, the interrupt context information includes the contents stored in 49 registers s 0-s 31, fpscr, r 0-r 12, lr, retaddress, xpsr.

(2) If the interrupt is generated in a secure state, the processing of the interrupt is also in a secure state, or the interrupt is generated in an unsafe state, the processing of the interrupt is also in an unsafe state, or the interrupt is generated in an unsafe state, but the processing of the interrupt is in a secure state, the interrupt context information is consistent with the situation of b).

2. And searching the entry address of the interrupt handler according to the current interrupt number index, wherein the interrupt number is the identification of the interrupt event.

3. After waiting for the completion of saving the interrupt context information to the stack memory, the CPU jumps to the entry address of the interrupt handler to execute the contents of the interrupt handler.

4. High priority interrupts can interrupt execution of a current interrupt handler, forming multiple interrupt nests. When interrupt nesting occurs, the steps 1-3 can be repeated when each interrupt is processed.

5. After the interrupt processing program is executed, the interrupt returns, at this time, the hardware automatically restores the interrupt context information from the stack memory to the register for field restoration, and then continues to execute the program interrupted by the interrupt before. If the current returned interrupt is not the interrupt of the innermost layer of the interrupt nest, returning to the interrupt processing program which is interrupted before to continue to execute; if the currently returned interrupt is the interrupt of the innermost layer of interrupt nesting, returning to the normal program flow to execute the originally interrupted program. Taking three interrupts as examples, during the process of processing the first interrupt, the second interrupt with higher priority is received, at this time, the process of the first interrupt is stopped and the process of the second interrupt is started, during the process of processing the second interrupt, the process of the third interrupt with higher priority is received, at this time, the process of the second interrupt is stopped and the process of the third interrupt is started, at this time, the three interrupts form an interrupt nest, the first interrupt is the interrupt of the innermost layer, the second interrupt is the interrupt of the middle layer, and the third interrupt is the interrupt of the outermost layer. After the third interrupt is processed, the interrupt processing program which is returned to the previous (second) interrupted continues to execute, after the second interrupt is processed, the interrupt processing program which is returned to the previous (first) interrupted continues to execute, and after the first interrupt is processed, the interrupt (first) which is returned currently is the interrupt of the innermost layer of the interrupt nest, and at the moment, the program which is originally interrupted is returned to the normal program flow to execute.

It can be seen that the interrupt context information is saved by hardware, and the saved process is to write the interrupt context information in the register into the memory one by one, and in general, it is necessary to wait until the interrupt context information is written into the memory, and then the CPU can jump to the entry address of the interrupt handler to execute the interrupt handler.

In another reference embodiment, the process of fetching the entry address of the interrupt handler and saving the interrupt context information of the register to memory may be performed in parallel. However, writing the interrupt context information of the register to the memory is time consuming, resulting in that even if the entry address of the interrupt handler has been indexed or calculated, it is necessary to wait until the interrupt context information of the register is saved to the memory before jumping to the entry address of the interrupt handler, especially as in the case of the contexts d) -iii- (1), the interrupt context information involves up to 49 registers, the interrupt context information of 49 registers needs to be written to the memory, the process of which is time consuming, resulting in a larger response delay of the interrupt. It should be appreciated that the need to wait until the interrupt context information of the register is saved to memory before jumping to the entry address of the interrupt handler for interrupt handling is to avoid the risk that the interrupt context information of the register will jump to the entry address of the interrupt handler for interrupt handling before being saved to memory completely, with the subsequently occurring interrupt context information overriding the register contents, resulting in loss of current interrupt context information.

The interrupt event processing method according to the above-described reference embodiment has a problem that interrupt response time is long, resulting in low interrupt processing efficiency. Therefore, a manner of rapidly saving interrupt context information is needed, so that the CPU jumps to the entry address of the interrupt handler to process the interrupt event as soon as possible after responding to the interrupt, so as to shorten the interrupt response time and improve the interrupt processing efficiency.

In view of the above problems pointed out in the reference examples, the present embodiment provides an optimized interrupt event processing method.

The interrupt event processing method provided in this embodiment relates to two types of registers, including a base register and a backup register. The register mentioned in the above reference embodiment is a register based, and the present embodiment adds a backup register based on the above reference embodiment.

Fig. 1 shows a schematic diagram of a base register and a backup register provided in an embodiment of the present application.

In view of the problems pointed out in the above-mentioned reference embodiments, this embodiment proposes another interrupt response flow based on the CPU of the ARM v8-M architecture and having floating point extensions and secure extensions. And a group of backup registers are added on the hardware level, and the backup registers correspond to the basic registers. For example, the number of backup registers corresponds to the number of basic registers, and the basic registers include s0 to s31, fpscr, r0 to r12, lr, retaddress, xpsr, and 49 backup registers sr0 to sr48 are correspondingly increased. The backup register may be used as a hardware storage area to temporarily hold interrupt context information when responding to an interrupt.

Fig. 2 is a flow chart of a method for processing an interrupt event according to an embodiment of the present application.

As shown in fig. 2, the method 200 for processing an interrupt event provided in the embodiment of the present application includes steps S210 to S230, for example. The interrupt event processing method 200 may be performed by a central processing unit CPU.

In step S210, in response to receiving the interrupt request for the first interrupt event, the first interrupt context information stored in the base register is written into the backup register.

Illustratively, in the process of the CPU processing the current event or the interrupt event occurring before the processing, if the first interrupt event occurs subsequently, an interrupt request for the first interrupt event is generated. Each time an interrupt event occurs, the contents of the current base register are the context information of the interrupt.

The first interrupt context information is used to characterize the presence information of the central processing unit CPU in case of a first interrupt event. Specifically, when the CPU receives an interrupt request, the CPU pauses the currently running process or thread and then jumps to a predefined interrupt handler to execute the interrupt event. In this process, since the original event or program needs to be returned to be executed after the interrupt event processing is completed, some critical field information needs to be saved and restored for smooth return, so the field information of the CPU is saved by storing the first interrupt context information.

After receiving the interrupt request for the first interrupt event, the CPU writes the first interrupt context information stored in the base register into the backup register, so as to prevent the first interrupt context information in the base register from being destroyed due to the fact that the base register is used in the process of executing the interrupt processing program.

In step S220, in response to determining that writing the first interrupt context information stored in the base register to the backup register is complete, the first interrupt event is processed.

In one example, processing the first interrupt event begins after determining that writing the first interrupt context information stored in the base register to the backup register is complete. For example, the CPU jumps to an entry address of an interrupt handler corresponding to the first interrupt event, and processing the first interrupt event is achieved by executing the interrupt handler.

In step S230, the first interrupt context information stored in the backup register is written in parallel to the memory during the processing of the first interrupt event.

Illustratively, the time required to write the first interrupt context information to the backup register is much shorter than the time required to write the first interrupt context information to the memory due to the different structures and functions of the registers and the memory. Second, the time required to process the first interrupt event is also typically relatively long, so the first interrupt context information stored in the backup register may be written to memory in parallel during processing of the first interrupt event. Compared with the situation that the first interrupt event is required to be processed after the first interrupt context information stored in the basic register is required to be written into the memory when only the basic register is included, the first interrupt event is required to be processed immediately after the first interrupt context information stored in the basic register is quickly written into the backup register to be temporarily stored by setting the backup register, and the first interrupt context information in the backup register is written into the memory in parallel in the process of processing the first interrupt event, so that the time required by interrupt processing is shortened. Therefore, the embodiment processes the interrupt event by setting the backup register, shortens the interrupt response time and improves the processing efficiency of the interrupt event.

In another example, during processing of the first interrupt event, if a second interrupt event occurs subsequently, the second interrupt event also needs to be processed.

For example, after receiving an interrupt request for the first interrupt event, a memory space for storing the first interrupt context information may be reserved in the memory, and then the first interrupt context information stored in the base register is written into the backup register for temporary saving in one clock cycle. During the processing of the first interrupt event, the first interrupt context information stored in the backup register is written in parallel to the reserved memory space in the memory. The duration of one clock cycle is much less than the duration required to write the first interrupt context information to memory. It will be appreciated that the operation of writing the first interrupt context information into the backup register may be generally completed within one clock cycle, or the present application does not exclude that the operation of writing the first interrupt context information into the backup register is completed within a shorter or longer period of time according to the actual situation, so long as the time required for writing the first interrupt context information into the backup register is less than the time required for writing the first interrupt context information into the memory, the purpose of shortening the interrupt response time may be achieved.

Similarly, after receiving the interrupt request for the second interrupt event, if the current condition meets the processing condition of the second interrupt event, a storage space for storing the second interrupt context information may be reserved in the memory first, and then the second interrupt context information stored in the base register is written into the backup register for temporary storage in one clock period. During the processing of the second interrupt event, the second interrupt context information stored in the backup register is written in parallel to the reserved memory space in the memory.

Therefore, when responding to the interrupt, a storage space for storing the interrupt context information can be reserved in the memory, then the interrupt context information is stored in the backup register, and the storing operation can be completed within one clock period, so that the interrupt response time is shortened, and the processing efficiency of interrupt events is improved.

Fig. 3 is a schematic diagram of a method for processing an interrupt event according to an embodiment of the present application.

As shown in fig. 3, the memory includes a stack memory (stack memory for short). After receiving the interrupt request, reserving a storage space of interrupt context information in a stack memory, and storing the interrupt context information into a backup register. Taking the example that the interrupt event includes a first interrupt event and a second interrupt event, the interrupt context information includes the first interrupt context information or the second interrupt context information. Then, the entry address of the interrupt handler corresponding to the interrupt event is acquired, and execution of the interrupt handler is started to implement processing of the corresponding interrupt event. In this process, interrupt context information stored in the backup register may be written in parallel to the stack memory space reserved in response to the interrupt.

It can be seen that the interrupt context information is saved by the backup register, and that the interrupt context information stored in the backup register is written in the stack memory in parallel in the process of subsequently acquiring the entry address of the interrupt handler and executing the interrupt handler, i.e. the process of executing the interrupt handler may be parallel to the process of writing the interrupt context information in the backup register to the stack memory. Thus, the time for interrupt response can be greatly shortened, so that the CPU can jump to the entry address of the interrupt handler as early as possible and execute the content of the interrupt handler. The effect of shortening the interrupt response time is more pronounced in the case of a relatively large number of registers involved in the interrupt context information, on the premise that both the set of basic registers and the set of backup registers comprise 49 registers.

It should be understood that, in this embodiment, the interrupt context information corresponding to each interrupt event does not necessarily relate to all 49 basic registers or all 49 backup registers, and in particular, the writing of the interrupt context information stored in the backup registers into the stack memory and the storage layout of the stack memory may refer to the above-mentioned reference embodiments. For example, when an interrupt event generated in an unsafe state is handled in the unsafe state, and when no unfinished floating point operation is performed when the interrupt event occurs, interrupt context information in 8 backup registers corresponding to 8 basic registers of r0, r1, r2, r3, r12, lr, retaddress, xpsr may be saved in the stack memory, and the saving order of the interrupt context information in the stack memory may be identical to the saving order of the above-mentioned reference embodiment.

Fig. 4 is a flowchart of a method for processing an interrupt event according to another embodiment of the present application.

As shown in fig. 4, the memory includes a stack memory (abbreviated as stack memory), and the processing method 400 of the interrupt event provided in this embodiment includes steps S401-S409, for example. The interrupt event processing method 400 may be performed by a central processing unit CPU that includes an interrupt controller NVIC and a kernel core. Some interrupt handling operations may be performed by the interrupt controller NVIC during the processing of interrupt events by the CPU. For example, step S407 may be performed by the interrupt controller NVIC, and other steps may be performed by the kernel of the CPU.

Illustratively, in processing the first interrupt event, if an interrupt request for the second interrupt event is received, a memory write state is determined in which the first interrupt context information stored in the backup register is written to the stack memory. Wherein the event processing priority of the second interrupt event is higher than the event processing priority of the first interrupt event.

And writing second interrupt context information stored in the basic register into the backup register under the condition that the memory writing state indicates that the writing of the first interrupt context information is completed, wherein the interrupt context information of the second interrupt event is used for representing the field information of the CPU under the condition that the second interrupt event occurs.

If it is determined that writing the second interrupt context information stored in the base register to the backup register is completed, processing of the second interrupt event is started. During processing of the second interrupt event, the second interrupt context information stored in the backup register is written in parallel to the stack memory. After the second interrupt event is processed, the processing of the first interrupt event is continued.

If the memory write status indicates that the first interrupt context information is not written to completion, processing the second interrupt event is suspended and processing the first interrupt event continues.

Therefore, in the process of processing the first interrupt event, if a second interrupt event with higher priority occurs, the first interrupt event needs to be suspended and the second interrupt event needs to be processed preferentially under certain conditions, at this time, the first interrupt event and the second interrupt event form a nested interrupt, the second interrupt event is an outer interrupt, and the first interrupt event is an inner interrupt. The specific procedure is referred to as steps S401 to S409 below.

Illustratively, the push flag is set to a first value (e.g., a 0 value) before writing the first interrupt context information or the second interrupt context information stored in the backup register to the stack memory is completed. After writing the first interrupt context information or the second interrupt context information stored in the backup register to the stack memory is completed, the push flag is set to a second value (e.g., a 1 value). The memory write state is characterized by a push flag, e.g., push flag 0 indicates that the write to memory is incomplete and push flag 1 indicates that the write to memory is complete.

Step S401, in response to receiving the interrupt request.

Step S402, reserving a storage space of interrupt context information in a stack memory, saving the interrupt context information to a backup register, and clearing a push identifier of 0.

Illustratively, clearing the push flag to 0 indicates setting the push flag to a value of 0. For example, after receiving the first interrupt request, it is necessary to write the first interrupt context information stored in the base register into the backup register, and clear the push flag by 0, which indicates that the writing of the first interrupt context information into the stack memory has not been completed.

Step S403, an entry address of the interrupt handler is acquired.

Step S404, an interrupt handler is executed.

For example, the interrupt handler may correspond to an interrupt event, and processing the corresponding interrupt event may be implemented by executing the interrupt handler. For example, if the interrupt event is a first interrupt event, executing the interrupt handler may implement processing the first interrupt event.

In step S405, the interrupt context information in the backup register is written into the reserved storage space of the stack memory.

In step S406, the push flag is set to 1.

For example, during execution of the first interrupt handler, the first interrupt context information stored in the backup register may be written to the stack memory in parallel. After the write is completed, the push flag is set to 1, indicating that the write is completed.

Step S407, it is determined whether a high-priority interrupt request is received. If yes, go to step S408; if not, step S409 is performed.

For example, during execution of an interrupt handler for a first interrupt event, it may be detected in real time whether a higher priority interrupt event, such as a second interrupt event, has occurred.

In step S408, it is determined whether the push flag is 1. If yes, return to execute step S402; if not, step S409 is performed.

If a high priority interrupt request is received, it is further determined whether the push flag is 1. If the push flag is 1, indicating that the writing of the first interrupt context information to the stack memory has been completed, execution of the first interrupt event may be stopped at this point and execution of step S402 may be returned to begin processing the high priority second interrupt event. After the second interrupt event is processed, a return to continuing processing the first interrupt event is required.

Step S409, the interrupt handling routine is continued.

For example, if a high-priority interrupt request is not received, or if a high-priority interrupt request is received but interrupt context information corresponding to a last interrupt event is not completely written into the stack memory, in order to avoid that the interrupt context information with a high priority overwrites the last interrupt context information in the backup register to cause information loss, it is necessary to suspend processing of the second interrupt event and continue processing of the first interrupt event. When it is determined that the push flag is 1, step S402 is executed again to store the high-priority second interrupt context information to the backup register, and to clear the push flag for the high-priority second interrupt context information by 0.

It can be seen that in case the CPU has started executing the current interrupt handler but the interrupt context information in the backup register has not been written to the stack memory, no higher priority interrupt event is responded anymore, so as to avoid that the interrupt context information of the new interrupt event overrides the interrupt context information in the backup register that has not been saved to the stack memory. After writing the interrupt context information of the backup register to the stack memory is completed, the response to the higher priority interrupt event may begin and an interrupt nest may be formed. And adding a push identifier for the backup register on hardware, and indicating whether the operation of saving the interrupt context information of the backup register to the stack memory is completed or not by using the push identifier. When the backup register is updated in response to the interrupt event with high priority, the push identifier is cleared again to 0, and after the operation of saving the interrupt context information of the backup register to the stack memory is completed, the push identifier is set to 1 again, so that it is seen that execution of a plurality of nested interrupts can be controlled through the push identifier.

Fig. 5 is a flowchart of a method for processing an interrupt event according to another embodiment of the present application.

As shown in fig. 5, the processing method 500 of the interrupt event provided in the present embodiment includes steps S501 to S519, for example.

Step S501, in response to receiving the interrupt request.

Step S502, reserving a storage space of interrupt context information in a stack memory, saving the interrupt context information to a backup register, and clearing a push identifier of 0.

In step S503, the entry address of the interrupt handler is acquired.

Step S504, an interrupt handler is executed.

In step S505, the interrupt context information in the backup register is written into the reserved storage space of the stack memory.

Step S506, the push identifier is set to 1.

Step S507, it is determined whether a high-priority interrupt request is received. If yes, go to step S508; if not, step S510 is performed.

Step S508, determining whether the push identifier is 1. If yes, step S509 is performed; if not, step S510 is performed.

Step S509, forming interrupt nesting, and returning to step S502.

Step S510, the interrupt handling procedure is continued.

Steps S501 to S510 of this embodiment are the same as or similar to the corresponding steps of the example shown in fig. 4, and are not described herein.

In step S511, an interrupt return instruction is executed.

Step S512, it is confirmed whether the push flag is 1. If yes, go to step S514; if not, step S513 is performed.

Step S513 waits until the saving of the interrupt context information in the backup register to the stack memory is completed.

In step S514, interrupt context information is restored from the stack memory.

For example, taking the currently processed interrupt event as the first interrupt event as an example. In one case, before the first interrupt event processing is completed, if steps S505 and S506 are both completed before the previous execution, then step S512 determines that the push stack corresponding to the first interrupt event is identified as being supposed to be 1, and at this time, the interrupt context information is directly recovered from the stack memory, for example, the first interrupt context information stored in the stack memory is read to the base register to implement recovery of the interrupt context information from the stack memory.

In another case, after receiving the interrupt return instruction indicating that the processing of the first interrupt event is completed, a memory write state in which the first interrupt context information stored in the backup register is written to the stack memory is determined, and if the memory write state indicates that the first interrupt context information is not written to completion (i.e., steps S505 and S506 are not performed to completion before the interrupt return instruction is received), execution of the interrupt return instruction is suspended at this time, and the completion of the first interrupt context information writing is waited for. After determining that the writing of the first interrupt context information is completed, the first interrupt context information stored in the stack memory is read into the base register. Specifically, if steps S505 and S506 take much time, when the interrupt of step S511 is returned, there is a case where the push identifier corresponding to the first interrupt event is not updated yet (when the push identifier is still 0) after the processing of the first interrupt event is completed, and at this time, waiting is continued until the operation of saving the first interrupt context information in the backup register to the stack memory is completed (when the push identifier is updated to 1), and then the first interrupt context information is restored from the stack memory.

It follows that if less program content needs to be executed in the interrupt handler, in some cases, such as when the saving of the interrupt context information in the backup register to the stack memory has not been completed at the time of the interrupt return, the return instruction is required to instruct waiting until the interrupt context information in the backup register is saved to the stack memory before the execution of the interrupt return instruction is started. When the interrupt returns, the interrupt context information can be directly restored to the basic register from the stack memory, and the interrupt context information does not pass through the backup register any more.

Step S515, adjusting the stack position, and releasing the memory space of the stack memory.

In step S516, the current interrupt returns to the end.

Step S517, it is determined whether the current interrupt is the innermost interrupt. If not, then step S518 is performed; if so, step S519 is performed.

Step S518, the previous interrupt handler is returned.

In step S519, all interrupt processing ends.

For example, taking a first interrupt event and a second interrupt event as an example, the second interrupt event occurs after the first interrupt event, and the event processing priority of the second interrupt event is higher than the event processing priority of the first interrupt event. The first interrupt event and the second interrupt event form interrupt nesting, the first interrupt event is the innermost interrupt, and the second interrupt event is the outer interrupt. If the currently processed interrupt event is the second interrupt event, it is determined at step S517 that the current interrupt event is not the innermost interrupt, and step S518 is required to be performed to return to the last interrupt handler to continue processing the first interrupt event.

Fig. 6 is a flowchart of a method for processing an interrupt event according to another embodiment of the present application.

As shown in fig. 6, the processing method 600 of the interrupt event provided in this embodiment includes steps S601 to S621, for example.

Step S601, in response to receiving the interrupt request.

Step S602, reserving a storage space of interrupt context information in a stack memory, saving the interrupt context information to a backup register, setting the interrupt context information of the backup register to be effective, and clearing a push identifier to 0.

It will be appreciated that when a new high priority interrupt event occurs, the interrupt context information of the newly occurring high priority interrupt event needs to be set to be valid when step S602 is performed. For ease of understanding, the present embodiment exemplifies a first interrupt event and a high priority second interrupt event.

After the occurrence of the high-priority second interrupt event, in the case where writing of the second interrupt context information stored in the base register to the backup register is completed, the state of the interrupt context information (e.g., the second interrupt context information) stored in the backup register is set to be valid.

In step S603, the entry address of the interrupt handler is acquired.

In step S604, an interrupt handler is executed.

In step S605, the interrupt context information in the backup register is written into the reserved storage space of the stack memory.

Step S606, a push flag is set to 1.

In step S607, it is determined whether a high-priority interrupt request is received. If yes, go to step S608; if not, step S610 is performed.

In step S608, it is determined whether the push flag is 1. If yes, step S609 is performed; if not, step S610 is performed.

Step S609, forming interrupt nesting, and returning to step S602.

Step S610, the interrupt handling routine is continued.

In step S611, an interrupt return instruction is executed.

Steps S601, S603-S611 of this embodiment are the same as or similar to the corresponding steps of the example shown in fig. 5, and are not described herein.

In step S612, it is confirmed whether the interrupt context information of the backup register is valid. If not, then step S613 is performed; if so, step S614 is performed.

In step S613, interrupt context information is restored from the stack memory.

In step S614, it is confirmed whether the push flag is 1. If yes, go to step S616; if not, step S615 is performed.

Step S615, stopping the storage. For example, the saving of the interrupt context information of the backup register to the stack memory is stopped.

In step S616, the interrupt context information is restored from the backup register, and the interrupt context information of the backup register is set to be invalid.

Further description is provided below with respect to steps S612-S616.

If the currently processed interrupt event is a second interrupt event of high priority, upon receiving an interrupt return instruction indicating that the second interrupt event processing is completed (step S611), it is necessary to determine a memory write state in which second interrupt context information stored in the backup register is written to the stack memory. For example, upon receiving an interrupt return instruction indicating that the second interrupt event processing is completed, and in the case where it is determined that the state of the second interrupt context information stored in the backup register is valid, it is further determined that the second interrupt context information stored in the backup register is written to the memory writing state of the memory.

And stopping continuous writing and writing the second interrupt context information stored in the backup register back to the basic register when the memory writing state indicates that the second interrupt context information is not written.

Specifically, in step S612, it is confirmed that the interrupt context information (second interrupt context information) of the backup register is valid, and in step S614, it is further determined whether the push flag for the second interrupt event is 1, if the push flag is 1, it indicates that writing of the second interrupt context information from the backup register to the stack memory is completed, at this time, the second interrupt context information (writing the second interrupt context information of the backup register to the base register) may be directly recovered from the backup register by executing step S616, and the speed of recovering from the backup register is fast, which does not exclude, of course, that the second interrupt context information may be written from the stack memory to the base register.

If step S614 determines that the push flag is not 1, indicating that the process of writing the second interrupt context information from the backup register to the stack memory has not been completed, at which point the saving of the interrupt context information of the backup register to the stack memory is stopped (the subsequent writing to the stack memory is stopped), and step S616 is performed to directly restore the second interrupt context information from the backup register (the writing of the second interrupt context information of the backup register back to the base register).

After the second interrupt context information is restored from the backup register, the interrupt context information of the backup register needs to be set to be invalid so that, at the time of an interrupt event after processing (such as the first interrupt event of the inner layer), the interrupt context information of the backup register is judged to be invalid at the time of interrupt return so as to restore the interrupt context information from the stack memory.

Step S617, the position of the stack is adjusted, and the storage space of the stack memory is released.

In step S618, the current interrupt returns to the end.

In step S619, it is determined whether the current interrupt is the innermost interrupt. If not, then step S620 is performed; if so, step S621 is performed.

Step S620, the previous interrupt handler is returned.

In step S621, all interrupt processing ends.

Steps S617-S621 of this embodiment are the same as or similar to the corresponding steps of the example shown in fig. 5, and are not described herein.

The example shown in fig. 6 is applicable to accelerating interrupt returns. After the CPU responds to the interrupt and saves the interrupt context information to the backup register, the interrupt context information of the backup register is automatically recorded as effective. Based on this, when the interrupt event processing is completed and the interrupt returns, it is necessary to further determine whether the interrupt context information of the backup register is valid.

In one case, taking the current interrupt event as the second interrupt event with high priority as an example, if the interrupt context information of the backup register is valid, it indicates that the interrupt context information in the backup register is the interrupt context information corresponding to the current interrupt event, and also indicates that the current interrupt event is the interrupt event of the outermost layer in the interrupt nesting. At this time, if the process of saving the interrupt context information in the backup register to the stack memory is not finished, stopping to continue saving, directly recovering the interrupt context information from the backup register to the base register, adjusting the position of the stack, and removing the stack memory space occupied by the interrupt context information. If the process of saving the interrupt context information in the backup register to the stack memory is finished, the interrupt context information can be directly restored to the basic register from the backup register, the position of the stack is adjusted, and the stack memory space occupied by the interrupt context information is removed. After the completion of the interrupt context information restoration, the interrupt context information of the backup register is set to be invalid.

In another case, when the first interrupt event is returned to be processed after the second interrupt event is processed, the current interrupt event is the first interrupt event. Since the interrupt context information of the high-priority second interrupt event already covers the interrupt context information corresponding to the current interrupt event (such as the first interrupt event) in the backup register, the interrupt context information of the backup register is invalid at this time, which indicates that the interrupt context information in the backup register is not the interrupt context information corresponding to the current interrupt event (the first interrupt event), and also indicates that the high-priority second interrupt event interrupting the first interrupt event has been processed and returned. In addition, the interrupt context information corresponding to the current interrupt event (e.g., the first interrupt event) is already stored in the stack memory, so that the interrupt context information corresponding to the current interrupt event (e.g., the first interrupt event) needs to be recovered from the stack memory, the position of the stack is adjusted, and the stack memory space occupied by the interrupt context information is removed.

Therefore, in this embodiment, by setting the state (valid state or invalid state) of the interrupt context information of the backup register, when the outermost interrupt event is processed, the interrupt context information can be directly recovered from the backup register, and if the process of writing the interrupt context information of the backup register into the stack memory is not completed, the process is stopped, so as to accelerate the return of the interrupt, and improve the processing efficiency of the interrupt event.

Fig. 7 is a flowchart of a method for processing an interrupt event according to another embodiment of the present application.

As shown in fig. 7, the processing method 700 of the interrupt event provided in the present embodiment includes steps S701 to S722, for example.

Step S701, in response to receiving the interrupt request.

Step S702, reserving a storage space of interrupt context information in a stack memory, saving the interrupt context information to a backup register, setting the interrupt context information of the backup register to be effective, recording the position of the interrupt context information in the stack memory, and clearing a push identifier by 0.

It will be appreciated that when a new high priority interrupt event occurs, the interrupt context information of the newly occurring high priority interrupt event needs to be set to be valid when step S702 is performed. Before writing interrupt context information to the stack memory, a memory space needs to be reserved in the stack memory, at which point the location of the reserved memory space can be recorded. For ease of understanding, the present embodiment exemplifies a first interrupt event and a high priority second interrupt event.

After the first interrupt event occurs, in the case where writing of the first interrupt context information stored in the base register to the backup register is completed, the state of the interrupt context information (e.g., the first interrupt context information) stored in the backup register is set to be valid. Next, after the occurrence of the second interrupt event of high priority, in the case where writing of the second interrupt context information stored in the base register into the backup register is completed, the state of the interrupt context information (e.g., the second interrupt context information) stored in the backup register is set to be valid, at which time the state originally for the first interrupt context information is invalid or overwritten.

In step S703, the entry address of the interrupt handler is acquired.

In step S704, an interrupt handler is executed.

Step S705, writing the interrupt context information in the backup register into the reserved storage space of the stack memory.

Step S706, the push flag is set to 1.

Step S707 determines whether a high-priority interrupt request is received. If yes, go to step S708; if not, step S710 is performed.

In step S708, it is determined whether the push flag is 1. If yes, step S709 is performed; if not, step S710 is performed.

Step S709, forming interrupt nesting, and returning to step S702.

Steps S701, S703-S709 of this embodiment are the same as or similar to the corresponding steps of the example shown in fig. 5 or fig. 6, and are not described herein.

Step S710, the interrupt handling routine is continued.

In step S711, it is confirmed whether the interrupt context information of the backup register is valid. If not, step S712 is performed.

Step S712, reading the interrupt context information in the stack memory to the backup register according to the recorded position of the interrupt context information in the stack memory.

In step S713, the interrupt context information of the backup register is set to be valid.

In step S714, an interrupt return instruction is executed.

In step S715, it is confirmed whether the interrupt context information of the backup register is valid. If not, then step S716 is performed; if so, step S717 is performed.

Step S716, wait until the completion of reading the interrupt context information of the stack memory to the backup register, and then set the interrupt context information of the backup register to be valid.

In step S717, the interrupt context information is restored from the backup register, and the interrupt context information of the backup register is set to be invalid.

Further description is provided below with respect to steps S710-S717.

If the currently processed event is a second interrupt event of high priority, step S711 may be performed in parallel to determine whether the interrupt context information of the backup register is valid (based on the fact that the interrupt context information of the backup register is valid for the second interrupt event is known to be valid in step S702) in the course of executing the interrupt handler for the second interrupt event (step S710), and step S712 is not performed in the case that the interrupt context information of the backup register is valid. After the execution of the interrupt handler for the second interrupt event is completed, the interrupt returns (step S714), and it is again confirmed whether the interrupt context information of the backup register is valid (step S715), and it is known that the interrupt context information for the second interrupt event is valid, at this time, step S717 is performed to directly restore the interrupt context information (such as the second interrupt context information) from the backup register, and the interrupt context information of the backup register is set to be invalid after the restoration is completed. It can be seen that in the case where the second interrupt event processing is completed, the state of the second interrupt context information stored in the backup register needs to be set to invalid.

And in the process of completing the second interrupt event processing and returning to continue to process the first interrupt event, the current interrupt event is the first interrupt event, and the first interrupt context information stored in the memory is read to the backup register in parallel. Specifically, in the case where it is determined that the state of the second interrupt context information stored in the backup register is invalid in the process of completing the second interrupt event processing and returning to continue processing the first interrupt event, it is necessary to read the first interrupt context information stored in the stack memory to the backup register in parallel and set the state of the first interrupt context information stored in the backup register to be valid. Next, after receiving an interrupt return instruction indicating that the first interrupt event processing is completed, the first interrupt context information stored in the backup register is written back to the base register to enable restoration of the first interrupt context information from the backup register.

Specifically, in the process that the second interrupt event processing is completed and the processing of the first interrupt event is returned to continue, the current interrupt event is the first interrupt event, in the process of executing the interrupt processing program for the first interrupt event (step S710), step S711 may be executed in parallel to determine whether the interrupt context information (such as the first interrupt context information) of the backup register is valid (it is known that the state for the second interrupt context information has been set to valid in step S702 after responding to the second interrupt event of high priority while the state for the first interrupt context information has become invalid), in the event that the interrupt context information (such as the first interrupt context information) in the stack memory is invalid is read in advance to the backup register (step S712), and step S713 is executed to set the interrupt context information (such as the first interrupt context information) of the backup register to valid after the reading is completed. After the execution of the interrupt handler for the first interrupt event is completed, the interrupt returns (step S714), and it is again confirmed whether the interrupt context information of the backup register is valid (step S715), and if not, it is necessary to wait until the completion of reading the interrupt context information of the stack memory to the backup register, and after completion, the interrupt context information of the backup register is set to be valid. Step S717 is then performed to restore the interrupt context information (e.g., the first interrupt context information) directly from the backup register, and the interrupt context information (e.g., the first interrupt context information) of the backup register is set to be invalid after the restoration is completed, so that steps S712 and S713 are performed to read the corresponding interrupt context information from the stack memory in advance based on the invalid state when the subsequent interrupt is processed.

It follows that interrupt context information (e.g., second interrupt context information) may be restored directly from the backup register when the outermost interrupt event (e.g., second interrupt event) is processed. When the second interrupt event is processed and then the inner layer interrupt event (such as the first interrupt event) is executed, in the process of executing the interrupt processing program, corresponding first interrupt context information can be read from the stack memory in advance to the backup register in parallel, and then the first interrupt context information of the backup register is directly written back to the basic register when the interrupt returns to realize the recovery of the first interrupt context information. As can be seen, compared with the manner of reading the interrupt context information from the stack memory to the base register when waiting for the interrupt to return, the method of the present embodiment causes that the time for executing the interrupt handler and the time for reading the information from the stack memory accumulate to affect the interrupt return speed, the method of the present embodiment reads the information from the stack memory in parallel during the execution of the interrupt handler, compresses the time for reading the information from the stack memory to the time for executing the interrupt handler, and directly writes the interrupt context information of the backup register back to the base register when the interrupt returns (for example, only one clock cycle is needed). It can be seen that the interrupt context information is recovered from the backup register only by one clock cycle, which is much faster than the recovery from the stack memory, so that the interrupt return speed can be greatly increased by reading the interrupt context information from the stack memory in advance.

Step S718, adjusting the position of the stack, and releasing the storage space of the stack memory.

In step S719, the current interrupt returns to end.

In step S720, it is determined whether the current interrupt is the innermost interrupt. If not, then step S721 is performed; if so, step S722 is performed.

In step S721, the previous interrupt processing routine is returned.

In step S722, all interrupt processing ends.

Steps S718-S722 of the present embodiment are the same as or similar to the corresponding steps of the example shown in fig. 5 or fig. 6, and are not described herein.

It can be seen that fig. 7 shows another way of accelerating interrupt return, where the CPU may respond to an interrupt and save interrupt context information to the backup register, and may automatically record that the interrupt context information in the backup register is valid, and may also record the location of the interrupt context information corresponding to the current interrupt event in the stack memory. When the CPU is in the process of executing the current interrupt processing program and the interrupt context information of the backup register is invalid, the CPU indicates that the outer interrupt event (such as the second interrupt event) in the interrupt nest is already executed and returns to continue executing the current interrupt event (such as the first interrupt event), and at this time, the CPU can automatically read the interrupt context information (such as the first interrupt context information) from the corresponding position of the recorded stack memory in advance into the backup register. After the read is completed, the interrupt context information (e.g., the first interrupt context) of the backup register is set to be valid. Based on this, the process of executing the interrupt handler and the process of reading current interrupt context information (e.g., first interrupt context information) from the stack memory to the backup register may be performed in parallel.

When the processing of the current interrupt event (such as the first interrupt event) is completed and returned, whether the interrupt context information of the backup register is valid or not is judged. If the interrupt context information of the backup register is valid, the interrupt context information can be directly recovered from the backup register, the position of a stack is adjusted, and the stack storage space occupied by the interrupt context information is removed. If the interrupt context information of the backup register is invalid, the operation of reading the current interrupt context information from the stack memory to the backup register is not completed, and the interrupt return needs to continue waiting until the operation of reading the interrupt context information to the backup register is completed. After waiting until the interrupt context information of the backup register is valid, the interrupt context can be directly recovered from the backup register, the position of a stack is adjusted, and the stack storage space occupied by the interrupt context information is removed.

After the completion of the interrupt context information restoration, the interrupt context information of the backup register needs to be set to be invalid so that the corresponding interrupt context information is read in advance from the stack memory based on the invalid state when the subsequent interrupt is processed.

In an embodiment of the present application, the enable, priority, wait state, etc. of each interrupt event may be set by the interrupt controller NVIC. The interrupt controller NVIC, when responding to an interrupt event, responds to high priority and enabled interrupt events in priority according to the priority of the interrupt. The interrupt processing is executed based on the ARM v8-M CPU, floating point expansion and safety expansion are realized, and the flow of the interrupt processing is summarized as follows:

1. When an interrupt event occurs, the currently executing program is stopped, a storage space for storing interrupt context information is reserved on a stack memory, and the position of the interrupt context information in the stack memory is recorded.

2. Interrupt context information stored in the base registers s 0-s 31, fpscr, r 0-r 12, lr, retaddress, xpsr is automatically saved to the backup registers sr 0-sr 48, and the interrupt context information status of the backup registers is set to valid.

3. The entry address of the interrupt handler is obtained and jumps to the address to execute the interrupt handler.

4. And according to the security state of the CPU, the security state of the target CPU for interrupt processing and the state of floating point operation when the interrupt occurs, part or all of interrupt context information is saved on a stack memory from a backup register.

5. Steps 3 and 4 may be performed in parallel.

6. When the CPU starts to execute the current interrupt processing program and the content of the backup register is not written into the stack memory, the interrupt event with higher priority is not responded any more, so that interrupt context information of the new interrupt event is prevented from being covered by interrupt context information which is not stored into the stack memory in the backup register; at the end of writing interrupt context information of the backup register to the stack memory, a response to a higher priority interrupt event may begin to form an interrupt nest.

7. In the second extended embodiment (the example shown in fig. 7 above), when the interrupt context information state of the backup register is invalid during execution of the interrupt handler, the interrupt context information may be read into the backup register in advance according to the stack memory corresponding to the current interrupt context information.

8. In the case of interrupt return, the actions performed by the different embodiments are different, and the embodiments shown in fig. 5, 6, and 7 are exemplified above.

a) Basic embodiment (embodiment as shown in FIG. 5 above)

Judging whether the process of storing the interrupt context information in the backup register into the stack memory is finished or not:

i. and if the interrupt context information is finished, restoring the interrupt context information from the stack memory, and after the interrupt context information is restored, adjusting the position of the stack to remove the stack memory space occupied by the interrupt context information.

if not, continuing waiting until the interrupt context information in the backup register is stored in the stack memory, executing interrupt return, recovering the interrupt context information from the stack memory, and after the interrupt context information is recovered, adjusting the position of the stack and removing the stack memory space occupied by the interrupt context information.

b) Extended embodiment one (embodiment as shown in FIG. 6 above)

Judging whether interrupt context information of the backup register is valid or not:

i. if the process of saving the interrupt context information of the backup register to the stack memory is not finished, the saving process is stopped, the interrupt context information is directly recovered from the backup register, then the interrupt context information of the backup register is set to be invalid, the position of the stack is adjusted, and the stack space occupied by the interrupt context is removed.

And if invalid, restoring the interrupt context information from the stack memory, and after restoring the interrupt context information, adjusting the position of the stack to remove the stack space occupied by the interrupt context.

c) Extension embodiment two (embodiment shown in FIG. 7 above)

i. and when the interrupt context information is effective, recovering the interrupt context information from the backup register, setting the interrupt context information of the backup register to be ineffective, adjusting the position of a stack, and removing stack space occupied by the interrupt context.

When invalid, waiting until the process of reading the interrupt context information from the stack memory to the backup register is finished, and setting the interrupt context information of the backup register to be valid after finishing; and executing interrupt return, recovering interrupt context information from the backup register, setting the interrupt context information of the backup register as invalid, adjusting the position of a stack, and removing stack space occupied by the interrupt context.

According to the interrupt event processing method, in the process of executing the interrupt processing program, the interrupt context information of the backup register is automatically stored in the stack memory, and the stack pressing time spending required by storing the interrupt context information in the stack memory is hidden in the executing process of the interrupt processing program, so that the interrupt response speed is increased, and the processing efficiency of the interrupt event is improved. In addition, by adding the mark for representing whether the interrupt context information is effective and the push mark for representing whether the process of storing the interrupt context information into the stack memory is completed to the backup register, the quick response and recovery of the interrupt are realized, and the interrupt nesting formed by a plurality of interrupt events can be supported.

Therefore, the method and the device can quickly respond to the interrupt, reserve the storage space of the interrupt context information on the stack memory when responding to the interrupt, and save the interrupt context information into the backup register by using the time of one clock cycle. And in the process of acquiring the entry address of the interrupt handling program and jumping to the entry address of the interrupt handling program to execute the interrupt handling program, extracting part or all of interrupt context information from the backup register and storing the information to a stack memory in parallel so as to accelerate the CPU to jump to the interrupt handling program and accelerate the response to the interrupt.

In addition, the application provides a control technology, if the interrupt context information of the backup register is invalid in the process of executing the interrupt processing program by the CPU, the CPU stores the interrupt context information in the stack memory into the backup register in advance in parallel, so that the interrupt context information can be directly recovered from the backup register when the interrupt returns, the recovery is carried out only in a period of one clock cycle, and the return of the interrupt is accelerated, so that the interrupted program is rapidly and continuously executed.

The fast response interrupt and the fast interrupt return are realized on the basis of the backup register, and the logic of parallel execution is increased. Reading and writing the backup register and the stack memory includes writing the contents of the backup register to the stack memory and reading interrupt context information on the stack memory to the backup register. The present application proposes to set a backup register when handling interrupt events, without thereby limiting the depth of interrupt nesting while accelerating interrupt responses.

Referring to fig. 8, referring to an apparatus 800 for processing an interrupt event, the apparatus 800 for processing an interrupt event includes: a first writing module 810, a first processing module 820, and a second writing module 830.

Illustratively, the first writing module 810 is configured to write first interrupt context information stored in the base register to the backup register in response to receiving an interrupt request for a first interrupt event, wherein the first interrupt context information is used to characterize the presence information of the central processing unit in the event of the first interrupt event.

Illustratively, the first processing module 820 is configured to process the first interrupt event in response to determining that writing the first interrupt context information stored in the base register to the backup register is complete.

Illustratively, the second writing module 830 is configured to write the first interrupt context information stored in the backup register to the memory in parallel during processing of the first interrupt event.

It will be appreciated that for a specific description of the interrupt event handling device 800, reference may be made to the description of the interrupt event handling method hereinabove.

Illustratively, the apparatus 800 for processing an interrupt event further includes: the device comprises a determining module, a third writing module, a second processing module, a fourth writing module and a third processing module. A determining module, configured to determine, in response to receiving an interrupt request for a second interrupt event during processing of the first interrupt event, a memory write state in which first interrupt context information stored in a backup register is written into a memory, where an event processing priority of the second interrupt event is higher than an event processing priority of the first interrupt event; a third writing module, configured to write second interrupt context information stored in the base register into the backup register when the memory writing state indicates that writing of the first interrupt context information is completed, where the interrupt context information of the second interrupt event is used to characterize field information of the central processing unit when the second interrupt event occurs; a second processing module for processing a second interrupt event in response to determining that writing the second interrupt context information stored in the base register to the backup register is complete; a fourth writing module, configured to write, in parallel, second interrupt context information stored in the backup register into the memory during processing of the second interrupt event; and the third processing module is used for returning to continue to process the first interrupt event under the condition that the second interrupt event is processed.

Illustratively, the apparatus 800 for processing an interrupt event further includes: and the fourth processing module is used for suspending processing the second interrupt event and continuing processing the first interrupt event when the writing state of the memory indicates that the writing of the first interrupt context information is not completed.

Illustratively, the apparatus 800 for processing an interrupt event further includes: and the first reading module is used for responding to the received interrupt return instruction indicating that the first interrupt event processing is completed and reading the first interrupt context information stored in the memory to the basic register.

Illustratively, the first reading module includes: the method comprises the steps of determining a sub-module, waiting the sub-module and reading the sub-module. A determination submodule for determining a memory write state in which first interrupt context information stored in the backup register is written into the memory in response to receiving an interrupt return instruction indicating that the processing of the first interrupt event is completed; a waiting sub-module, configured to wait for completion of writing of the first interrupt context information when the memory writing state indicates that the writing of the first interrupt context information is not completed; and the reading submodule is used for reading the first interrupt context information stored in the memory to the basic register under the condition that the writing of the first interrupt context information is completed.

Illustratively, the apparatus 800 for processing an interrupt event further includes: a fifth write module and a first write-back module. A fifth writing module for determining a memory writing state in which the second interrupt context information stored in the backup register is written into the memory in response to receiving an interrupt return instruction indicating that the second interrupt event processing is completed; and the first write-back module is used for stopping continuous writing and writing the second interrupt context information stored in the backup register back to the basic register when the writing state of the memory indicates that the writing of the second interrupt context information is not completed.

Illustratively, the apparatus 800 for processing an interrupt event further includes: a second read module and a second write-back module. The second reading module is used for reading the first interrupt context information stored in the memory to the backup register in parallel in the process of completing the processing of the second interrupt event and returning to continue to process the first interrupt event; and the second write-back module is used for writing back the first interrupt context information stored in the backup register into the basic register in response to receiving an interrupt return instruction indicating that the first interrupt event processing is completed.

An embodiment of the present application provides an electronic device, including a memory storing a computer program and a processor, where the processor executes the computer program to implement the steps of the method in any of the above embodiments.

Embodiments of the present application provide a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method of any of the above embodiments.

The present application provides a chip comprising a central processing unit for performing the steps of the method of any of the above embodiments. In an example, the chip may include other electronic components in addition to the central processing unit CPU. The central processing unit CPU may comprise a base register and a backup register.

An embodiment of the present application provides a computer program product comprising instructions which, when executed by a processor of a computer device, enable the computer device to perform the steps of the method of any one of the embodiments described above.

It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered as a ordered listing of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium may even be paper or other suitable medium upon which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.

It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.

In the description of the present application, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this application, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present application, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," etc. indicate orientations or positional relationships based on the orientations or positional relationships illustrated in the drawings, are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be configured and operated in a particular orientation, and therefore should not be construed as limiting the present application.

Furthermore, the terms "first," "second," and the like, as used in embodiments of the present application, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated in the present embodiment. Thus, a feature of an embodiment described herein that is termed a "first," "second," etc., may explicitly or implicitly indicate that at least one such feature is included in the embodiment. In the description of the present application, the word "plurality" means at least two or more, for example, two, three, four, etc., unless explicitly defined otherwise in the embodiments.

In this application, unless explicitly stated or limited otherwise in the examples, the terms "mounted," "connected," and "fixed" as used in the examples should be interpreted broadly, e.g., the connection may be a fixed connection, may be a removable connection, or may be integral, and it may be understood that the connection may also be a mechanical connection, an electrical connection, etc.; of course, it may be directly connected, or indirectly connected through an intermediate medium, or may be in communication with each other, or in interaction with each other. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art depending on the specific implementation.

In this application, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.

Although embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives, and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.

Claims

1. A method of handling interrupt events, the method comprising:

in response to receiving an interrupt request for a first interrupt event, writing first interrupt context information stored in a base register to a backup register, wherein the first interrupt context information is used to characterize field information of a central processing unit in the event of the first interrupt event;

processing the first interrupt event in response to determining that writing first interrupt context information stored in the base register to the backup register is complete; and

first interrupt context information stored in the backup register is written to memory in parallel during processing of the first interrupt event.

2. The method according to claim 1, wherein the method further comprises:

determining, in response to receiving an interrupt request for a second interrupt event in the process of processing the first interrupt event, a memory write state in which first interrupt context information stored in the backup register is written to the memory, wherein an event processing priority of the second interrupt event is higher than an event processing priority of the first interrupt event;

Writing second interrupt context information stored in the base register to the backup register if the memory write status indicates that the first interrupt context information write is complete, wherein the interrupt context information of the second interrupt event is used to characterize field information of the central processing unit if the second interrupt event occurs;

processing the second interrupt event in response to determining that writing second interrupt context information stored in the base register to the backup register is complete;

writing second interrupt context information stored in the backup register to the memory in parallel during processing of the second interrupt event; and

and returning to continue to process the first interrupt event under the condition that the second interrupt event is processed.

3. The method according to claim 2, wherein the method further comprises:

and suspending processing the second interrupt event and continuing processing the first interrupt event when the memory write state indicates that the first interrupt context information is not written to be completed.

4. The method according to claim 1, wherein the method further comprises:

In response to receiving an interrupt return instruction indicating that the first interrupt event processing is complete, first interrupt context information stored in the memory is read to the base register.

5. The method of claim 4, wherein the reading the first interrupt context information stored in the memory to the base register in response to receiving an interrupt return instruction indicating that the first interrupt event processing is complete comprises:

determining a memory write state in which first interrupt context information stored in the backup register is written to the memory in response to receiving an interrupt return instruction indicating that the first interrupt event processing is completed;

waiting for completion of writing of the first interrupt context information when the memory writing state indicates that the writing of the first interrupt context information is not completed; and

and reading the first interrupt context information stored in the memory to the base register when the writing of the first interrupt context information is completed.

6. The method according to claim 2, wherein the method further comprises:

determining a memory write state in which second interrupt context information stored in the backup register is written to the memory in response to receiving an interrupt return instruction indicating that the second interrupt event processing is completed; and

7. The method according to claim 2 or 6, characterized in that the method further comprises:

reading first interrupt context information stored in the memory to the backup register in parallel during the process of completing the processing of the second interrupt event and returning to continue processing the first interrupt event; and

in response to receiving an interrupt return instruction indicating that the first interrupt event processing is complete, first interrupt context information stored in the backup register is written back to the base register.

8. A method according to claim 2, 3 or 6, characterized in that:

the method further comprises the steps of: in response to receiving an interrupt request for the first interrupt event or the second interrupt event, reserving storage space in the memory for storing the first interrupt context information or the second interrupt context information;

writing the first interrupt context information or the second interrupt context information stored in the base register to the backup register includes: first interrupt context information or the second interrupt context information stored in the base register is written to the backup register within one clock cycle.

9. The method according to claim 6, wherein in the case where writing of the second interrupt context information stored in the base register to the backup register is completed, a state of the second interrupt context information stored in the backup register is set to be valid;

wherein, upon receiving an interrupt return instruction indicating that the second interrupt event processing is completed, and upon determining that the state of the second interrupt context information stored in the backup register is valid, a memory write state in which the second interrupt context information stored in the backup register is written to the memory is determined.

10. The method according to claim 9, wherein the state of the second interrupt context information stored in the backup register is set to be invalid in the case where the second interrupt event processing is completed;

and in the process of completing the second interrupt event processing and returning to continue processing the first interrupt event, in the case that the state of the second interrupt context information stored in the backup register is determined to be invalid, reading the first interrupt context information stored in the memory to the backup register in parallel, and setting the state of the first interrupt context information stored in the backup register to be valid.

11. The method of claim 2, 3 or 6, wherein the memory comprises a stacked memory; setting a push flag to a first value before writing first interrupt context information or second interrupt context information stored in the backup register to the stack memory is completed, and setting the push flag to a second value after writing the first interrupt context information or the second interrupt context information stored in the backup register to the stack memory is completed; the memory write state is characterized by the push identifier.

12. An interrupt event processing apparatus, the apparatus comprising:

a first writing module, configured to write first interrupt context information stored in a base register into a backup register in response to receiving an interrupt request for a first interrupt event, where the first interrupt context information is used to characterize field information of a central processing unit in a case where the first interrupt event occurs;

a first processing module for processing the first interrupt event in response to determining that writing of the first interrupt context information stored in the base register to the backup register is complete; and

And the second writing module is used for writing the first interrupt context information stored in the backup register into a memory in parallel in the process of processing the first interrupt event.

13. The apparatus of claim 12, wherein the apparatus further comprises:

a determining module, configured to determine, in response to receiving an interrupt request for a second interrupt event during processing of the first interrupt event, a memory write state in which first interrupt context information stored in the backup register is written into the memory, where an event processing priority of the second interrupt event is higher than an event processing priority of the first interrupt event;

a third writing module, configured to write, in a case where the memory writing state indicates that writing of the first interrupt context information is completed, second interrupt context information stored in the base register into the backup register, where the interrupt context information of the second interrupt event is used to characterize field information of the central processing unit in a case where the second interrupt event occurs;

a second processing module for processing the second interrupt event in response to determining that writing of the second interrupt context information stored in the base register to the backup register is complete;

A fourth writing module, configured to write, in parallel, second interrupt context information stored in the backup register into the memory during processing of the second interrupt event; and

and the third processing module is used for returning to continue to process the first interrupt event under the condition that the second interrupt event is processed.

14. The apparatus of claim 13, wherein the apparatus further comprises:

and the fourth processing module is used for suspending processing the second interrupt event and continuing processing the first interrupt event when the writing state of the memory indicates that the writing of the first interrupt context information is not completed.

15. The apparatus of claim 12, wherein the apparatus further comprises:

and the first reading module is used for responding to the received interrupt return instruction indicating that the first interrupt event processing is completed, and reading the first interrupt context information stored in the memory to the basic register.

16. The apparatus of claim 15, wherein the first reading module comprises:

a determining submodule for determining a memory write state in which first interrupt context information stored in the backup register is written to the memory in response to receiving an interrupt return instruction indicating that the processing of the first interrupt event is completed;

A waiting sub-module, configured to wait for completion of writing of the first interrupt context information when the memory writing state indicates that the writing of the first interrupt context information is not completed; and

and the reading submodule is used for reading the first interrupt context information stored in the memory to the basic register under the condition that the writing of the first interrupt context information is completed.

17. The apparatus of claim 13, wherein the apparatus further comprises:

a fifth writing module, configured to determine a memory writing state of writing second interrupt context information stored in the backup register into the memory in response to receiving an interrupt return instruction indicating that the second interrupt event processing is completed; and

and the first write-back module is used for stopping continuous writing and writing the second interrupt context information stored in the backup register back to the basic register when the writing state of the memory indicates that the writing of the second interrupt context information is not completed.

18. The apparatus according to claim 13 or 17, characterized in that the apparatus further comprises:

the second reading module is used for reading the first interrupt context information stored in the memory to the backup register in parallel in the process of completing the processing of the second interrupt event and returning to continue to process the first interrupt event; and

And the second write-back module is used for writing back the first interrupt context information stored in the backup register into the basic register in response to receiving an interrupt return instruction indicating that the first interrupt event processing is completed.

19. An electronic device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1-11 when the computer program is executed.

20. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1-11.

21. A chip comprising a central processing unit for performing the steps of the method of any of claims 1-11.