CN117242522A - Hybrid library latch array - Google Patents

Abstract

A Static Random Access Memory (SRAM) includes a fast SRAM bit cell and a fast multiplexer circuit formed in a first row of fast cells in a mixed standard cell architecture. The slow SRAM bit cells and the slow multiplexer circuit are formed in a second row of slow cells. The slow multiplexer circuit provides column outputs for the fast SRAM bitcells and the fast multiplexer circuit provides column outputs for the slow SRAM bitcells. Thus, one SRAM column has a fast bit cell and a slow multiplexer stage, while an adjacent SRAM column has a slow bit cell and a fast multiplexer stage, providing an improved balance of performance when reading the SRAM.

Description

Hybrid library latch array

Background

The present application relates to SRAM and SRAM bit cells. SRAM has traditionally used 6T or 8T bit cells. Because SRAM generally includes a large number of bit cells, ensuring the efficiency of SRAM bit cell area utilization is important to reduce the cost of SRAM in terms of silicon area utilized.

Disclosure of Invention

Thus, in one embodiment, a Static Random Access Memory (SRAM) includes a first plurality of bit cells and a first plurality of multiplexer circuits. The SRAM also includes a second plurality of bit cells and a second plurality of multiplexer circuits. The first plurality of bit cells is coupled to a first multiplexer circuit of the second plurality of multiplexer circuits and the second plurality of bit cells is coupled to a second multiplexer circuit of the first plurality of multiplexer circuits. The first plurality of bit cells and the first plurality of multiplexer circuits have a first performance level and the second plurality of bit cells and the second plurality of multiplexer circuits have a second performance level that is lower than the first performance level.

In another embodiment, a method for operating a Static Random Access Memory (SRAM) includes supplying a first bitcell output from a first plurality of bitcells to a first multiplexer, the first plurality of bitcells having a first performance level and the first multiplexer having a second performance level that is lower than the first performance level. The first multiplexer supplies one of the first bit cell outputs as a first multiplexer output signal from the first multiplexer. The method also includes supplying a second bitcell output from a second plurality of bitcells having a second performance level to a second multiplexer having the first performance level. The second multiplexer supplies one of the second bitcell outputs as a second multiplexer output signal.

A Static Random Access Memory (SRAM) includes a first plurality of SRAM bit cells formed from standard cells in a first row of cells having a first performance level and a first multiplexer circuit. The second plurality of SRAM bit cells and the second multiplexer circuit are formed in a second row of second cells having a second performance level lower than the first performance level. The second multiplexer circuit receives respective first outputs of the first plurality of bit cells and selects one of the respective first outputs as a second multiplexer output signal. The first multiplexer circuit receives respective second outputs of the second plurality of SRAM bit cells and selects one of the respective second outputs as a first multiplexer output signal.

Drawings

The present application may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

Fig. 1 shows an embodiment of a latch bit cell according to an embodiment.

FIG. 2 illustrates an exemplary layout of a latch bit cell.

Fig. 3 shows how different threshold voltages may be used in the read and write portions of a latch bit cell.

Fig. 4 shows a column of 32 latch bit cells.

Fig. 5 depicts a high-level block diagram of two columns each having 64 rows of latch bit cells.

FIG. 6 illustrates an embodiment of a write-masked latch bit cell.

Fig. 7 shows a layout of a latch bit cell of a write mask.

Fig. 8 illustrates another embodiment of a write-masked latch bit cell.

Fig. 9 shows an embodiment of a pulse generator generating WRZERO or WRONEX pulses.

Fig. 10 shows a layout of the latch bit cells of the write mask of fig. 8.

FIG. 11 illustrates an embodiment of a column formed from the latch bit cells of FIG. 1.

Fig. 12A shows a conventional standard cell architecture with two fins per transistor finger.

Fig. 12B shows a hybrid standard cell architecture with two fins per transistor finger and an alternating cell with one fin per transistor finger.

Fig. 12C depicts a high-level block diagram of a fin field effect transistor with one fin per transistor finger and two fins per transistor finger.

FIG. 13 illustrates an embodiment of a latch bit cell array utilizing a hybrid standard cell library.

FIG. 14 shows an embodiment of a latch bit cell array utilizing a hybrid standard cell library that provides a more balanced performance than the embodiment of FIG. 13.

FIG. 15 depicts a high-level block diagram of an embodiment of a latch bit cell array.

FIG. 16 depicts a high-level block diagram of an embodiment of a latch bit cell array using mask-written bit cells.

The use of the same reference symbols in different drawings indicates similar or identical items.

Detailed Description

In newer technology nodes, eight transistor (8T) Static Random Access Memory (SRAM) arrays are not scaled well in area. However, circuits built with standard cell design rules continue to scale relatively well in newer technology nodes. Building an SRAM array with standard cell design rules allows for smaller areas to be used even if there are more transistors. FIG. 1 shows an SRAM bitcell implemented as a latch bitcell 100 with separate read and write ports. Note that the latch bit cell 100 uses 12 transistors per bit compared to 8 transistors of an 8T SRAM bit cell, but still uses less area in some fabrication techniques due to the use of standard cell design rules. A significant difference between latch-type bitcells and classical 6T/8T SRAM bitcells is that the latch bitcells disable feedback during writing. In contrast, in a 6T/8T bit cell, the transfer gate must resist pull-up to perform the write. The latch bit cells do not have such contention during writing.

The method of fig. 1 implemented using standard cell design rules means that the overhead required to use custom SRAM macros is eliminated, thereby reducing area. For example, using standard cell layout rules allows 0 Contact Poly Pitch (CPP) (distance between transistors in the horizontal direction) to be abutted into standard cell logic. More traditional SRAM approaches have boundary cells and edge cells required for lithographic purposes. Because standard cell design rules scale well, implementing SRAM cells based on latch bit cells 100 and standard cell design rules allows SRAM designs to scale in area in the future similar to standard architectures.

The latch bit cell shown in fig. 1 distributes the local inverter normally present in the latch over more cells. The latch bit cell shown in fig. 1 removes the local inverters that would conventionally be used on inputs into the latch, including the Write Bit Line (WBL), write Word Line (WWL), active low Write Word Line (WWLX), read Word Line (RWL), and active low Read Word Line (RWLX). In more conventional latch arrays, CMOS combination stages are used between latches. Latch bit cell 100 uses the tri-state output for RBL 101. The use of tri-state drivers by latch bit cells allows the outputs (read bit lines) of several cells (e.g., 16) to be combined together using tri-state output drivers to avoid any additional combined stage of output data (such as NOR/NANDing).

Fig. 2 shows a stripe layout of a latch bit cell 100 showing 7 transistors in the horizontal direction. The box shows the source/drain connections of the transistor. The gate region of the transistor is shown as a vertical line, with the same reference numerals as the transistor in fig. 1. Long vertical line 201 indicates a shared gate connection, for example, through transistors PFBO and NFBO and transistors PINV and NINV. In the case where there is a void in the box, there is an unnamed node in fig. 1, but any unidentified source/drain connections, as well as gate connections, can be easily seen in fig. 1. The layout includes a virtual cell (DUM) transistor. The dummy transistor is a formed but unconnected transistor. The use of dummy transistors provides an efficient way of providing isolation between other transistors. The use of dummy transistors also provides the advantage of being able to vary the type of transistor used in terms of threshold voltage (Vt). In an embodiment, the write portion of the latch (transistors PPG, NPG, PINV, NINV, NFB1, NFB0, PFB0, and PFB 1) does not require high performance, but the read portion of the latch (transistors PRP1, PRP0, NRP0, and NRP 1) does. Note that the first letter of the transistor name refers to the type of transistor (N or P), and the remaining letters refer to its function (PG: transmission gate, INV: inverter, FB: feedback, RP: read port)

Referring to fig. 3, it allows the read portion 301 of the latch bit cell 100 including transistors PRP0, PRP1, NRP0, and NRP1 to be implemented using lower Vt (such as ultra low Vt (uvt)) transistors, providing the required high performance, while the write portion 303 of the latch bit cell 100 on the left side of the virtual transistor in fig. 3 is implemented with higher threshold voltage transistors such as low Vt (lvt) transistors. Higher Vt transistors provide lower performance but also cause less leakage and are utilized only if performance is needed. Thus, the layout option allows for different threshold voltages to be utilized on the read and write ports with different performance requirements, allowing for reduced leakage current as compared to having to use lower Vt devices of all devices to meet the performance requirements of only a portion of the bitcell. Transistors in the read and write ports share diffusion between adjacent cells, where xtor (transistor) loading may be halved compared to non-optimal designs.

Referring back to FIG. 1, the operation of latch bit cell 100 will now be described. The data to be written to the cells on write bit line WBL 102, also referred to herein as Write Data (WD), is supplied to a transfer gate 103 formed from transistors NPG and PPG. The gate or transistors are coupled to a Write Word Line (WWL) and a Write Word Line X (WWLX), respectively, where "X" indicates that the signal is active low. When WWL and WWLX are asserted, the data on WBL is passed as data "D" into inverter 104 formed by transistors PINV and NINV. When WWL and WWLX are asserted, transistors NFB1 and PFB1 are turned off. The gates of NFB0 and PFB0 in the feedback portion of bit latch cell 100 receive the output d_x from the inverter ("inverted value of D"). The gates of PRP1 and NRP1 in the read portion 106 of the latch also receive D_X. When WWL and WWLX are de-asserted, transmission gate 103 is off and transistors NFB1 and PFB1 are on, allowing d_x to turn on one of transistors NFB0 or PFB0 to supply "D" as a feedback signal. Transistors NFB1, NFB0, PFB0, and PFB1 act as keeper circuits 108 and, along with the inverters formed by transistors PINV and NINV, ensure that the data on node D is maintained when WWL and WWLX are de-asserted. In this way, the value of D is maintained in the write portion of latch bit cell 100 and is available when the latch is read. In latch bit cell 100, PMOS transistors PINV, PFB1, and PRP1 are coupled at their sources to a supply Voltage (VDD). The NMOS transistors NINV, NFB1 and NRP1 are coupled at their sources to a second supply voltage (ground).

To read the latch bit cell, read Word Lines (RWL) and RWLX assertions turn on NRP0 and PRP0, respectively. Bearing in mind that "X" indicates an active low signal. Assertion of RWL and RWLX allows the value of D_X to determine the value of output signal Read Bit Line (RBL) 101, which is also referred to herein as Read Data (RD). When RWL and RWLX are de-asserted, the RBL is set to a high impedance to allow other SRAM cells to drive the RBL when other SRAM cells are selected for reading.

FIG. 4 shows an embodiment in which a set of 32 latch bit cells is formed in two sets of latch bit cells (bits <31:16> and bits <15:0 >). Each set of latch bit cells supplies bits to multiplexer 401, which selects bits from bits <31:16> or bits from bits <15:0> and supplies the selected bits on rdData 403. In the implementation of fig. 4, the tri-state drivers on the read side of the latch bit cell allow 16 bits (only one bit at a time to be valid) to drive the same RBL supplied to multiplexer 401. Thus, only one RWL/RWLX is turned on at a time in each of the packets [31:16] and [15:0] to ensure that the RBL is not driven by multiple latch bit cells at the same time, otherwise a high current condition would be caused. It is also important to ensure that one of the RWL/RWLX signals is active, causing one of the bit cells to drive a high or low logic level onto the RBL. The deassertion of all RWL/RWLX pairs will result in a floating node on the RBL, which can cause high current draw in the downstream CMOS gates receiving intermediate signals between VDD and VSS.

Fig. 5 shows a block diagram of an embodiment with 64 rows of bit cells and two columns, and a multiplexer 501 selects one bit from the 64 rows and two columns. Although not shown in fig. 5 for ease of illustration, the implementation shown in fig. 5 also requires a write column multiplexer function. One way to achieve this is to supply a WWL/WWLX pair to even physical columns and another WWL/WWLX pair to odd physical columns. In this way every other cell can be written. Another way to implement the write multiplexer function is to use a write mask as described further herein.

During a write operation, when a word line of a particular word line is asserted, all bits in the word line may change state. Instead of changing the state of all bits in a word line, it may be advantageous to only write to selected cells of the word line, which helps make the write operation more efficient. Thus, in another embodiment shown in fig. 6, latch bitcell 600 includes a write mask. The write mask writes an X (WRONEX) and a zero (WRZERO) with signals, where "X" indicates that the signal is active low. The write mask circuit is formed by transistors PWD 601 and NWD 603, where WD represents write data. When WRONEX is asserted (active low), the Write Data (WD) node is pulled high through transistor PWD, and when WRZERO is asserted, the WD node is pulled low through transistor NWD. The write mask allows the write word line for a row of cells to be asserted without changing the state in all of the cells. For example, only one byte or a few bits on a word line may be changed by asserting the word line and using a write mask to ensure that only those cells of interest are written. In addition to transistors PWD and NWD for determining the value of WD, the write-masked latch bit cell 600 also includes transistors NFB2 and PFB2 used in the keeper circuit 605. Those transistors are used to ensure that the feedback function of the keeper circuit continues to operate, so the latch bit cell remains in state even when WWL and WWLX are asserted. NFB1 is turned off if WWLX is asserted, and PFB1 is turned off if WWL is asserted. Transistors NFB2 and PFB2 ensure that if the bit has a write mask that actually blocks the writing of the latch bit cell, then the keeper circuit remains driving "D" with the correct value from the node between NFB0 and PFB0 when WWL and WWLX are asserted. Note that WD will float when WRONEX and WRZERO are de-asserted. By incorporating the PWD and NWD transistors into the bitcell itself, the capacitance on the intermediate node WD remains low enough to avoid cell stability issues when WWL/WWLX is asserted. In fig. 6, the Keeper Stack (KSTK) nodes PKSTK 602 and NKSTK 604 are labeled.

Fig. 7 shows a simplified diagram of a layout of the write-masked latch bit cell 600 shown in fig. 6. Note that the solution of fig. 6 increases the cell size by four transistors and includes additional dummy cells compared to the layout shown in fig. 2. Thus, compared to the layout of FIG. 2 (7 CPP) of latch bit cell 100 shown in FIG. 1, latch bit cell 600 (FIG. 6) with a write mask shows an increase in 3CPP to 10CPP.

Fig. 8 shows a more efficient implementation of the write-masked latch bit cell 800 as compared to the write-masked latch bit cell 600 of fig. 6. Note that the additional transistors NFB2 and PFB2 coupled to the keeper stack node in the write-masked latch bit cell 600 replace NFB1 and PFB1 in the write-masked latch bit cell 800. When WWL and WWLX are asserted (see fig. 1 and 6), the write-masked latch bit cell 800 does not disable the keeper circuit 805 by turning off NFB1 and PFB1, but rather, the write-masked latch bit cell 800 disables the keeper only in response to WRONEX or WRZERO being asserted. This ensures that the latch bit cell 800 remains in state in the event that the latch bit cell 800 is masked. Note that WWL and WWLX are coupled only to pass gate transistors PPG and NPG in the write masked latch bit cell 800. When WRONEX is asserted (active low), transistor NFB2 is turned off, and when WRZERO is asserted, transistor PFB2 is turned off. Assuming WWLX and WWL are asserted, node WD goes high and node D goes high when WRONEX is asserted, and node WD goes low and node D goes low when WRZERO is asserted (active low). When the respective mask lines (WRONEX and WRZERO) are de-asserted, both NFB2 and PFB2 are turned on and the keeper circuit maintains the value of node D according to the value of D_X provided by the inverter formed by transistors PINV and NINV. D_X turns on transistor NFB0 to maintain a low value of node D or PFB0 to maintain a high value of node D. The write mask circuit is formed by transistors PWD 801 and NWD 803 and is similar to the embodiment shown in fig. 6. The read side of the write masked latch bit cell 800 formed by transistors PRP1, PRP0, NRP0, and NRP1 is the same as in the previous latch bit cell implementations 100 and 600 shown in fig. 1 and 6, respectively.

Each bit cell in the column coupled to WRONEX and WRZERO will have its keeper circuit disabled whenever WRONEX or WRZERO is asserted because WRONEX is asserted to turn off NFB2, preventing d_x from being pulled to VSS through NFB0 and NFB2, and WRZERO is asserted to turn off PFB2, preventing d_x from being pulled to BDD through PFB0 and PBF 2. Thus, node D will float in response to the assertion of WRONEX or WRZERO. If the assertion of WRONEX or WRZERO is long enough, the cells along the column may change state because at least a portion of the keeper circuit is turned off as NFB1 or PFB1 is disabled by the assertion of WRONEX or WRZERO. Therefore, WRONEX and WRZERO should be asserted as pulse writes. Thus, those signals should be asserted as self-timed pulses with several inverters delayed by a long period (e.g., 50 ps). The pulses may be generated using, for example, 9 inverters. The number of inverters depends on the technology used. Fig. 9 shows an embodiment of a pulsing circuit 901 for WRZERO and a pulsing circuit 903 for WRONEX. Note that an odd number of inverters are used in each of the pulse circuits shown in fig. 9. In fig. 9, the inputs to the logic gates (write zeros and write ones) are assumed to be active high. Many other pulse generator circuits that provide suitable pulse widths for WRONEX and WRZERO are known to those skilled in the art. The pulse should be long enough to write one cell, but short enough so that other cells along the column do not lose state due to node D floating during the pulse, and therefore there is a relatively small area penalty for additional write mask capability compared to the write masked latch bit cell shown in fig. 6.

Fig. 10 shows an exemplary layout of the circuit of fig. 8. Note that latch bit cell 800 requires only one dummy transistor. The layout of latch bit cell 800 shown in FIG. 10 has only one additional CPP compared to the baseline latch bit cell 100 shown in FIG. 2.

FIG. 11 shows a column of the latch array of the latches shown in FIG. 1 formed in a single standard cell row. Note that the term "single standard cell row" refers to a physical row of an integrated circuit rather than a logical row of SRAM. In standard designs with non-mixed standard cell library rules, all devices typically have the same number of fins. In a conventional standard cell architecture, the devices of all rows have the same height. In the field of fin field effect transistors, this also generally means that each finger has the same number of fins. Fig. 12A shows a conventional standard cell architecture for PFETs and NFETs with 2 fins per finger. Each standard cell is identical in row and has P and N transistors.

Hybrid standard cell architectures utilize alternating high performance standard cell rows and high density (but lower performance) standard cell rows. For example, in one embodiment, this means that each transistor finger of a high performance cell has two fins, and each transistor finger of a lower performance cell has one fin. This results in alternating higher and shorter cell rows and shorter rows, as shown in fig. 12B. The advantage of the hybrid standard cell architecture is smaller area and reduced power, but the shorter cell height results in reduced performance compared to the larger two-fin cell. Fig. 12C shows one fin per transistor finger device 1201 and two fins per transistor finger device 1203.

FIG. 13 illustrates that transitioning from a conventional standard cell library to a hybrid standard cell library approach to construct a standard cell latch array can result in unbalanced performance between adjacent bits. For example, the bit cells in column 1301 are formed of "fast" standard cells, e.g., each finger has two fins. In the illustrated embodiment, the logical SRAM column 1301 is in a physical fast row of a hybrid row architecture. The bit cells in column 1303 are "slow" cells, for example, with one fin per finger. Thus, reading Rddata [1]1302 from one of the bit cells in column 1301 occurs faster than reading Rddata [0]1304 from column 1302. Thus, adjacent bits are read at different timings (one fast and one slow), which is undesirable.

To provide a more balanced performance between fast and slow cells, the implementation shown in fig. 14 uses a set of bit cells from one column, such as bit cells in columns 1401 (fast physical row) or 1403 (slow physical row), but uses a multiplexer circuit from the other row. For example, slow multiplexer 1407 selects one bit from the 32 fast bit cells. The 32 fast bit cells are fast bit cell 1404 (bits <15:0>, only one of which is shown) and fast bit cell 1406 (bits <31:16>, only one of which is shown). Fast multiplexer 1415 selects one bit from the 32 slow bit cells. The 32 slow bit cells are slow bit cell 1409 (bits <15:0>, only one of which is shown) and slow bit cell 1411 (bits <31:16>, only one of which is shown). Similarly, fast bit cells 1421 and 1423 use slow multiplexer 1425, while slow bit cells 1427 and 1429 use fast multiplexer 1431. The read data (Rddata [1 ]) supplied by the fast multiplexer 1435 has a fast multiplexer (2-fin) but has slow bit cells (1-fin), and the read data (Rddata [0 ]) has a slow multiplexer (1-fin) but has fast bit cells (2-fin). Thus, one logical SRAM column has fast bit cells and slow multiplexer stages, while an adjacent SRAM logical column has slow bit cells and fast multiplexer stages. With significantly different timing than every other bit: this provides an improved balance of performance compared to a fast and slow array.

Fig. 15 depicts a high-level block diagram of a bit cell array. Although fig. 14 shows the latch bit cell of fig. 1 being used as a bit cell in columns 1401 and 1403, in other implementations, other bit cells may be used. Fig. 16 shows an embodiment in which the masked-written latch bit cell 600 of fig. 6 or the masked-written latch bit cell 800 of fig. 8 is utilized. Fig. 16 shows mask signals WRONEX and WRZERO signals allocated to bit cells.

Thus, a hybrid cell standard cell architecture has been described with alternating high performance standard cell rows and high density standard cell rows, with bit cells and multiplexing stages alternating to provide a more balanced read timing. The description of the application set forth herein is illustrative and is not intended to limit the scope of the application as set forth in the following claims. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein without departing from the scope of the application as set forth in the following claims.

Claims (19)

1. A Static Random Access Memory (SRAM), comprising:

a first plurality of bit cells and a first plurality of multiplexer circuits;

a second plurality of bit cells and a second plurality of multiplexer circuits;

wherein the first plurality of bit cells is coupled to a first multiplexer circuit of the second plurality of multiplexer circuits;

wherein the second plurality of bit cells is coupled to a second multiplexer circuit of the first plurality of multiplexer circuits; and is also provided with

Wherein the first plurality of bit cells and the first plurality of multiplexer circuits have a first performance level and the second plurality of bit cells and the second plurality of multiplexer circuits have a second performance level that is lower than the first performance level.

2. The SRAM of claim 1, wherein the SRAM comprises alternating rows of first cells having the first performance level and second cells having the second performance level.

3. The SRAM of claim 1 or 2, further comprising:

a third plurality of bitcells having the first performance level;

a fourth plurality of bit cells having the second performance level;

wherein the third plurality of bit cells is coupled to a third multiplexer circuit of the second plurality of multiplexer circuits; and is also provided with

Wherein the fourth plurality of bit cells is coupled to a fourth multiplexer circuit of the first plurality of multiplexer circuits.

4. An SRAM according to claim 3,

wherein the first multiplexer circuit and the third multiplexer circuit are coupled to a fifth multiplexer circuit of the second plurality of multiplexer circuits; and is also provided with

Wherein the second multiplexer circuit and the fourth multiplexer circuit are coupled to a sixth multiplexer circuit of the first plurality of multiplexer circuits.

5. The SRAM of claim 1 or 2, wherein the first performance level is determined at least in part from a first number of fins per transistor finger and the second performance level is determined at least in part from a second number of fins per transistor finger, and the first number of fins is greater than the second number of fins.

6. The SRAM of claim 5, wherein the first number of fins is two and the second number of fins is one.

7. The SRAM of claim 1 or 2, wherein the first plurality of bit cells forms at least a portion of a first column of the SRAM and the second plurality of bit cells forms at least another portion of a second column of the SRAM.

8. The SRAM of claim 7, wherein the first column and the second column are adjacent in the SRAM.

9. The SRAM of claim 7, wherein each of the first plurality of bit cells and the second plurality of bit cells is a latch bit cell.

10. The SRAM of claim 7, wherein each of the first plurality of bit cells and the second plurality of bit cells is a write-masked bit cell.

11. A method for operating a Static Random Access Memory (SRAM), comprising:

supplying a first bitcell output from a first plurality of bitcells having a first performance level to a first multiplexer having a second performance level, the second performance level being lower than the first performance level;

supplying one of the first bitcell outputs as a first multiplexer output signal from the first multiplexer;

supplying a second bitcell output from a second plurality of bitcells having the second performance level to a second multiplexer having the first performance level; and

one of the second bitcell outputs is supplied as a second multiplexer output signal.

12. The method of claim 11, further comprising:

supplying a third bit cell output from a third plurality of bit cells having the first performance level to a third multiplexer having the second performance level and a third multiplexer output signal; and

a fourth bit cell output from a fourth plurality of bit cells having the second performance level is supplied to a fourth multiplexer having the first performance level and a fourth multiplexer output signal is supplied.

13. The method according to claim 12,

supplying the first and third multiplexer output signals to a fifth multiplexer circuit having the second performance level and a fifth multiplexer output signal;

supplying the second and fourth multiplexer output signals to a sixth multiplexer circuit having the first performance level and a sixth multiplexer output signal;

supplying the fifth multiplexer output signal as read data bits from the first SRAM column; and

the sixth multiplexer output signal is supplied as another read data bit from a second SRAM column adjacent to the first SRAM column.

14. The method of any of claims 11 to 13, wherein the first performance level is determined at least in part from a first number of fins per transistor finger and the second performance level is determined at least in part from a second number of fins per transistor finger, and the first number of fins is greater than the second number of fins.

15. The method of claim 14, wherein the first number of fins is two and the second number of fins is one.

16. The method of any of claims 11 to 13, further comprising supplying the first bitcell output from a first writemask bitcell and the second bitcell output from a second writemask bitcell.

17. A Static Random Access Memory (SRAM), comprising:

a first plurality of SRAM bit cells and a first multiplexer circuit formed in a first row of first cells having a first performance level;

a second plurality of SRAM bit cells and a second multiplexer circuit formed in a second row of second cells having a second performance level lower than the first performance level;

wherein the second multiplexer circuit is coupled to receive respective first outputs of the first plurality of bit cells and to select one of the respective first outputs as a second multiplexer output signal; and is also provided with

Wherein the first multiplexer circuit is coupled to receive respective second outputs of the second plurality of SRAM bit cells and to select one of the respective second outputs as a first multiplexer output signal.

18. The Static Random Access Memory (SRAM) of claim 17, wherein the first plurality of SRAM bit cells and the second plurality of SRAM bit cells are in adjacent SRAM columns.

19. The Static Random Access Memory (SRAM) of claim 17 or 18, further comprising:

a third plurality of bit cells in the first row having the first performance level;

a fourth plurality of bit cells in the second row having the second performance level; and is also provided with

Wherein the third plurality of bit cells is coupled to a third multiplexer circuit in the second row and the fourth plurality of bit cells is coupled to a fourth multiplexer circuit in the first row.