CN117220649B - Latch for high speed one-by-eight multiplexer - Google Patents
Latch for high speed one-by-eight multiplexer Download PDFInfo
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- CN117220649B CN117220649B CN202311468624.1A CN202311468624A CN117220649B CN 117220649 B CN117220649 B CN 117220649B CN 202311468624 A CN202311468624 A CN 202311468624A CN 117220649 B CN117220649 B CN 117220649B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a latch for a high-speed eight-selection multiplexer, which comprises a plurality of groups of latch units, wherein each latch unit comprises four latch modules, each latch module comprises two latch units, each latch unit comprises five transistors and an inverter, the grid electrodes of the first transistor and the second transistor receive one input clock signal, the source electrode of the first transistor is connected with a power supply end, the source electrode of the second transistor is connected with the drain electrodes of the third transistor and the fourth transistor, the grid electrode of the third transistor receives input data, the source electrode of the third transistor is grounded, the grid electrode of the fourth transistor receives another input clock signal, the source electrode of the fourth transistor is grounded, the drain electrodes of the first transistor and the second transistor are both connected with the drain electrodes of the fifth transistor and the input end of the inverter, the grid electrode of the fifth transistor receives another input clock signal, the source electrode of the fifth transistor is connected with the power supply end, and the drain electrode of the fifth transistor is connected with the input end of the inverter; the two latch cell outputs of each latch module are connected together. The invention can realize better performance.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly to a latch for a high-speed one-eighth multiplexer.
Background
In high-speed SerDes circuit applications, a high-speed latch connected to a driver or Digital-to-Analog Converter (DAC) is one of the core blocks of a Transmitter (TX), which typically employs a half-speed architecture and a quarter-speed architecture and is implemented by 2:1 or 4: the multiplexer of the 1 input mode generates baud rate data and is connected to a driver or DAC. With the higher demands on SerDes speeds by data interconnection and transmission, there is also a higher demand on clock speed, however, because of the complexity of the high speed clock transmission scheme, inadequate time margin, high power consumption, and jitter amplification, selecting a more multiplexed multiplexer is more attractive than high speed clocks, and thus in single channel 200Gbps four-level pulse amplitude modulation (PAM 4, 4 Pulse Amplitude Modulation) and higher speed applications, an eighth rate and architecture that produces full rate data by an eighth rate multiplexer comes with. Conventional multiplexers have a large self-loading due to process limitations resulting in insufficient bandwidth and large intersymbol interference (ISI, inter-Symbol Interference), which greatly affects the performance of the high-speed driver or DAC.
Disclosure of Invention
In view of the shortcomings of the prior art, the present invention provides a latch for a high-speed one-by-one multiplexer by which eight ways of data timing alternation is implemented in a high-speed driver or DAC, improving performance of the high-speed driver or DAC in single channel 200gbps PAM4 and higher applications. The latch can increase the rising and falling speed of data transmitted to a driver or a DAC so as to reduce ISI and jitter amplification and realize better performance; the latch adopts an eight-one architecture, so that the speed on a clock path is reduced, and better power consumption and jitter of the clock path are realized.
A latch for a high speed one-by-one multiplexer, comprising: several sets of latch units, each latch unit comprising four latch modules, each latch module comprising two latch units, each latch unit comprising: the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the source electrode of the fourth transistor, the source electrode of the fifth transistor, the drain electrode of the fourth transistor, the drain electrode of the fifth transistor, the input end of the inverter, the first to fifth transistors, the gate electrode of the first to fifth transistors, the drain electrode of the first and second transistors, the drain electrode of the fifth transistor, the input end of the inverter, the source electrode of the fifth transistor, the drain electrode of the fifth transistor, the input end of the inverter;
the outputs of the two latch units of each latch module are connected together.
Further, the four latch modules are a first latch module, a second latch module, a third latch module and a fourth latch module respectively;
in the first latch module, gates of first and second transistors of a first latch unit receive a θ° input clock signal, and gates of fourth and fifth transistors receive a θ+135° input clock signal; gates of the first and second transistors of the second latch unit receive the θ+180° input clock signal, and gates of the fourth and fifth transistors receive the θ+315° input clock signal;
in the second latch module, gates of the first and second transistors of the first latch unit receive a θ+45° input clock signal, and gates of the fourth and fifth transistors receive a θ+180° input clock signal; gates of the first and second transistors of the second latch unit receive the θ+225° input clock signal, and gates of the fourth and fifth transistors receive the θ° input clock signal;
in the third latch module, gates of the first and second transistors of the first latch unit receive a θ+90° input clock signal, and gates of the fourth and fifth transistors receive a θ+225° input clock signal; gates of the first and second transistors of the second latch unit receive a θ+270° input clock signal, and gates of the fourth and fifth transistors receive a θ+45° input clock signal;
in the fourth latch module, gates of the first and second transistors of the first latch unit receive a θ+135° input clock signal, and gates of the fourth and fifth transistors receive a θ+270° input clock signal; gates of the first and second transistors of the second latch unit receive a θ+315° input clock signal, and gates of the fourth and fifth transistors receive a θ+90° input clock signal;
when the input clock signal calculated according to the rule is equal to or greater than 360 DEG, the actually received input clock signal is the calculated input clock signal minus 360 DEG, wherein θ is any clock of 0, 45, 90, 135, 180, 225, 270, 315.
Further, in the first latch module, a gate of a third transistor of the first latch unit receives first parallel data, and a gate of a third transistor of the second latch unit receives fifth parallel data;
in the second latch module, a gate of a third transistor of the first latch unit receives second parallel data, and a gate of a third transistor of the second latch unit receives sixth parallel data of input data;
in the third latch module, a gate of a third transistor of the first latch unit receives third parallel data, and a gate of a third transistor of the second latch unit receives seventh parallel data;
in the fourth latch module, a gate of the third transistor of the first latch unit receives fourth parallel data, and a gate of the third transistor of the second latch unit receives eighth parallel data.
Further, the first transistor and the fifth transistor are PMOS transistors, and the second transistor, the third transistor, and the fourth transistor are NMOS transistors.
Further, the inverter realizes a signal output converting the signal a generated by the first to fifth transistors into a rail-to-rail signal.
Further, the turn-on of the second transistor, the third transistor, and the fifth transistor forms a pre-discharge to the signal a.
Further, the rising edge of the input clock signal clk_2 of the fifth transistor gate triggers the rising edge of the output pulse signal Data, and the falling edge of the input clock signal clk_1 of the first and second transistor gates triggers the falling edge of the output pulse signal Data.
Compared with the prior art, the invention has at least the following beneficial effects:
first, the latch for a high-speed eight-select multiplexer of the present invention implements a Unit Interval (UI) pulse of different timings and sequentially feeds into a driver or DAC, greatly reducing ISI of data output from each latch module.
Second, the high speed clock frequency on the clock path is greatly reduced using an eighth rate architecture and through an eighth-by-one multiplexer to achieve more adequate time margin, better power consumption and jitter on the clock path.
Thirdly, the high-speed latch module adopts a pre-charge and discharge mode, so that the rising and falling time of the output data of the latch module is improved, the ISI of the data is reduced, and good performance in higher-speed application can be realized.
Drawings
FIG. 1 is a schematic diagram of a high-speed one-eighth multiplexer for unit bits in one embodiment of the present application.
FIG. 2 is a circuit diagram of a latch module in one embodiment of the present application.
FIG. 3 is a timing diagram of a first latch module according to one embodiment of the present application.
FIG. 4 is a timing diagram of an eighth multiplexer according to one embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be understood by those skilled in the art that the claimed invention may be practiced without these specific details and with various changes and modifications from the embodiments that follow.
In the present application, a number of technical features are described in the specification, and are distributed in each technical solution, which makes the specification too lengthy if all possible combinations of technical features (i.e. technical solutions) of the present application are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the present application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.
It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.
The multiplexer is one of the core modules that generates full rate data in the high speed SerDes TX. The present application discloses a latch for a high-speed one-eighth multiplexer, the multiplexer implementation schematic diagram is shown with reference to fig. 1, which illustrates a high-speed one-eighth multiplexer 100 of unit bits, comprising: a latch unit 101, and a driver or DAC 102 connected to the latch unit 101. Wherein the latch unit 101 includes four latch modules for generating four-way 1UI pulses with alternating timings, and one latch unit 101 alternately opens and closes four input switches in the driver or DAC 102 corresponding to one driver or DAC 102,1UI pulse.
Referring to fig. 2, each latch module includes:
the first to fifth transistors M1 to M5 and the inverter, wherein the gates of the first transistor M1 and the second transistor M2 receive one input clock signal, the source of the first transistor M1 is connected with the power supply terminal, the source of the second transistor M2 is connected with the drains of the third transistor M3 and the fourth transistor M4, the gate of the third transistor M3 receives input data, the source of the third transistor M3 is grounded, the gate of the fourth transistor M4 receives the other input clock signal, the source of the fourth transistor M4 is grounded, the drains of the first transistor M1 and the second transistor M2 are both connected with the drain of the fifth transistor M5 and the input terminal of the inverter, the gate of the fifth transistor M5 receives the other input clock signal, and the source of the fifth transistor M5 is connected with the power supply terminal, and the drain of the fifth transistor M5 is connected with the input terminal of the inverter.
In one embodiment, in the first latch module, gates of the first transistor M1 and the second transistor M2 of the first latch unit receive the 0 ° input clock signal, gates of the fourth transistor M4 and the fifth transistor M5 receive the 135 ° input clock signal, gates of the first transistor M1 and the second transistor M2 of the second latch unit receive the 180 ° input clock signal, and gates of the fourth transistor M4 and the fifth transistor M5 receive the 315 ° input clock signal; in the second latch module, gates of the first transistor M1 and the second transistor M2 of the first latch unit receive the 45 ° input clock signal, gates of the fourth transistor M4 and the fifth transistor M5 receive the 180 ° input clock signal, gates of the first transistor M1 and the second transistor M2 of the second latch unit receive the 225 ° input clock signal, and gates of the fourth transistor M4 and the fifth transistor M5 receive the 0 ° input clock signal; in the third latch module, gates of the first transistor M1 and the second transistor M2 of the first latch unit receive the 90 ° input clock signal, gates of the fourth transistor M4 and the fifth transistor M5 receive the 225 ° input clock signal, gates of the first transistor M1 and the second transistor M2 of the second latch unit receive the 270 ° input clock signal, and gates of the fourth transistor M4 and the fifth transistor M5 receive the 45 ° input clock signal; in the fourth latch module, gates of the first transistor M1 and the second transistor M2 of the first latch unit receive the 135 ° input clock signal, gates of the fourth transistor M4 and the fifth transistor M5 receive the 270 ° input clock signal, gates of the first transistor M1 and the second transistor M2 of the second latch unit receive the 315 ° input clock signal, and gates of the fourth transistor M4 and the fifth transistor M5 receive the 90 ° input clock signal.
In one embodiment, in the first latch module, the gate of the third transistor M3 of the first latch unit receives the input data D <0>, and the gate of the third transistor M3 of the second latch unit receives the input data D <4>; in the second latch module, the gate of the third transistor M3 of the first latch unit receives the input data D <1>, and the gate of the third transistor M3 of the second latch unit receives the input data D <5>; in the third latch module, the gate of the third transistor M3 of the first latch unit receives the input data D <2>, and the gate of the third transistor M3 of the second latch unit receives the input data D <6>; in the fourth latch module, the gate of the third transistor M3 of the first latch unit receives the input data D <3>, and the gate of the third transistor M3 of the second latch unit receives the input data D <7>.
With continued reference to fig. 2, the two latch cell outputs within a latch module are connected together.
In one embodiment, the first transistor M1 and the fifth transistor M5 are PMOS transistors, and the second transistor M2, the third transistor M3, and the fourth transistor M4 are NMOS transistors. When the input data is 1, the latch module circuit generates a pulse signal with output logic 1 and voltage of power supply voltage VDD, and when the input data is 0 or no pulse signal, generates a pulse signal with output logic 0 and voltage of ground voltage GND, and the output signal with the characteristic is sent to an NMOS driver or DAC.
In fig. 2, 8T data is sent to 4 different latch modules, in each of which clk_1 and clk_2 in each latch cell trigger a 1UI pulse accordingly. To increase 1UI speed and reduce ISI in higher speed applications, data a uses a pre-discharge technique where the level is pre-reduced before the 1UI pulse is generated to increase the subsequent 1UI pulse rise time, and the presence of transistor M4 also causes data a to discharge faster, allowing the 1UI pulse rise time to be faster. To reduce the output performance impact caused by the phase offset between eight-phase clocks, an eight-phase clock with phase calibration is required here.
FIG. 3 is a timing diagram of the latch module in one embodiment of the present application, describing the pre-discharge technique and how the rising edge of clk_2 and the falling edge of clk_1 generate 1UI pulses, here illustrated as a first latch module. Wherein clk_1 received by the gates of the first and second transistors M1 and M2 of the first latch unit is a 0 ° input clock signal, clk_2 received by the gates of the fourth and fifth transistors M4 and M5 is a 135 ° input clock signal, and the gate of the third transistor M3 receives input data D <0>. When the data D <0> is 1, clk_1 is 1, and clk_2 is 0, the data A <0> is pre-discharged, and then 0 is output through the inverter; when clk_1 is 1 and clk_2 is also 1, data A <0> discharges to 0, outputting 1 through the inverter; when clk_1 is 0 and clk_2 is 1, data A <0> charges to 1, outputting 0 through the inverter; when clk_1 and clk_2 are both 0, data a <0> remains unchanged at 1, outputting 0 through the inverter. The rising edge of clk_2 (135 °) determines one side of Data <0> (D0), and the falling edge of clk_1 (0 °) determines the other side of Data <0> (D0), thereby generating Data <0> (D0). In the second latch unit, clk_1 received by the gates of the first transistor M1 and the second transistor M2 is a 180 ° input clock signal, clk_2 received by the gates of the fourth transistor M4 and the fifth transistor M5 is a 315 ° input clock signal, and the gate of the third transistor M3 receives the input data D <4>. The rising edge of clk_2 (315 °) determines one side of Data <0> (D4), and the falling edge of clk_1 (180 °) determines the other side of Data <0> (D4), thereby generating Data <0> (D4). The Data <0> is sent to one input switch of the driver or DAC 102. It should be appreciated that the timing diagrams of the other latch modules may be similarly and respectively generate Data <1:3> to be sent to the remaining three input switches of the driver or DAC 102. FIG. 4 is a timing diagram of an eighth multiplexer according to one embodiment of the present application.
All documents mentioned in the present specification are considered to be included in the disclosure of the present application as a whole, so that they may be regarded as a basis for modification if necessary. Furthermore, it should be understood that the foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present disclosure, is intended to be included within the scope of one or more embodiments of the present disclosure.
Claims (6)
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