CN117219654B - High-voltage grid driving circuit and preparation method thereof - Google Patents

Abstract

The application discloses high-voltage gate drive circuit and preparation method thereof, high-voltage gate drive circuit includes: a substrate of a first doping type; a first buried layer of a second doping type located on the substrate; an epitaxial layer of a first doping type on the substrate and the first buried layer, the epitaxial layer including a high-side drive circuit region, a low-side drive circuit region, and a level shift circuit region, the level shift circuit region including at least a high-voltage LDMOS device; and a high-voltage isolation island and an isolation structure, the high-side drive circuit region and the low-side drive circuit region being isolated via the high-voltage isolation island, the level shift circuit region and the high-side drive circuit region being isolated via the isolation structure. The high-voltage grid driving circuit has higher breakdown voltage and isolation voltage, reduces reliability risks such as high-voltage overline and the like, requires fewer photoetching layers and simpler working procedures in the process, and reduces production cost.

Description

A high-voltage gate drive circuit and preparation method thereof

Technical field

The invention relates to the field of semiconductor technology, and in particular to a high-voltage gate drive circuit and a preparation method thereof.

Background technique

According to industry standards, BCD (Bipolar-CMOS-DMOS technology) is generally divided into high-voltage BCD, high-density BCD (emphasis on reduced line width of control logic), and high-power BCD (emphasis on the output of large currents of key power tubes). Among them, high-voltage BCD technology is generally used in HVIC (High Voltage Integrated Circuit), which refers to BCD technology with a withstand voltage above 100V. It is currently widely used in AC-DC power supplies, LED drivers, high-voltage gate drivers (motor drivers), etc. In general applications, the withstand voltage of power devices is required to reach 500V to 800V.

When HVIC is used in high-voltage gate drive circuits, it is mainly used to drive motors. The typical topology is half-bridge drive. The high-voltage gate drive circuit includes a low-side drive circuit area and a high-side drive circuit area. The high-side drive circuit The area requires level shifting technology to achieve floating driving on the high side. The level shift circuit area is generally implemented using high-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor, lateral double-diffused metal oxide semiconductor) devices. The drain end of the high-voltage LDMOS device usually requires a high-voltage jumper (HVI) to the high-side drive circuit area. This leads to problems with high-voltage crossover lines. In order to solve this problem, three generations of technology have been mainly developed in high-voltage gate drive circuits. Figures 1a to 1c show schematic structural diagrams of three generations of isolation structures of high-voltage gate drive circuits. Figure 1a shows a schematic diagram of a first-generation conventional isolation structure; Figure 1b shows a schematic diagram of a second-generation self-isolation structure. ; Figure 1c shows a schematic diagram of the third-generation partitioned RESURF (Divided RESURF) isolation structure. At present, these three isolation structures have been applied.

However, the above three isolation structures are all based on the ordinary lateral PN junction isolation of bulk silicon. In practical applications, there will be reliability problems such as high-voltage cross-lines and parasitic effects.

In addition, with the iteration of products, the requirements for switching speed, area and efficiency are getting higher and higher. How to use fewer photolithography levels and lower costs to achieve the above goals and obtain better performance is the development of HVIC. Main trends.

Contents of the invention

In view of the above problems, the object of the present invention is to provide a high-voltage gate drive circuit and a preparation method thereof. The high-voltage gate drive circuit is provided with an isolation structure with an air gap. The isolation structure with an air gap combines good isolation, low leakage, Small area, high reliability, high breakdown voltage and other characteristics play a very good isolation role.

According to an aspect of the present invention, a high-voltage gate driving circuit is provided, including: a first doped type substrate; a second doped type first buried layer located on the substrate; a first doped type An epitaxial layer located on the substrate and the first buried layer, the epitaxial layer includes a high-side driving circuit area, a low-side driving circuit area and a level shift circuit area, and the level shift circuit area at least includes A high-voltage LDMOS device; and a high-voltage isolation island and an isolation structure, the high-side drive circuit area and the low-side drive circuit area are isolated via the high-voltage isolation island, the level shift circuit area is isolated from the high-side drive circuit area Isolated via the isolation structure; wherein the isolation structure includes: an isolation trench extending from the surface of the epitaxial layer to the inside of the substrate; a dielectric layer located on the inner wall of the isolation trench; and air gap inside the layer.

Optionally, the width of the isolation trench is 1.0 μm ~ 3.0 μm, the depth is 15 μm ~ 30 μm, and the width-to-depth ratio of the isolation trench is 1:5 ~ 1:20.

Optionally, the high-voltage LDMOS device includes: the substrate of a first doping type; the first buried layer of a second doping type, located on the substrate; the first doping type of the An epitaxial layer, located on the substrate and the first buried layer; a second doping type high-voltage well, located in the epitaxial layer; a first doping type low-voltage well, located in the high-voltage well; A second buried layer of doping type is located in the high-voltage well; a field oxide layer is located on the high-voltage well and the low-voltage well of the first doping type; an ohmic contact region of the second doping type is located in the high-voltage well and the low-voltage well of the first doping type; an ohmic contact region of the first doping type located in the low-voltage well of the first doping type; and a gate structure located in the field oxide layer, the high-voltage well and the low-voltage well of the first doping type; wherein the second buried layer includes: a first portion located under the low-voltage well of the first doping type and connected with the third a doped type low voltage well contact; a second portion located below and separated from the field oxide layer; and a third portion connecting the first portion and the second portion such that the The second buried layer is electrically connected to the low voltage well of the first doping type.

Optionally, the high-side driving circuit region includes at least a medium-voltage NMOS device and a medium-voltage PMOS device, and the medium-voltage NMOS device includes: the substrate of a first doping type; and the second doping type of the substrate. A first buried layer is located on the substrate; the epitaxial layer of the first doping type is located on the first buried layer; the high voltage well of the second doping type is located in the epitaxial layer, The high-voltage well in the high-voltage LDMOS device and the high-voltage well in the medium-voltage NMOS device are formed at the same time; the first doping type low-voltage well is located in the epitaxial layer, and the first doped well in the high-voltage LDMOS device is A doping type low voltage well and a first doping type low voltage well in the medium voltage NMOS device are formed at the same time; a second doping type low voltage well is located in the epitaxial layer and the high voltage well; a first doping type low voltage well is formed in the epitaxial layer and the high voltage well; The second buried layer of hybrid type is located under the low-voltage well of the first doping type and the low-voltage well of the second doping type in the epitaxial layer, and is connected with the first doped type low-voltage well. The low-voltage well is in contact with the low-voltage well of the second doping type, and the second buried layer in the high-voltage LDMOS device and the second buried layer in the medium-voltage NMOS device are formed at the same time; a field oxide layer is located in the high-voltage well, the first doping type low voltage well, the second doping type low voltage well and the epitaxial layer, the field oxide layer in the high voltage LDMOS device and the field oxide layer in the medium voltage NMOS device The oxide layer is formed at the same time; the first doping type ohmic contact region is located in the first doping type low voltage well, the first doping type ohmic contact region in the high voltage LDMOS device and the middle The ohmic contact region of the first doping type in the NMOS device is formed at the same time; the ohmic contact region of the second doping type is located in the low voltage well of the first doping type and the low voltage well of the second doping type. In the well, the ohmic contact region of the second doping type in the high-voltage LDMOS device and the ohmic contact region of the second doping type in the medium-voltage NMOS device are formed simultaneously; and a gate structure is located in the field oxide On the layer, the low-voltage well of the first doping type, and the low-voltage well of the second doping type, the gate structure in the high-voltage LDMOS device and the gate structure in the medium-voltage NMOS device are formed simultaneously; In the medium-voltage NMOS device, the high-voltage well is located on both sides of the medium-voltage NMOS device and is connected to the first buried layer, and the second doping type low-voltage well and the first buried layer The second buried layer is isolated from the epitaxial layer.

Optionally, it also includes: one or more devices among low-voltage NMOS, low-voltage PMOS, transistor, resistor, and capacitor.

According to another aspect of the present invention, a method for preparing a high-voltage gate drive circuit is provided, including: forming a first buried layer of a second doping type on a first doping type substrate; A first doped type epitaxial layer is formed on the first buried layer, the epitaxial layer includes a high-side driving circuit area, a low-side driving circuit area and a level shift circuit area; an isolation structure is formed; in the level shift At least a high-voltage LDMOS device is formed in the epitaxial layer of the circuit area, and the level shift circuit area and the high-side drive circuit area are isolated via the isolation structure; and a high-voltage isolation island is formed in the epitaxial layer, and the high-side The driving circuit area is isolated from the low-side driving circuit area via the high-voltage isolation island; wherein the method of forming the isolation structure includes: etching the epitaxial layer and part of the substrate to form a The surface of the layer extends to an isolation trench inside the substrate; a dielectric layer is formed on the inner wall of the isolation trench; and an air gap is formed inside the dielectric layer.

Optionally, the width of the isolation trench is 1.0 μm ~ 3.0 μm, the depth is 15 μm ~ 30 μm, and the width-to-depth ratio of the isolation trench is 1:5 ~ 1:20.

Optionally, the method of forming the high-voltage LDMOS device includes: forming the first buried layer of the second doping type on the substrate of the first doping type; The epitaxial layer of the first doping type is formed on the buried layer; a high-voltage well of the second doping type is formed in the epitaxial layer; a low-voltage well of the first doping type is formed in the high-voltage well; in the forming a second buried layer of the first doping type in the high-voltage well; forming a field oxide layer on the high-voltage well and the low-voltage well of the first doping type in the high-voltage well; An ohmic contact region of a second doping type is formed in the low-voltage well of the first doping type in the high-voltage well, and a first doping region is formed in the low-voltage well of the first doping type in the high-voltage well. type ohmic contact region; and forming a gate structure on the field oxide layer, the high voltage well and the first doping type low voltage well among the high voltage well; wherein the second buried layer includes : The first part is located under the low-voltage well of the first doping type and is in contact with the low-voltage well of the first doping type; the second part is located under the field oxide layer and is in contact with the field oxide layer Separate; and a third part connecting the first part and the second part such that the second buried layer is electrically connected to the low voltage well of the first doping type.

Optionally, the method further includes forming at least a medium-voltage NMOS device and a medium-voltage PMOS device in the epitaxial layer of the high-side driving circuit region, and the method of forming the medium-voltage NMOS device includes: The first buried layer of the second doped type is formed on the substrate; the epitaxial layer of the first doped type is formed on the first buried layer; and the epitaxial layer of the second doped type is formed in the epitaxial layer. The high-voltage well, the high-voltage well in the high-voltage LDMOS device and the high-voltage well in the medium-voltage NMOS device are formed at the same time; the first doping type is formed in the epitaxial layer of the medium-voltage NMOS device. A low-voltage well, the low-voltage well of the first doping type in the high-voltage LDMOS device and the low-voltage well of the first doping type in the medium-voltage NMOS device are formed simultaneously; in the epitaxial layer of the medium-voltage NMOS device and forming a low-voltage well of a second doping type in the high-voltage well; forming the second buried layer of the first doping type in the epitaxial layer of the medium-voltage NMOS device, and the second buried layer is located below the first doping type low voltage well and the second doping type low voltage well in the epitaxial layer, and with the first doping type low voltage well and the second doping type Low-voltage well contact, the second buried layer in the high-voltage LDMOS device and the second buried layer in the medium-voltage NMOS device are formed at the same time; the high-voltage well in the epitaxial layer of the medium-voltage NMOS device, The first doped type low voltage well in the epitaxial layer, the second doped type low voltage well in the epitaxial layer and the field oxide layer are formed on the epitaxial layer, and the high voltage LDMOS The field oxide layer in the device and the field oxide layer in the medium-voltage NMOS device are formed simultaneously; the first doping type low-voltage well in the epitaxial layer of the medium-voltage NMOS device is formed. A doped type ohmic contact region, the first doped type ohmic contact region in the high voltage LDMOS device and the first doped type ohmic contact region in the medium voltage NMOS device are formed simultaneously; in the Forming the second doped type ohmic contact region in the first doped type low voltage well in the epitaxial layer of the NMOS device and the second doped type low voltage well in the epitaxial layer , the second doping type ohmic contact region in the high-voltage LDMOS device and the second doping type ohmic contact region in the medium-voltage NMOS device are formed simultaneously; and in the field of the medium-voltage NMOS device The gate structure is formed on the oxide layer, the first doping type low voltage well in the epitaxial layer, and the second doping type low voltage well in the epitaxial layer, and in the high voltage LDMOS device The gate structure and the gate structure in the medium-voltage NMOS device are formed at the same time; in the medium-voltage NMOS device, the high-voltage well is located on both sides of the medium-voltage NMOS device and is connected to the first buried layer Connected, the second doping type low voltage well and the first buried layer are isolated by the second buried layer and the epitaxial layer.

Optionally, it also includes: forming one or more devices among low-voltage NMOS, low-voltage PMOS, transistors, resistors, and capacitors.

In the embodiment of the present application, the DTI isolation structure with an air gap is mainly used between the level shift circuit area and the high-side driving circuit area, which can effectively alleviate the process and layout sensitivity of breakdown voltage and isolation voltage existing in conventional processes. sex, and the simpler isolation zone design between the two. While achieving a higher breakdown voltage, there is also a higher isolation voltage between the level shift circuit area and the high-side drive circuit area, which solves the problem of low isolation voltage caused by the high-voltage cross-line of the traditional junction isolation structure. And because the dielectric constant of the air gap is much smaller than that of solid insulating materials such as polycrystalline and oxide layers, the parasitic capacitance in the applied circuit is reduced, the response time is improved, and it is more suitable for high-frequency applications.

Compared with the conventional polycrystalline-filled DTI isolation structure (the isolation trench is filled with a polycrystalline structure), under working conditions, the floating polycrystalline will induce a potential, causing field opening on both sides of the isolation trench (isolation trench Carriers are induced on both sides of the isolation trench, thereby forming a conductive path on both sides of the isolation trench, resulting in a field turn-on phenomenon and a lower punch-through voltage. One improvement method is to etch the isolation trench so that the polycrystalline in the isolation trench is connected to the substrate and is always at zero potential. However, this structure will cause the problem of electric field concentration, which ultimately leads to a reduction in breakdown voltage. Another solution is to use trench bottom injection, but the high concentration of P-type impurities introduced at the bottom of the trench will cause premature breakdown of the trench bottom. Neither of the above two methods can achieve a higher isolation voltage while taking into account the breakdown voltage to meet the requirements. The DTI isolation structure of the embodiment of the present application does not cause the above-mentioned problems caused by the polycrystalline-filled DTI isolation structure, and can meet the requirements of breakdown voltage and isolation voltage at the same time.

All-dielectric DTI isolation can avoid the above-mentioned problems caused by the polycrystalline-filled DTI isolation structure. However, the stress problem caused by all-dielectric DTI can easily lead to defects inside the device. The DTI isolation structure of the embodiment of the present application can alleviate the conventional all-dielectric DTI isolation structure. The inherent stress issues caused by DTI isolation structures improve reliability.

The isolation voltage on both sides of the DTI isolation structure in the embodiment of the present application will continue to increase as the depth of the DTI isolation structure increases. The required isolation voltage can be obtained by setting the depth of the DTI isolation structure.

The DTI isolation structure in the embodiment of the present application can also be used for isolation of other devices, such as between the high-side driving circuit area and the low-side driving circuit area. Not only can it reduce the risk of parasitic transistors in the circuit turning on, thereby alleviating the latch-up effect and improving related leakage and reliability issues, but also due to the isolation effect of the DTI isolation structure, the negative voltage that occurs in inductive loads in practical applications Problems as well as dV/dT problems are better alleviated.

In summary, the DTI isolation structure provided by this application is used between the level shift circuit area and the high-side drive circuit area. It has the characteristics of high breakdown voltage and high isolation voltage, and can effectively alleviate the breakdown that exists in conventional processes. Voltage and isolation voltage sensitivity to process and layout. It combines the characteristics of good isolation, small leakage, small area, high reliability and high breakdown voltage, and can play a very good isolation role.

The high-voltage gate drive circuit provided by this application introduces a second buried layer of the first doping type into the high-voltage well. In order to maintain charge balance, the introduction of the second buried layer also improves the second doping type in the high-voltage LDMOS device ( For example, the concentration of N-type impurities can achieve a lower specific on-resistance under the same drift region length and breakdown voltage. Under the same current application requirements, the high-voltage LDMOS device of this application has a smaller area and smaller capacitance, and is more suitable for application in high-frequency scenarios, such as LLC power supplies and other fields.

Furthermore, the introduction of the second buried layer increases the second doping type impurity concentration of the drain, which is beneficial to improving the on-state characteristics of the high-voltage LDMOS device, thereby expanding the safe operating area of the high-voltage LDMOS device, and at the same time mitigating the electric field of the thin epitaxial process The effect of concentration towards the source end reduces the reliability problems caused by the excessive electric field in the beak part.

In the high-voltage LDMOS device, the second buried layer is located under the low-voltage well of the first doping type. Injecting the second buried layer of the first doping type under the low-voltage well of the first doping type can improve the parasitic NPN transistor base region. The concentration makes it more difficult to turn on the parasitic NPN transistor and increases the stability of the high-voltage LDMOS device.

In the high-voltage LDMOS device, the second buried layer located under the low-voltage well of the first doping type is connected to the low-voltage well of the first doping type to make them electrically connected, so that the high-voltage LDMOS device is the third one at the moment when the switching state is switched. The depleted charge in the second buried layer provides a path for discharge, thereby increasing the switching speed.

In addition, conventional fully-isolation NMOS devices require additional layers to improve the isolation voltage between the second doping type low-voltage well and the first buried layer. This application introduces the third layer of high-voltage LDMOS devices. The second buried layer is used in a medium-voltage NMOS device to improve the isolation voltage between the low-voltage well of the second doping type in the medium-voltage NMOS device and the first buried layer through the second buried layer, thereby achieving a better Fully isolated medium-voltage NMOS devices with high breakdown voltage also save additional photolithography levels.

This application requires less photolithography and processes to realize a full set of BCD (Bipolar, CMOS, DMOS) devices, significantly reducing costs.

Description of drawings

The above and other objects, features and advantages of the present invention will be more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

Figure 1a shows a schematic structural diagram of the first generation conventional isolation structure;

Figure 1b shows a schematic structural diagram of the second generation self-isolation structure;

Figure 1c shows a schematic structural diagram of the third generation Divided RESURF isolation structure;

Figure 2 shows the equivalent circuit diagram of the high-voltage gate drive circuit;

Figure 3a shows a top view of a conventional high voltage gate drive circuit;

Figure 3b shows a cross-sectional view along the direction AA' of Figure 3a;

Figure 4a shows a top view of the high-voltage gate drive circuit of the first embodiment of the present application;

Figure 4b is a cross-sectional view along the BB’ direction in Figure 4a;

Figure 4c shows a schematic connection diagram of the second buried layer of the high-voltage LDMOS device according to the first embodiment of the present application;

Figure 4d shows an enlarged view of C in Figure 4b;

Figure 4e shows an enlarged view of D in Figure 4b;

Figure 5a shows a simulation schematic diagram of the breakdown voltage and isolation voltage of a conventional polycrystalline-filled DTI isolation structure changing with the implanted dose at the bottom of the trench;

Figure 5b shows a simulation schematic diagram of the change of breakdown voltage and isolation voltage of the DTI isolation structure with the implanted dose at the bottom of the trench according to the first embodiment of the present application;

Figure 6 shows the changing trend of the breakdown voltage and specific on-resistance of the high-voltage LDMOS device according to the first embodiment of the present application with the dose of the second buried layer implant;

Figure 7a shows a simulation diagram of the longitudinal isolation withstand voltage of the medium-voltage NMOS device according to the first embodiment of the present application;

Figure 7b shows a simulation diagram of the breakdown voltage of the medium-voltage NMOS device according to the first embodiment of the present application;

Figure 8 shows a schematic structural diagram of a high-voltage gate drive circuit according to the second embodiment of the present application;

9a to 9j show schematic structural diagrams of various stages in the preparation process of the high-voltage gate drive circuit according to the first embodiment of the present application.

Detailed ways

The invention will be described in more detail below with reference to the accompanying drawings. In the various drawings, identical elements are designated with similar reference numerals. For the sake of clarity, parts of the figures are not drawn to scale. Additionally, some well-known parts may not be shown.

The invention may be presented in various forms, some examples of which are described below.

Figure 2 shows an equivalent circuit diagram of a high-voltage gate drive circuit. The high-voltage gate drive circuit includes a high-side drive circuit area, a low-side drive circuit area, and a level shift circuit area. The level shift circuit area at least includes a high-voltage LDMOS. device, the high-voltage LDMOS device performs signal transmission between the high-side drive circuit area and the low-side drive circuit area. The low-side drive circuit area is based on the substrate potential GND, and the input signal drives the external power device through the low-side drive circuit area; the small voltage in the low-side drive circuit area is output to the high-side drive circuit area through the high-voltage LDMOS device, thereby generating Sufficient driving voltage finally passes through the high-side driving circuit area to drive external power devices.

Wherein, the level shift circuit area may include one or more high-voltage LDMOS devices, the gate of each high-voltage LDMOS device in the one or more high-voltage LDMOS devices is connected to the pulse generation circuit in the low-side driving circuit area, and the source is connected to ground. The drain is connected to the high-side driver circuit area. When multiple high-voltage LDMOS devices are used in the level shift circuit area to transmit signals from the low-side drive circuit area to the high-side drive circuit area, multiple high-voltage LDMOS devices work alternately to achieve the effect of reducing power consumption. The high-side driving circuit area at least includes medium-voltage NMOS devices and medium-voltage PMOS devices.

Figure 3a shows a top view of a conventional high-voltage gate drive circuit, and Figure 3b shows a cross-sectional view along the direction AA' of Figure 3a. The conventional high-voltage gate drive circuit has a Divided RESURF structure. As shown in Figure 3a and Figure 3b, the high-side drive circuit area, low-side drive circuit area and level shift circuit area are located on the same substrate, and the high-voltage isolation island isolates the high-side drive circuit area from the low-side drive circuit area. The junction isolation structure J isolates the level shift circuit area from the high-side driving circuit area.

The second-generation self-isolation structure usually results in large leakage between the high-voltage LDMOS device and the high-voltage isolation island. Although the third-generation Divided RESURF structure has greater leakage compared to the second-generation self-isolation, However, the isolation structure is still highly sensitive to process fluctuations and layout design. The impact of charge balance on breakdown voltage and isolation voltage needs to be taken into consideration, and failure problems are prone to occur.

The high-voltage gate drive circuit using junction isolation structure J needs to consider the impact of the width of the isolation region on the breakdown voltage of the high-voltage LDMOS device and the isolation voltage between the high-voltage LDMOS device and the high-side drive circuit area. In order to obtain better isolation effect, the width of the isolation area cannot be too small, otherwise it may lead to premature breakdown of the high-voltage LDMOS device and the high-side drive circuit area. However, the wider the isolation area, the greater the impact of the isolation on the high-voltage LDMOS device and the high-side drive circuit area. The worse the depletion effect of the area, when the impurities somewhere in the isolation area are not depleted, it will cause premature breakdown of the high-voltage LDMOS device and reduce the breakdown voltage, that is, the width of the isolation area cannot be too large. Therefore, the conventional Divided-RESURF structure requires a relatively complex design in the isolation area, and has certain requirements for layout drawing and process processing. At the same time, due to the influence of high-voltage cross-wires, the junction isolation structure easily causes field opening on the surface of the epitaxial layer during operation, resulting in a reduction in the isolation voltage on both sides of the high-voltage LDMOS device and the high-side drive circuit area. In the junction isolation structure J in Figure 3b, the introduction of the low-voltage well 306b can alleviate the field turn-on effect and increase the isolation voltage, but higher electric field peaks will appear on both sides of 306b, which may lead to premature breakdown of the device.

The isolation structure S of the present application can effectively alleviate the problems caused by junction isolation. Figure 4a shows a schematic structural diagram of a high-voltage gate drive circuit according to the first embodiment of the present application. Figure 4b is a cross-sectional view along the BB' direction in Figure 4a. Figure 4c shows a high-voltage LDMOS device according to the first embodiment of the present application. A schematic structural diagram of the second buried layer, Figure 4d shows an enlarged view of C in Figure 4b, and Figure 4e shows an enlarged view of D in Figure 4b.

As shown in Figure 4a, the high-side drive circuit area, low-side drive circuit area and level shift circuit area are located on the same substrate. The high-voltage isolation island isolates the high-side drive circuit area from the low-side drive circuit area. DTI isolation structure S isolates the level-shift circuit area from the high-side drive circuit area. As shown in Figure 4b, the level shift circuit area includes a high-voltage LDMOS device, and the high-side driving circuit area includes at least a medium-voltage NMOS device and a medium-voltage PMOS device. In other embodiments, two high-voltage LDMOS devices can be used in the level shift circuit area to transmit signals from the low-side driving circuit area to the high-side driving circuit area. The two high-voltage LDMOS devices work alternately to achieve the effect of reducing power consumption.

Continuing to refer to FIG. 4b, the high-voltage gate driving circuit includes a first doping type substrate 301, a second doping type first buried layer 302, a first doping type epitaxial layer 303 and DTI (Deep Trench Isolation, Deep Trench Isolation). slot isolation) isolation structure S. In this embodiment, the first doping type is, for example, P-type doping, and the second doping type is, for example, N-type doping.

The first buried layer 302 is located on the substrate 301 and covers part of the surface of the substrate 301 . The epitaxial layer 303 is located on the substrate 301 and the first buried layer 302 and covers the surface of the substrate 301 and the surface of the first buried layer 302 . The DTI isolation structure S extends from the surface of the epitaxial layer 303 toward the substrate 301 . The DTI isolation structure S penetrates the epitaxial layer 303 and extends into the substrate 301 . The DTI isolation structure S isolates the epitaxial layer 303 into multiple regions to form corresponding semiconductor devices in each region.

The DTI isolation structure S includes an isolation trench S01, a dielectric layer S02 located in the trench S01, and an air-gap S03 inside the dielectric layer S02. The isolation trench S01 extends from the surface of the epitaxial layer 303 to the inside thereof, penetrates the epitaxial layer 303 , and extends to the inside of the substrate 301 . The dielectric layer S02 is located in the isolation trench S01, and an air gap S03 is formed inside the dielectric layer S02.

The DTI isolation structure S with air gap is mainly used between the level shift circuit area and the high-side drive circuit area. The isolation trench structure is different from junction isolation. The high-voltage cross-line has no impact on the isolation trench structure, thus avoiding the field turn-on phenomenon. and the problem of low isolation voltage. The DTI isolation structure S of the present application has little impact on the isolation voltage and breakdown voltage, and there is no need to consider the width of the isolation region on the breakdown voltage of the high-voltage LDMOS device and the isolation voltage between the high-voltage LDMOS device and the high-side drive circuit area. Impact. It can effectively alleviate the sensitivity of breakdown voltage and isolation voltage to process and layout that exist in conventional processes, and has a large tolerance. While achieving a higher breakdown voltage, there is also a higher isolation voltage between the level shift circuit area and the high-side drive circuit area.

For medium and high-voltage devices (>30V), larger rules (taking into account the transverse expansion of the well) are generally used to achieve the required isolation withstand voltage, thus occupying a larger chip area and increasing the cost of the chip. The DTI isolation structure S can effectively solve this problem. It only requires an isolation trench S01 of 1.0μm~2.0μm (which is filled with a dielectric layer S02 internally and an air gap S03 is formed in the dielectric layer S02) to meet the corresponding isolation withstand voltage requirements. The area of the DTI isolation structure S in the embodiment of the present application is smaller, reducing the area of the chip, which can effectively save the isolation area of the chip and reduce costs.

Figure 5a shows a simulation schematic diagram of the breakdown voltage and isolation voltage of a conventional polycrystalline-filled DTI isolation structure changing with the implanted dose at the bottom of the trench; Figure 5b shows the breakdown voltage of the DTI isolation structure of the first embodiment of the present application. and the simulation diagram of the isolation voltage changing with the dose injected at the bottom of the trench; in Figure 5a and Figure 5b, the abscissa is the dose D _bi injected at the bottom of the trench, the ordinate on the left is the breakdown voltage, and the ordinate on the right is the isolation voltage. The main purpose of trench bottom injection is to increase the P-type impurity concentration at the bottom of the trench, alleviate the field turn-on phenomenon at both ends of the isolation trench, and thereby increase the isolation voltage. In actual applications, the breakdown voltage is required to be greater than 800V, and the isolation voltage is greater than 30V. As shown in Figure 5a, the conventional polycrystalline-filled DTI structure has a breakdown voltage greater than 800V without trench bottom injection, but the isolation voltage is low, only 8V, which cannot meet the needs of the application; with the dose injected at the trench bottom With the increase, at a dose of 5e12cm ^-2 , the isolation voltage can reach more than 30V, but at this time, due to the increase in the curvature effect of the trench bottom, the breakdown voltage decreases, so the conventional polycrystalline-filled DTI isolation structure cannot meet the breakdown voltage at the same time. voltage and isolation voltage requirements. As shown in Figure 5b, the DTI isolation structure of the first embodiment of the present application does not have the field turn-on phenomenon caused by the introduction of polycrystalline. Therefore, a higher isolation voltage can be obtained without trench bottom injection, and it has the advantages of high The characteristics of breakdown voltage and high isolation voltage meet the application requirements of HVIC (High Voltage Integrated Circuit) and are more suitable for high-voltage applications. Moreover, the DTI isolation structure S of the embodiment of the present application can alleviate the inherent stress problem caused by the conventional all-dielectric DTI isolation structure and improve the reliability.

The DTI isolation structure in the embodiment of the present application can also be used for isolation of other devices, such as between the high-side driving circuit area and the low-side driving circuit area. Junction isolation structures J will have larger latching problems. This embodiment adopts the DTI isolation structure S with an air gap. Compared with the junction isolation structure J, the DTI isolation structure S in the embodiment of the present application can not only reduce the risk of turning on the parasitic transistor in the circuit, thereby mitigating the latch-up effect and making the relevant The leakage and reliability problems have been improved, and due to the isolation effect of the DTI isolation structure, it has a better effect on alleviating the negative voltage problems and dV/dT problems that occur in practical applications of inductive loads. The DTI isolation structure S in the embodiment of the present application combines the characteristics of good isolation, small leakage, small area, high reliability, and high breakdown voltage, and can play a very good isolation role.

Continuing to refer to FIG. 4 b , the high-voltage LDMOS device includes a second doping type high-voltage well 304 located in the epitaxial layer 303 , a first doping type low-voltage well 306 b located in the second doping type high-voltage well 304 , and respectively located in A plurality of ohmic contact regions in the second doping type high voltage well 304 and the first doping type low voltage well 306b. The plurality of ohmic contact regions include a second doping type ohmic contact region 308a and a first doping type ohmic contact region. Ohmic contact region 308b, ohmic contact region 308a are located in the high voltage well 304 and low voltage well 306b, ohmic contact region 308b is located in the low voltage well 306b; ohmic contact region 308a and ohmic contact region 308b serve as the source region and/or drain region of the high voltage LDMOS device lead out.

The high-voltage LDMOS device also includes a field oxide layer 305 located on the high-voltage well 304 and the low-voltage well 306b, and a gate structure 307 located on the surfaces of the low-voltage well 306b, the high-voltage well 304 and the field oxide layer 305. The gate structure 307 includes a gate oxide layer and Gate polycrystalline.

The high-voltage LDMOS device also includes an insulating layer 311 and a metal electrode 309. The insulating layer 311 covers the gate structure 307, the field oxide layer 305 and the ohmic contact areas 308a and 308b. A penetrating insulating layer 311 is also formed on the insulating layer 311 to connect with the ohmic contact areas. 308a, 308b and the metal electrode 309 connected to the gate structure 307.

Preferably, the high-voltage LDMOS device further includes a second buried layer 310 of the first doping type located in the high-voltage well 304 . As shown in Figure 4b and Figure 4c, the second buried layer 310 includes a first portion 3101 located under the low-voltage well 306b. The first portion 3101 is located between the source region and the drain region and is in contact with the first doping type low-voltage well 306b; a second part 3102 located below the field oxide layer 305 and separated from the field oxide layer 305; and a third part 3103 connecting the first part 3101 and the second part 3102, and the first part 3101, the second part 3102 and the third part 3103 are connected It is formed into one body, and the first part 3101 is in contact with the low-voltage well 306b, so that the entire second buried layer 310 is electrically connected to the low-voltage well 306b.

In this application, a second buried layer 310, a first doping type second buried layer 310, a second doping type first buried layer 302, and a first doping type epitaxial layer 303 are introduced into the high voltage well 304. , the second doping type high-voltage well 304 and the first doping type low-voltage well 306b form a Triple RESURF (Triple reduced surface field, triple reduced surface field) structure.

In order to obtain better dynamic performance, the floating second buried layer 310 is not used in the Triple RESURF structure, but the second buried layer 310 is partially connected to the first doping type low-voltage well 306b to electrically connect it. The high-voltage LDMOS device provides a discharge path for the depleted charge in the second buried layer 310 at the moment when the switching state is switched, thereby increasing the switching speed. Therefore, the high-voltage LDMOS device in this application is more suitable for high-frequency applications. occasion.

The introduction of the second buried layer 310 increases the concentration of the first doping type (eg, P-type) impurities in the high-voltage LDMOS device. In order to maintain charge balance, the concentration of the second doping type (eg, N-type) impurities in the high-voltage well 304 It has also been improved. Under the same drift region length and breakdown voltage, the increase in the first doping type impurity concentration of the high-voltage well 304 reduces the specific on-resistance of the high-voltage LDMOS device. Under the same current application requirements, high-voltage LDMOS devices have smaller areas and smaller capacitances, making them more suitable for application in high-frequency scenarios.

Furthermore, the introduction of the second buried layer 310 increases the second doping type impurity concentration of the drain, which is beneficial to improving the on-state characteristics of the high-voltage LDMOS device, thereby expanding the safe operating area of the high-voltage LDMOS device, while reducing the thin epitaxial The effect of the process electric field concentrating towards the source end reduces the reliability problems caused by the excessive electric field in the beak part.

There is a parasitic NPN transistor in the high-voltage LDMOS device composed of the second doping type ohmic contact region 308a, the first doping type low-voltage well 306b, and the second doping type high-voltage well 304. Turning on the parasitic NPN transistor will cause Snapback effect (negative resistance effect) affects the output characteristics of high-voltage LDMOS devices. Injecting the second buried layer 310 of the first doping type below the low-voltage well 306b of the high-voltage LDMOS device can increase the concentration of the parasitic NPN transistor base region (low-voltage well 306b), making it more difficult to turn on the parasitic NPN transistor. Stability of high-voltage LDMOS devices.

FIG. 6 shows the changing trend of the breakdown voltage and specific on-resistance of the high-voltage LDMOS device according to the first embodiment of the present application as the dose of the second buried layer 310 is implanted. The specific on-resistance increases as the implantation dose of the second buried layer 310 increases, because the specific on-resistance is mainly determined by the concentration and conductive path of the high-voltage well 304 . An increase in the implant dose of the second buried layer 310 will only consume part of the first doping type impurity concentration and part of the conductive path in the high voltage well 304, so the specific on-resistance will only increase slightly. The specific on-resistance of the present invention reaches the level of 100 mΩ·cm ² , which is far smaller than the 300 mΩ·cm ² of Single RESURF and the 170 mΩ·cm ² of Double RESURF, and can provide the same current capability in a smaller area. .

Too much or too little implantation dose into the second buried layer 310 will lead to charge imbalance. Therefore, when the implantation dose is too much or too little, the breakdown voltage will be greatly reduced. Under the implantation dose of 2.9e12 cm ^-2 , the charge balance of N-type impurities and P-type impurities was achieved, and the maximum breakdown voltage (over 800V) was obtained, meeting the application of high-voltage gate drive circuits with 600 V specifications.

Referring to Figures 4b and 4d, the buried layer 302 in the medium-voltage NMOS device is located on the substrate 301, the epitaxial layer 303 is located on the buried layer 302, and the medium-voltage NMOS device includes a high-voltage well of the second doping type located in the epitaxial layer 303. 304, a second doped type low pressure well 306a located in the high pressure well 304, a first doped type low pressure well 306b and a second doped type low voltage well 306a located in the epitaxial layer 303, and the second doped type low voltage well 306a respectively located in the epitaxial layer 303. A plurality of ohmic contact regions in the impurity type low voltage well 306a and the first doping type low voltage well 306b. The plurality of ohmic contact regions include a second doping type ohmic contact region 308a and a first doping type ohmic contact region. 308b, the ohmic contact region 308a is located in the first doping type low voltage well 306b and the second doping type low voltage well 306a, the ohmic contact region 308b is located in the first doping type low voltage well 306b, the ohmic contact region 308a and the ohmic Contact region 308b leads to the source and/or drain regions of medium voltage NMOS device 30b.

The medium voltage NMOS device also includes a field oxide layer 305, a gate structure 307, an insulating layer 311 and a metal electrode 309. The field oxide layer 305 is located on the epitaxial layer 303, the high voltage well 304, the low voltage well 306a and the low voltage well 306b; the gate structure 307 is located on the surfaces of the low voltage well 306b, the low voltage well 306a and the field oxide layer 305; the insulating layer 311 covers the low voltage well 306a, The low voltage well 306b, the ohmic contact regions 308a, 308b, the gate structure 307 and the field oxide layer 305, the metal electrode 309 is located on the insulating layer 311 and penetrates the insulating layer 311 to connect with the ohmic contact regions 308a, 308b and the gate structure 307.

The medium voltage NMOS device also includes a second buried layer 310 of the first doping type located within the epitaxial layer 303 . The second buried layer 310 is located under the low-voltage well 306a and the low-voltage well 306b in the epitaxial layer 303, and is in contact with the low-voltage well 306a and the low-voltage well 306b respectively.

The high-voltage well 304 in the high-voltage LDMOS device and the high-voltage well 304 in the medium-voltage NMOS device are formed simultaneously; the first doping type low-voltage well 306b in the high-voltage LDMOS device and the first doping type low-voltage well in the medium-voltage NMOS device 306b is formed at the same time; the second buried layer 310 in the high-voltage LDMOS device and the second buried layer 310 in the medium-voltage NMOS device are formed at the same time; the field oxide layer 305 in the high-voltage LDMOS device and the field oxide layer 305 in the medium-voltage NMOS device are formed at the same time. Forming; the first doping type ohmic contact region 308a in the high-voltage LDMOS device and the first doping type ohmic contact region 308a in the medium-voltage NMOS device are simultaneously formed; the second doping type ohmic contact in the high-voltage LDMOS device The region 308b and the second doping type ohmic contact region 308b in the medium-voltage NMOS device are formed at the same time; the gate structure 307 in the high-voltage LDMOS device and the gate structure 307 in the medium-voltage NMOS device are formed at the same time; the gate structure 307 in the high-voltage LDMOS device is formed simultaneously. The insulating layer 311 and the insulating layer 311 in the medium-voltage NMOS device are formed at the same time; the metal electrode 309 in the high-voltage LDMOS device and the metal electrode 309 in the medium-voltage NMOS device are formed at the same time.

In this embodiment, the second buried layer 310 is introduced into the medium-voltage NMOS device 30b, thereby improving the vertical isolation voltage of the medium-voltage NMOS device.

In the medium-voltage NMOS device, the high-voltage well 304 is located on both sides of the medium-voltage NMOS device and is connected to the first buried layer 302. The second doping type low-voltage well 306a in the epitaxial layer 303 and the first buried layer 302 are connected by a third The second buried layer 310 is isolated from the epitaxial layer 303.

In the medium-voltage NMOS device of this embodiment, the isolation voltage between the drain and the peripheral isolation ISO ring composed of the high-voltage well 304 depends on the first doping type impurity concentration between the two. The greater the concentration, the higher the isolation voltage. Since the medium-voltage NMOS device is isolated laterally by the low-voltage well 306b with a higher concentration, the isolation voltage between the drain of the medium-voltage NMOS device and the peripheral isolation ISO ring composed of high-voltage wells mainly depends on the low-voltage well 306a and the first buried The first doping type impurity concentration between the layers 302 is the first doping type impurity concentration of the epitaxial layer 303 . However, due to the relatively thin concentration of the epitaxial layer 303, the isolation voltage of the medium-voltage NMOS device is limited. The introduction of the second buried layer 310 increases the concentration of the first doped type impurity, thereby improving the connection between the second doped type low-voltage well 306a and the first buried layer 302 through the second buried layer 310. The isolation voltage between them realizes a fully isolated medium-voltage NMOS device with a higher breakdown voltage while also saving additional photolithography levels. Figure 7a shows a simulation diagram of the longitudinal isolation withstand voltage of the medium-voltage NMOS device according to the first embodiment of the present application; Figure 7b shows a simulation diagram of the breakdown voltage of the medium-voltage NMOS device according to the first embodiment of the present application; Figure 7a As shown in the figure, due to the introduction of the second buried layer 310 in the medium-voltage NMOS device, the isolation voltage between the second doping type low-voltage well 306a and the first buried layer 302 through the second buried layer 310 reaches By using 62V, a fully isolated medium-voltage NMOS device with a higher breakdown voltage can be achieved, while also saving additional photolithography levels and increasing the application range of medium-voltage NMOS devices. By introducing the second buried layer 310, the breakdown voltage of the medium-voltage NMOS device in this embodiment can be achieved in a range of less than 62 V. As shown in Figure 7b, this embodiment provides a 20V-level medium-voltage NMOS with a breakdown voltage of 34.2V.

Referring to Figures 4b and 4e, the buried layer 302 in the medium-voltage PMOS device is located on the substrate 301, the epitaxial layer 303 is located on the buried layer 302, and the medium-voltage PMOS device includes a high-voltage well of the second doping type located in the epitaxial layer 303. 304 and the high-voltage well 304 is located on the buried layer 302, the low-voltage well 306a of the second doping type and the low-voltage well 306b of the first doping type are located in the high-voltage well 304, and the low-voltage wells 306a and 306b of the second doping type are respectively located in the high-voltage well 304. A plurality of ohmic contact regions in the first doping type low voltage well 306b. The plurality of ohmic contact regions include a second doping type ohmic contact region 308a and a first doping type ohmic contact region 308b. The ohmic contact region 308a is located In the second doping type low-voltage well 306a, the ohmic contact region 308b is located in the first doping type low-voltage well 306b and the second doping type low-voltage well 306a. The ohmic contact region 308a and the ohmic contact region 308b serve as a medium voltage PMOS. Source and/or drain regions of the device.

The medium voltage PMOS device also includes a field oxide layer 305, a gate structure 307, an insulating layer 311 and a metal electrode 309. The field oxide layer 305 is located on the high voltage well 304, the low voltage well 306a and the low voltage well 306b; the gate structure 307 is located on the surfaces of the low voltage well 306b, the low voltage well 306a and the field oxide layer 305; the insulating layer 311 covers the low voltage well 306a, the low voltage well 306b, The ohmic contact regions 308a, 308b, the gate structure 307 and the field oxide layer 305, the metal electrode 309 is located on the insulating layer 311 and penetrates the insulating layer 311 to connect with the ohmic contact regions 308a, 308b and the gate structure 307.

Figure 8 shows a schematic structural diagram of a high-voltage gate drive circuit according to the second embodiment of the present application; as shown in Figure 8, the high-voltage gate drive circuit includes a first doped type substrate 301, a second doped type substrate 301, and a second doped type substrate 301. a buried layer 302, a first doping type epitaxial layer 303, a high-voltage LDMOS device 30a, a medium-voltage NMOS device 30b, a medium-voltage PMOS device 30c, a low-voltage CMOS device 30d and a bipolar NPN device 30e located in the epitaxial layer 303, The high-voltage LDMOS device 30a, the medium-voltage NMOS device 30b, the medium-voltage PMOS device 30c, the low-voltage CMOS device 30d and the bipolar NPN device 30e are separated by a DTI isolation structure S.

In other embodiments, the high-voltage gate driving circuit may also include one or more devices such as transistors, resistors, and capacitors.

The various semiconductor devices listed in this embodiment are examples, and their positions and quantities can be adjusted accordingly and are not intended to limit the application. Those skilled in the art should understand that the semiconductor devices are not limited to the ones listed in this embodiment, and can also be other semiconductor devices not mentioned in this embodiment, and the positional relationship between the various semiconductor devices can also be based on specific The structure is adjusted. The above-mentioned semiconductor device may be located in the high-side driving circuit region and/or the low-side driving circuit region. It can be understood that although the semiconductor devices in FIG. 8 are separated by a DTI isolation structure S, in other embodiments, the semiconductor devices may also be separated by a traditional junction isolation structure, or may not be separated. open.

9a to 9j show schematic structural diagrams of various stages in the preparation process of the high-voltage gate drive circuit according to the first embodiment of the present application. The structure in FIG. 4b is used for illustration, but is not limited thereto.

As shown in FIG. 9a, a first buried layer 302 of the second doping type is formed on the substrate 301 of the first doping type.

In this step, photolithography and ion implantation processes are used to form the first buried layer 302 on the substrate 301, and then the first buried layer 302 is pushed and activated. In this embodiment, the first buried layer 302 covers part of the surface of the substrate 301 . The substrate 301 has a first doping type, the first buried layer 302 has a second doping type, and the resistivity of the substrate 301 can be selected according to the breakdown voltage of the device to be formed (eg, a high-voltage LDMOS device).

The first buried layer 302 is used for isolation to reduce the latch-up effect, and to reduce or block leakage between various semiconductor devices. Further, for high-voltage LDMOS devices, the first buried layer 302 is used to reduce the capacitance between the drain and the substrate 301, thereby increasing the switching speed of the high-voltage LDMOS device, but the introduction of the first buried layer 302 may cause High-voltage LDMOS devices break down prematurely here, so there is a trade-off between reducing capacitance and maintaining breakdown voltage.

As shown in FIG. 9 b , a first doped type epitaxial layer 303 is formed on the first doped type substrate 301 and the second doped type first buried layer 302 . The thickness of the epitaxial layer 303 is, for example, 7 μm to 10 μm.

As shown in Figure 9c, a high-voltage well 304 is formed in the first doping type epitaxial layer 303. The high-voltage well 304 is used for withstand voltage and isolation of the high-voltage LDMOS device. The doping of the high-voltage well 304 of the high-voltage LDMOS device in the embodiment of the present application is The impurity concentration has a certain increase compared to the conventional Single and Double RESURF structures, so the specific on-resistance of high-voltage LDMOS devices can be reduced at the same breakdown voltage. In addition, the second doping type high-voltage well 304 can also be used in medium and low-voltage MOS devices to increase the drift region concentration of NMOS devices or reduce the threshold voltage of PMOS devices; it can also be used as a lateral function in bipolar transistors. The base of PNP devices and the collector of vertical NPN devices.

As shown in Figure 9d, a DTI isolation structure S is formed.

In this step, the epitaxial layer 303 of the first doping type and part of the substrate 301 are etched to form an isolation trench S01, and then the dielectric layer S02 is deposited and backfilled to form the DTI isolation structure S. The DTI isolation structure S includes an isolation trench S01, a dielectric layer S02 located on the inner wall of the trench S01, and an air gap S03 inside the dielectric layer S02. The isolation trench S01 extends from the surface of the epitaxial layer 303 to the inside thereof, penetrates the epitaxial layer 303 and extends to the inside of the substrate 301 . The dielectric layer S02 is located in the isolation trench S01, and an air gap S03 is formed inside the dielectric layer S02.

The isolation trench S01 of the DTI isolation structure S can be formed by dry etching, for example, reactive ion etching (RIE). The width-to-depth ratio of isolation trench S01 is controlled between 1:5 and 1:20, and different etching angles can be used to obtain different trench sizes. To deposit the dielectric layer S02 inside the isolation trench S01, the low-pressure chemical vapor deposition (LPCVD) or sub-atmospheric pressure chemical vapor deposition (SACVD) process can be used. The main purpose is to alleviate the reliability problems caused by the stress of the dielectric layer. After the dielectric layer S02 is deposited, the dielectric layer S02 on the surface of the isolation trench S01 needs to be sealed in advance so that there is a certain gap in the middle of the dielectric layer S02 to form an air gap S03. The width of the isolation trench S01 is usually 1.0μm~3.0μm, and the depth is usually 15μm~30μm.

As shown in Figure 9e, the active area is formed by photolithography and etching, and the field oxide layer 305 is formed by thermal oxidation. The field oxide layer 305 is used for device isolation.

As shown in Figure 9f, a second buried layer 310 is formed.

In this step, the second buried layer 310 of the first doping type is formed through high-energy implantation. The second buried layer 310 in the high-voltage LDMOS device and the second buried layer 310 in the medium-voltage NMOS device are formed through the same photoresist, that is, the second buried layer 310 in the high-voltage LDMOS device and the second buried layer 310 in the medium-voltage NMOS device. The buried layer 310 is the same layer. The introduction of the second buried layer 310 increases the concentration of the first doping type impurity in the high-voltage LDMOS device, and improves the passage of the second doping type low-voltage well 306a and the first buried layer 302 through the second buried layer in the medium-voltage NMOS device. The isolation voltage between 310 and 310 enables fully isolated medium-voltage NMOS devices with higher breakdown voltage while also saving additional photolithography levels.

As shown in FIG. 9g , a low-voltage well 306a of the second doping type and a low-voltage well 306b of the first doping type are formed.

In this step, a second doping type low-voltage well 306a and a first doping type low-voltage well 306b are formed through high-energy implantation. The second doping type low-voltage well 306a and the first doping type low-voltage well 306b serve as intermediate In the well area of low-voltage devices, due to the small number of photolithography layers in this process, the low-voltage well is also used in the source area of medium and low-voltage MOS devices. It is necessary to consider whether the concentration meets the requirements of the threshold voltage, and to avoid the same rules. , the premature breakdown of devices with different doping types makes the design more difficult and requires reasonable optimization.

As shown in Figure 9h, a gate structure 307 is formed.

In this step, a thin gate oxide layer is grown by thermal oxidation. The thickness of the gate oxide layer is selected according to the actual application, and then polysilicon is deposited to form the gate structure 307. In addition, polysilicon can also be used to form a polycrystalline field plate or capacitor. Field board.

As shown in Figure 9i, implantation activates to form a first doping type ohmic contact region 308b and a second doping type ohmic contact region 308a, the first doping type ohmic contact region 308b and a second doping type ohmic contact region 308a is a heavily doped region, forming an ohmic contact to reduce contact resistance.

As shown in Figure 9j, similar to the ordinary CMOS process, the insulating layer deposition, contact hole photolithography and etching, the deposition and photolithography of the first layer of metal, the formation of the through hole between the two layers of metal, and the The deposition and photolithography of two layers of metal, as well as the formation of a passivation layer, ultimately form a complete high-voltage gate drive circuit.

According to the above-mentioned embodiments of the present invention, these embodiments do not exhaustively describe all the details, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above description. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and make modifications based on the present invention. The invention is limited only by the claims and their full scope and equivalents.

Claims (8)

1. A high voltage gate drive circuit comprising:

a substrate of a first doping type;

a first buried layer of a second doping type located on the substrate;

an epitaxial layer of a first doping type on the substrate and the first buried layer, the epitaxial layer including a high-side drive circuit region, a low-side drive circuit region, and a level shift circuit region, the level shift circuit region including at least a high-voltage LDMOS device; and

A high-voltage isolation island and an isolation structure, the high-side drive circuit region and the low-side drive circuit region being isolated via the high-voltage isolation island, the level shift circuit region and the high-side drive circuit region being isolated via the isolation structure;

wherein, the isolation structure includes:

an isolation trench extending from a surface of the epitaxial layer to an inside of the substrate;

the dielectric layer is positioned on the inner wall of the isolation groove; and

an air gap located inside the dielectric layer;

the high-voltage LDMOS device comprises:

a high-voltage well of a second doping type located in the epitaxial layer;

a low voltage well of a first doping type located in the high voltage well;

a second buried layer of the first doping type located in the high-voltage well;

a field oxide layer located on the high voltage well and the low voltage well of the first doping type;

an ohmic contact region of a second doping type located in the high voltage well and the low voltage well of the first doping type;

an ohmic contact region of a first doping type located in the low voltage well of the first doping type; and

the grid structure is positioned on the field oxide layer, the high-voltage well and the low-voltage well of the first doping type;

Wherein the second buried layer includes:

a first portion located under and in contact with the low voltage well of the first doping type;

a second portion below the field oxide layer and spaced apart from the field oxide layer; and

and a third portion connecting the first portion and the second portion such that the second buried layer is electrically connected with the low-voltage well of the first doping type.

2. The high voltage gate driving circuit of claim 1, wherein the isolation trench has a width of 1.0 μm to 3.0 μm and a depth of 15 μm to 30 μm, and the isolation trench has a width to depth ratio of 1: 5-1: 20.

3. the high voltage gate drive circuit of claim 1, wherein the high side drive circuit region comprises at least a medium voltage NMOS device and a medium voltage PMOS device, the medium voltage NMOS device comprising:

the substrate of the first doping type;

the first buried layer with the second doping type is positioned on the substrate;

the epitaxial layer with the first doping type is positioned on the first buried layer;

the high-voltage well of the second doping type is positioned in the epitaxial layer, and the high-voltage well in the high-voltage LDMOS device and the high-voltage well in the medium-voltage NMOS device are formed at the same time;

The low-voltage well of the first doping type is positioned in the epitaxial layer, and the low-voltage well of the first doping type in the high-voltage LDMOS device and the low-voltage well of the first doping type in the medium-voltage NMOS device are formed at the same time;

a low voltage well of a second doping type located in the epitaxial layer and the high voltage well;

the second buried layer of the first doping type is positioned below the low-voltage well of the first doping type and the low-voltage well of the second doping type in the epitaxial layer and is in contact with the low-voltage well of the first doping type and the low-voltage well of the second doping type, and the second buried layer in the high-voltage LDMOS device and the second buried layer in the medium-voltage NMOS device are formed at the same time;

a field oxide layer located on the high-voltage well, the low-voltage well of the first doping type, the low-voltage well of the second doping type and the epitaxial layer, wherein the field oxide layer in the high-voltage LDMOS device and the field oxide layer in the medium-voltage NMOS device are formed at the same time;

the ohmic contact region of the first doping type is positioned in the low-voltage well of the first doping type, and the ohmic contact region of the first doping type in the high-voltage LDMOS device and the ohmic contact region of the first doping type in the medium-voltage NMOS device are formed simultaneously;

The ohmic contact region of the second doping type is positioned in the low-voltage well of the first doping type and the low-voltage well of the second doping type, and the ohmic contact region of the second doping type in the high-voltage LDMOS device and the ohmic contact region of the second doping type in the medium-voltage NMOS device are formed at the same time; and

the gate structure is positioned on the field oxide layer, the low-voltage well of the first doping type and the low-voltage well of the second doping type, and the gate structure in the high-voltage LDMOS device and the gate structure in the medium-voltage NMOS device are formed at the same time;

in the medium voltage NMOS device, the high voltage well is positioned at two sides of the medium voltage NMOS device and connected with the first buried layer, and the low voltage well with the second doping type and the first buried layer are isolated through the second buried layer and the epitaxial layer.

4. The high voltage gate driving circuit according to any one of claims 1 to 3, further comprising: one or more of low-voltage NMOS, low-voltage PMOS, triode, resistor and capacitor.

5. A preparation method of a high-voltage gate driving circuit comprises the following steps:

forming a first buried layer of a second doping type on the substrate of the first doping type;

Forming an epitaxial layer of a first doping type on the substrate and the first buried layer, wherein the epitaxial layer comprises a high-side driving circuit region, a low-side driving circuit region and a level shift circuit region;

forming an isolation structure;

forming at least a high-voltage LDMOS device in an epitaxial layer of the level shift circuit area, wherein the level shift circuit area is isolated from the high-side driving circuit area through the isolation structure; and

forming a high-voltage isolation island in the epitaxial layer, the high-side drive circuit region being isolated from the low-side drive circuit region via the high-voltage isolation island;

the method for forming the isolation structure comprises the following steps:

etching the epitaxial layer and part of the substrate to form an isolation trench extending from the surface of the epitaxial layer to the inside of the substrate;

forming a dielectric layer on the inner wall of the isolation trench; and

forming an air gap inside the dielectric layer;

forming a high-voltage well of a second doping type in the epitaxial layer;

forming a low-voltage well of a first doping type in the high-voltage well;

forming a second buried layer of the first doping type in the high-voltage well;

forming a field oxide layer on the high voltage well and the low voltage well of the first doping type in the high voltage well;

Forming an ohmic contact region of a second doping type in the high-voltage well and a low-voltage well of the first doping type in the high-voltage well, and forming an ohmic contact region of the first doping type in the low-voltage well of the first doping type in the high-voltage well; and

forming a gate structure on the field oxide layer, the high voltage well and the low voltage well of the first doping type in the high voltage well;

wherein the second buried layer includes:

a first portion located under and in contact with the low voltage well of the first doping type;

a second portion below the field oxide layer and spaced apart from the field oxide layer; and

and a third portion connecting the first portion and the second portion such that the second buried layer is electrically connected with the low-voltage well of the first doping type.

6. The method of claim 5, wherein the isolation trench has a width of 1.0-3.0 μm and a depth of 15-30 μm, the isolation trench having a width to depth ratio of 1: 5-1: 20.

7. the method of claim 5, further comprising forming at least a medium voltage NMOS device and a medium voltage PMOS device in an epitaxial layer of the high side drive circuit region, the method of forming the medium voltage NMOS device comprising:

Forming the first buried layer of a second doping type on the substrate of a first doping type;

forming the epitaxial layer of the first doping type on the first buried layer;

forming the high-voltage well with the second doping type in the epitaxial layer, wherein the high-voltage well in the high-voltage LDMOS device and the high-voltage well in the medium-voltage NMOS device are formed at the same time;

forming a low-voltage well of the first doping type in the epitaxial layer of the medium-voltage NMOS device, wherein the low-voltage well of the first doping type in the high-voltage LDMOS device and the low-voltage well of the first doping type in the medium-voltage NMOS device are formed simultaneously;

forming a low-voltage well of a second doping type in the epitaxial layer and the high-voltage well of the medium-voltage NMOS device;

forming the second buried layer of a first doping type in the epitaxial layer of the medium voltage NMOS device, wherein the second buried layer is positioned below the low-voltage well of the first doping type and the low-voltage well of the second doping type in the epitaxial layer and is in contact with the low-voltage well of the first doping type and the low-voltage well of the second doping type, and the second buried layer in the high voltage LDMOS device and the second buried layer in the medium voltage NMOS device are formed simultaneously;

Forming the field oxide layer on the high voltage well in the epitaxial layer, the low voltage well of the first doping type in the epitaxial layer, the low voltage well of the second doping type in the epitaxial layer and the epitaxial layer of the medium voltage NMOS device, wherein the field oxide layer in the high voltage LDMOS device and the field oxide layer in the medium voltage NMOS device are formed simultaneously;

forming an ohmic contact region of the first doping type in the low-voltage well of the first doping type in the epitaxial layer of the medium-voltage NMOS device, wherein the ohmic contact region of the first doping type in the high-voltage LDMOS device and the ohmic contact region of the first doping type in the medium-voltage NMOS device are formed simultaneously;

forming ohmic contact regions of the second doping type in the low-voltage well of the first doping type in the epitaxial layer of the medium-voltage NMOS device and the low-voltage well of the second doping type in the epitaxial layer, wherein the ohmic contact regions of the second doping type in the high-voltage LDMOS device and the ohmic contact regions of the second doping type in the medium-voltage NMOS device are formed simultaneously; and

forming the gate structure on the field oxide layer of the medium voltage NMOS device, the low voltage well of the first doping type in the epitaxial layer, and the low voltage well of the second doping type in the epitaxial layer, wherein the gate structure in the high voltage LDMOS device and the gate structure in the medium voltage NMOS device are formed simultaneously;

In the medium voltage NMOS device, the high voltage well is positioned at two sides of the medium voltage NMOS device and connected with the first buried layer, and the low voltage well with the second doping type and the first buried layer are isolated through the second buried layer and the epitaxial layer.

8. The method according to any one of claims 5-7, further comprising: one or more devices of low-voltage NMOS, low-voltage PMOS, triode, resistor and capacitor are formed.