CN117172071B - A rapid thermal analysis method for chips based on advanced process packaging structure - Google Patents
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Abstract
本发明涉及集成电路热分析技术，提出了一种基于先进工艺封装结构下的芯片快速热分析方法，包括步骤：步骤1：先离散集成电路封装结构，再构建热分析系统；步骤2：使用LR‑ADI进行分解计算；步骤3：进行SVD分解；步骤4：计算状态空间转移矩阵；步骤5：截断处理；步骤6：构建降阶热分析模型；步骤7：求解微分方程组；步骤8：计算芯片核心温度。本发明使用模型降阶方法进行热仿真的方式，在保证一定精度下，有效地提升运行效率，达到温度预测、仿真闭环的目的。
The present invention relates to integrated circuit thermal analysis technology, and proposes a fast thermal analysis method for chips based on advanced process packaging structure, including the following steps: Step 1: discretize the integrated circuit packaging structure first, and then build a thermal analysis system; Step 2: use LR-ADI to perform decomposition calculation; Step 3: perform SVD decomposition; Step 4: calculate the state space transfer matrix; Step 5: truncation processing; Step 6: construct a reduced-order thermal analysis model; Step 7: solve a set of differential equations; Step 8: calculate the core temperature of the chip. The present invention uses a model reduction method to perform thermal simulation, which effectively improves the operating efficiency while ensuring a certain accuracy, and achieves the purpose of temperature prediction and closed-loop simulation.
Description
Technical Field
The invention relates to an integrated circuit thermal analysis technology, which can be applied to dynamic temperature control management of EDA and chips.
Background
Temperature is an important factor affecting chip performance. In the chip, when current flows through the conductor, joule heat is inevitably generated, and if heat is not normally and timely dissipated, the temperature of the chip is rapidly increased. If the temperature is too high, the probability of short circuit caused by breakdown of a transistor can be increased due to overheat excitation of high-energy carriers when the integrated circuit works, the performance of the transistor can change along with the temperature, part of the circuit can not work normally due to the performance change at high temperature, and the service life of a lead is reduced due to high-temperature electromigration promotion.
Contemporary 3D packaging techniques and other innovative integrated packaging methods, while offering advantages, introduce some important issues regarding thermal analysis, including issues such as thermal coupling effects, temperature non-uniformity, design limiting heat dissipation paths, selection of thermally conductive materials, etc.
In order to ensure that the IC system cannot damage a hardware structure due to high temperature in the operation process, a dynamic heat management technology is particularly important, in the dynamic heat management technology, power consumption, temperature and a dynamic regulation algorithm are integrated, a thermal analysis algorithm can conduct rapid thermal simulation calculation according to real-time power consumption data of different positions, the temperature change condition of each part of a chip in a future period is predicted, and then the regulation and control of a DVFS strategy are conducted on parts which are about to exceed a temperature threshold in advance, so that the purpose of protecting the chip is achieved.
Recently, the field of thermal simulation has emerged a number of thermal analysis methods for integrated circuits, including steady state and transient thermal analysis methods, particularly thermal analysis methods for three-dimensional chip and system-in-package. These methods can be largely classified into two major categories, the resolution/semi-resolution type method and the numerical type method.
The analytic/semi-analytic method calculates the temperature distribution of the integrated circuit by constructing a simplified thermal resistance network, and has lower calculation complexity but lower precision.
The numerical method is to solve the ordinary differential equation set obtained after the discretization by a finite element method, a finite volume method, a finite difference method and other discrete integrated circuit heat conduction equations and then by a direct method, an iteration method and other methods. In practice, the numerical method is used to solve the problem of thermal analysis with high accuracy but high computational complexity, which is usually caused by excessive grid numbers in order to ensure accuracy in discrete processes. But in practice, for dynamic thermal temperature control processes, only a few points in the chip, called hotspots, are concerned, and the temperature of all the positions of the chip is not concerned, which gives the model order reduction method a useful choice.
There are two main classes of model order reduction methods, namely a balance method based on singular value decomposition (Singular Value Decomposition, SVD) and a moment matching (Moments Matching) method based on Krylov subspace theory. The moment matching method based on the Krylov subspace theory has the advantages of small calculated amount and high speed in the process of processing the reduction of a large dynamic system, and can match a plurality of moments of the transfer function of the original system at a certain point. By means of moment matching, the complexity of the system can be effectively reduced. However, this approach has some drawbacks. Most importantly, the stability of the reduced order system cannot be guaranteed, and the error range between the reduced order system and the original system is difficult to obtain. The balance method is a reducing method based on a linear system theory concept, and has the advantages that the structural characteristics of a reducing model can be maintained, and the cutting-off and the reducing can be carried out according to the size of singular values of the system. Through a balance method, global error constraint can be set, so that the precision of the model after the order reduction is controlled. However, the balancing method also has some drawbacks, especially when dealing with a large dynamic system, because of the need to solve two Lyapunov equations of higher order, the calculation complexity is higher, and the memory requirement of the computer is also higher.
Disclosure of Invention
Aiming at the problems that the equation scale is too large and quick and effective calculation cannot be realized due to the fact that a numerical method is used for chip thermal simulation in the prior art, the invention provides a chip quick thermal analysis method based on an advanced process packaging structure.
The technical scheme is as follows:
a chip rapid thermal analysis method based on advanced technology packaging structure comprises the following steps:
step 1, firstly, dispersing an integrated circuit packaging structure, and then constructing a thermal analysis system;
step 2, performing decomposition calculation by using LR-ADI;
Step 3, SVD decomposition is carried out;
step 4, calculating a state space transition matrix;
step 5, cutting off;
Step 6, constructing a reduced-order thermal analysis model;
Step 7, solving a differential equation set;
and 8, calculating the core temperature of the chip.
The invention uses a model order reduction method to carry out thermal simulation, effectively improves the operation efficiency under the condition of ensuring certain precision, and achieves the aims of temperature prediction and simulation closed loop.
Drawings
FIG. 1 is a flow chart of a method according to an embodiment of the invention.
FIG. 2 is a graph showing a portion of the eigenvalues used in the balance cut-off error analysis of the test case of the present invention.
FIG. 3 is a graph showing the temperature comparison between the original system and the reduced order system of the test case of the present invention.
Detailed Description
The invention discloses a chip rapid thermal analysis method based on an advanced process packaging structure, which is characterized in that a finite volume method is used for further reducing the order of the packaging structure under the advanced process basically, namely a state space transfer matrix is solved by a balance cut-off method, and an original RC network is projected to a low-order space by cutting off characteristic values under the existing precision and speed limitation according to error theory analysis, so that model order reduction is achieved, and an acceleration operation effect is achieved.
The technical scheme provided by the application is further described below with reference to specific embodiments and attached drawings. The advantages and features of the present application will become more apparent in conjunction with the following description.
Examples
A chip rapid thermal analysis method based on advanced technology packaging structure, as shown in figure 1, comprises the following steps:
step 1, discrete integrated circuit packaging structure and then constructing a thermal analysis system
Step 1.1 spatially discretizes the package structure of the integrated circuit using a finite volume method (Finite Volume Method, FVM) to obtain the following formula:
Wherein G ε R n×n is a thermal conductivity matrix, symmetrically positive, including equivalent thermal conductivity to the boundary, x ε R n represents the temperature of the full-field junction, C ε R n×n is a matrix composed of geothermal energy, u (t) ε R p is a vector composed of the current heat source, E ε R n×p is a correlation matrix of the input heat source and junction temperature.
Note that, among them,
N represents the dimension of the system state space, namely the number of the total points of the system after the chip is subjected to space dispersion;
m represents the dimension of the output vector, namely the number of hotspots;
p represents the dimension of the input vector, i.e. the number of the current heat source nodes.
For hotspots (hotspots), the conversion can be done by:
y(t)=Lx(t)
Wherein y ε R m consists of the hotspot temperature and L ε R m×n is the correlation matrix of state and hotspot temperature.
Step 1.2 converts it to a "linear time independent" system equation (LINEAR TIME-invariant, LTI) to construct a thermal analysis system, as shown in the following formula:
wherein a= -C -1G,B＝C-1 E.
Step 2, performing decomposition calculation by using LR-ADI
By adopting a balanced cut-off method, specifically analyzing and observing Gramian a matrix Q and an arrival Gramian matrix P, firstly performing conversion projection of a state space, and solving the conversion projection is equivalent to solving a Lyapunov matrix equation, as follows:
AP+PAT+BBT＝0,ATQ+QA+LTL=0
The Lyapunov matrix equation and Low-Rank decomposition are further solved by using an LR-ADI (Low Rank-ALTERNATIVE DIRECTION IMPLICIT) method, namely, the method is converted into the method for solving P (SS) T and Q (RR) T.
Specifically, step 2 includes:
step 2.1 solves for P≡SS T.
Step 2.1.1 specifies a set of shift parameters a 1,And residual tol.
Step 2.1.2 initializes a temporary variable S 0＝[],W0 =b, i=1.
Step 2.1.3 sets a circulation condition II W i-1‖2 not less than tol:
Step 2.1.4 solving for (A+α) iI)Vi＝Wi-1
Step 2.1.5W i＝Wi-1-2Re(αi)Vi
Step 2.1.6 ream
Step 2.1.7 let i=i+1
Steps 2.1.4-2.1.7 are performed in a loop until the loop condition is not met, i.e., iiw i-1‖2 < tol.
When i=s, the loop is terminated, giving S s.
Step 2.1.8 lets s=s s.
Step 2.2 solves for Q≡RR T.
Step 2.2.1 specifies a set of shift parameters a 1,And residual tol.
Step 2.2.2 initializes a temporary variable R 0＝[],W0 =l, i=1.
Step 2.2.3 sets a circulation condition II W i-1‖2 not less than tol:
step 2.2.4 solving for (A+α) iI)Vi＝Wi-1
Step 2.2.5W i＝Wi-1-2Re(αi)Vi
Step 2.2.6 ream
Step 2.2.7 let i=i+1
Steps 2.2.4-2.2.7 are performed in a loop until the loop condition is not met, i.e. iiw i-1‖2 < tol.
When i=s, the cycle ends, yielding R s.
Step 2.2.8 let r=r s.
Step 3, SVD decomposition is carried out
The eigenvalue decomposition (Singular Value Decomposition, SVD) is calculated, with R TS＝U∑VT, where Σ=diag (σ 1,σ2,…,σn),σi is Hankel eigenvalues (HSVs), which are important values for error estimation in the balanced cut-off method.
Step 4, calculating state space transition matrix
Available state space transition matrixBy transferring the matrix, a new system can be obtainedIs a matrix of observations and arrival of (a)
Performing balance conversion:
Step 5, cutting off
And performing truncation processing according to the error, namely removing the inconveniently observed and inconveniently controlled states to obtain projection matrixes V BT and W BT.
I r represents an identity matrix of order r
Step 6, constructing a reduced order thermal analysis model
A reduced order system (Reduced Order Model, ROM) is available,And
That is, the reduced order system can be expressed as:
Wherein,
Step 7, solving differential equation set
For solving differential equationsThe direct use of the analytical solution is not cost-effective in the transient calculation of the practical application scenario, firstly, it needs to be recalculated for each time of interest, which consumes a lot of calculation resources, secondly, in the analytical solution, it needs to reach a steady-state temperature value of the chip, and in the dynamic temperature control scenario, it needs to predict the temperature according to the different power consumption prediction values, which limits the application of the analytical solution, so in the embodiment, the backward Euler method in the numerical solution is selected to solve, and there is
Where Δt represents the time step.
For the power consumption density, the variation of the sub-field (time step) on the time axis is limited to two cases, including u (t) being kept constant over the interval [ t 0,t0 +Δt ] and u (t) being kept constant over the interval [ t 0,t0 +Δt ]. For both cases, the integration results are identical, so the above formula is simplified as follows:
The discrete iteration format is as follows:
Solving the linear equation set to obtain the corresponding time
Step 8, calculating the core temperature of the chip
The temperature at the core of the chip is
Test case
This example was further tested using MATLAB 2017 b.
After the industrial integrated circuit example is spatially discretized by using a finite volume method, a 59472-order thermal analysis system is formed, 284 sources are used, the reduced-order thermal analysis system is 100-order by adopting a balance cut-off method and an LR-ADI method, 12 outputs are selected and are all core heat sources, the calculated preparation time is removed, and the time acceleration rate is 182 times by adopting an iteration method to solve.
FIG. 2 shows the Hankel eigenvalues used for error analysis of this test case using the balanced cut-off method;
FIG. 3 shows a temperature comparison graph of the original system and the reduced order system, wherein the average error is-0.6918%, and the analysis requirement is met.
The above description is only illustrative of the preferred embodiments of the application and is not intended to limit the scope of the application in any way. Any alterations or modifications of the application, which are obvious to those skilled in the art based on the teachings disclosed above, are intended to be equally effective embodiments, and are intended to be within the scope of the appended claims.
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| CN101976281A (en) * | 2010-10-15 | 2011-02-16 | 复旦大学 | Steady-state thermal analysis method of stack type three-dimensional FPGA (Field Programmable Gate Array) chip |
| CN106886621A (en) * | 2015-12-16 | 2017-06-23 | 复旦大学 | A kind of integrated circuit heat analysis method based on polymerization depression of order |
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