CN117170577A - Cross temperature compensation in non-volatile memory devices - Google Patents

Abstract

The present application relates to cross temperature compensation in non-volatile memory devices. Systems and methods are disclosed including a memory device and a processing device operably coupled to the memory device. The processing device may perform operations comprising: performing a first read operation on the memory device to retrieve first data; determining, from the first data, second data indicative of a write temperature associated with the first data, wherein the write temperature is indicative of a temperature measured during a write operation; determining a read voltage value based on the second data; and performing a second read operation on the memory device using the read voltage value to obtain the first data.

Description

Cross-temperature compensation in non-volatile memory devices

Technical field

Embodiments of the present disclosure relate generally to memory subsystems, and more particularly to cross-temperature compensation in non-volatile memory devices.

Background technique

A memory subsystem may include one or more memory devices that store data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, a host system may utilize a memory subsystem to store data at and retrieve data from a memory device.

Contents of the invention

In one aspect, the present application provides a system that includes: a memory device; and a processing device operably coupled to the memory device, the processing device configured to perform operations including: performing on the memory device a first read operation to retrieve first data; determining from the first data second data indicative of a write temperature associated with the first data, wherein the write temperature is indicative of a temperature measured during a write operation temperature; determining a read voltage value based on the second data; and performing a second read operation on the memory device using the read voltage value to obtain the first data.

In another aspect, the present application provides a method that includes receiving, by a processor, first data obtained from a memory page of a memory device, wherein the first data includes host data and write temperature data, wherein the The memory page is referenced by a first read command in a set of read commands; determining a read voltage value based on the write temperature data; instructing a memory device by applying the read voltage value to the second memory page A read operation is performed on a second memory page referenced by a second read command in the set of read commands.

In another aspect, the present application provides a non-transitory computer-readable storage medium including instructions that, when executed by a processing device operably coupled to a memory, perform operations including: operating on the memory The apparatus performs a first read operation to retrieve first data; determine second data from the first data indicative of a write temperature associated with the first data; and determine a read voltage value based on the second data ;Perform a second read operation on the memory device using the read voltage value to obtain the first data.

Description of drawings

The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure.

Figure 1 illustrates an example computing system including a memory subsystem in accordance with some embodiments of the present disclosure.

Figure 2 is a flowchart of an example method for performing a write operation in accordance with some embodiments of the present disclosure.

Figure 3 is a flowchart of an example method for performing a read operation in accordance with some embodiments of the disclosure.

Figure 4 is an illustrative example of a temperature compensation data structure in accordance with some embodiments of the present disclosure.

Figure 5A is a block diagram illustrating voltage distribution shifting in accordance with some embodiments of the present disclosure.

Figure 5B is a block diagram illustrating voltage distribution shifting in accordance with some embodiments of the present disclosure.

Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate.

Detailed ways

Aspects of the present disclosure relate to cross-temperature compensation in non-volatile memory devices. A memory subsystem may be a memory device, a memory module, or a hybrid of memory devices and memory modules. Examples of storage devices and memory modules are described below in conjunction with FIG. 1 . Generally speaking, a host system may utilize a memory subsystem that includes one or more components, such as a memory device that stores data. The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

The memory subsystem may include high-density non-volatile memory devices where it is desirable to retain data when no power is supplied to the memory device. One example of a non-volatile memory device is a NAND memory device. Other examples of non-volatile memory devices are described below in connection with FIG. 1 . A non-volatile memory device is a package of one or more die. Each die may contain two or more planes. For some types of non-volatile memory devices (eg, NAND devices), each plane contains a set of physical blocks. In some implementations, each block may contain multiple sub-blocks. Each plane carries a matrix of memory cells formed on a silicon wafer and bonded by conductors called word lines and bit lines, such that word lines bond multiple memory cells forming rows of the memory cell matrix, and bit lines bond form the memory cell matrix. columns of multiple memory cells.

Depending on the cell type, each memory cell may store one or more bits of binary information, and have various logic states related to the number of bits stored. Logic states may be represented by binary values such as "0" and "1" or combinations of such values. Memory cells can be programmed (written to) by applying a specific voltage to the memory cell, which causes charge to be retained by the memory cell, allowing modulation of the voltage distribution produced by the memory cell. A group of memory cells, called a memory page, can be programmed together in a single operation, for example, by selecting consecutive bit lines.

Various data operations can be performed by the memory subsystem. Data operations may be host-initiated operations. For example, the host system may initiate data operations (eg, write, read, erase, etc.) on the memory subsystem. The host system may send access commands (eg, write commands, read commands) to the memory subsystem, such as to store data on and read data from memory devices at the memory subsystem. Data to be read or written as specified by a host request is hereinafter referred to as "host data". The host request may contain logical address information (eg, logical block address (LBA), namespace) of the host data, which is the location where the host system associates the host data. Logical address information (eg, LBA, namespace) may be part of the metadata of the host data. Metadata may also include error-handling data (such as error correction code (ECC) codeword parity data), data versions (such as to distinguish the age of written data), valid bitmaps (which LBAs or logical transfer units contain valid data), etc.

A memory device includes a plurality of memory cells capable of storing one or more bits of information depending on the memory cell type. A memory cell can be programmed (written to) by applying a specific voltage to the memory cell, which causes charge to be retained by the memory cell, said voltage being called the "threshold voltage" and denoted Vt.

Precise control of the amount of charge stored by a memory cell allows multiple logic levels to be established, effectively allowing a single memory cell to store multiple bits of information. A read operation can be performed by comparing the measured threshold voltage (V _t ) exhibited by the memory cell to one or more reference voltage levels to operate between two logic levels in a single-level cell (SLC) and in multi-level The unit performs by distinguishing between multiple logic levels. In various embodiments, a memory device may include multiple portions, including, for example, one or more portions of SLC memory in which sub-blocks are configured as multi-level cells that can store multiple bits of information per cell. (MLC) memory and/or one or more portions of (three-level cell) TLC memory that can store three bits of information per cell. The voltage levels of the memory cells in a TLC memory form a set of 8 programming profiles representing 8 different combinations of the three bits stored in each memory cell. Depending on how they are configured, each physical page in one of the sub-blocks can contain multiple page types. For example, a physical page formed from single-level cells (SLC) has a single page type called a lower logical page (LP). Multi-level cell (MLC) physical page types can include LP and upper logical page (UP), TLC physical page types are LP, UP, and extra logical page (XP), and QLC physical page types are LP, UP, XP, and top Logical page (TP). For example, a physical page formed by QLC memory type memory cells may have a total of four logical pages, where each logical page may store data that is different from the data stored in other logical pages associated with that physical page. .

A memory device may have a voltage distribution that is narrower than the operating range of control voltages tolerated by the cells of the device. Therefore, multiple distributions (with "valleys" between distributions) can be fit into the operating voltage window, allowing storage and reliable detection of multiple bits per cell, e.g. 2 ³ = 8 distributions (7 valleys) for TLC , 2 ² of MLC = 4 distributions (3 valleys) and so on. Distributions are interspersed between distributions in voltage intervals ("valley margins") where none (or very few) of the device's memory cells have their threshold voltages. Thus, such valley margins can be used to separate various charge states—the logic state of a cell can be determined by detection during a read operation by applying a read voltage corresponding to each valley. This effectively allows a single memory cell to store multiple bits of information: a memory cell operating in 2 ^N distributions (which are also called levels) is able to store N bits of information. During the read operation, 2 ^N-1 read voltages are applied to distinguish 2 ^N distributions. Specifically, a read operation may be performed by comparing the measured threshold voltage _VT exhibited by the memory cell to one or more reference voltage levels corresponding to known valleys (eg, centers of valleys) of the memory device.

In some cases, the memory system may operate in an environment with varying temperatures (eg, between -40 and 90 degrees Celsius). Temperature changes between a write operation on a memory cell and a subsequent read operation on the memory cell can affect the charge stored in and read from the memory cell. This change in temperature between a write operation on a memory cell and a subsequent read operation on the memory cell may be referred to as the crossover temperature. For example, when a memory cell is programmed in a hotter temperature range (60 to 70°C) and read in a cooler temperature range (20 to 25°C) or when a memory cell is programmed in a cooler temperature range (20 to 25°C ) and reading in the hotter temperature range (65 to 70°C), cross-temperature conditions can occur. For illustrative purposes, the temperature ranges (20 to 25°C) and (65 to 70°C) are used, but other temperature ranges are possible.

Referring to Figure 5A, for an example, if a memory cell in a QLC memory is programmed at 70°C with a voltage level of 2V corresponding to the data value '0100' and the temperature over time becomes 25°C, then the voltage level may have shifted to 2.15V. Depending on how the threshold voltage range is defined in the memory cell, the actual read voltage may reflect a different data value than the programmed data value (eg, '0101'). This shift can result in an increase in raw bit error rate (RBER), which may exceed the error correction capabilities of the underlying error correction code (ECC).

Referring to Figure 5B, for another example, if a memory cell in a QLC memory is programmed with a voltage level of 2V corresponding to the data value '0100' at 25°C and the temperature changes over time as the memory cell is read into 70°C, then the apparent voltage level may have shifted to 1.85V. Depending on how the threshold voltage range is defined in the memory cell, the apparent read voltage can reflect different data values (e.g. '0011'). This shift can result in an increase in raw bit error rate (RBER), which may exceed the error correction capabilities of the underlying ECC.

In response to the RBER exceeding the error correction capabilities of the underlying ECC, some systems may perform a data recovery process to attempt to recover the data. The data recovery process may include one or more error handling operations regarding data items that have been retrieved from the memory device. In one example, the error handling operation may include one or more read retries using different parameters (eg, changes in read voltage) compared to the initial read operation performed on the memory cell. In another example, error handling operations may include "deep error handling techniques" such as forward error correction (FEC) with different versions of reliability information, hybrid automatic repeat request (HARQ), soft bit information request (e.g., data on the reliability of stored bits), histogram refinement (e.g. valley placement data), etc.

The trigger rate is an estimate of how often the data recovery process is performed. High trigger rates are associated with poor memory subsystem performance because the memory device requires additional computational and time resources to retrieve stored data.

Some memory subsystems reduce the impact of cross-temperature conditions that impose read voltage offsets based on current memory device temperature during read operations. However, these systems fail to account for the temperature of the memory device during write operations. As a result, these systems make assumptions that may be incorrect (eg, using a predetermined reference temperature), resulting in increased RBER and higher trigger rates. Therefore, mechanisms and methods for accurately determining cross-temperature compensation values are desired.

Aspects of the present disclosure address the above and other shortcomings by performing cross-temperature compensation in memory devices. In an illustrative example, during a write operation, the memory subsystem controller may store a temperature value that reflects the current temperature of the memory device. This write temperature value can be stored as metadata attached to the host data of the write operation. During a read operation, the memory subsystem controller may retrieve the write temperature value and determine the read voltage to account for cross temperature conditions. For example, the controller may extract a write temperature value for a previous write, determine a read offset voltage value that reflects the temperature difference between the write operation and the current temperature of the memory device, and compare the resulting temperature during subsequent read operations. Describe the read offset voltage value and read voltage level. The read offset voltage value may be determined in response to the original read operation returning a high error rate.

In some embodiments, the memory subsystem controller may measure temperature using a temperature measurement device (eg, thermocouple, thermometer, infrared sensor, etc.). The temperature measurement device may be a hardware device that is part of and operated by the memory subsystem controller. In some embodiments, the memory subsystem controller may retrieve temperature data from the memory device. For example, a memory device may include a temperature measurement device, and the memory subsystem controller may periodically poll (eg, once per second) the memory device to retrieve temperature data. The memory subsystem controller may then append the write temperature data (eg, the temperature value) to the host data and instruct the memory device to program the additional write data (host data with the temperature data appended) to the memory location. In some embodiments, the memory subsystem controller may append write temperature data to each specific memory granularity of the write command (eg, memory page, large memory page, memory sector, etc.). For example, if a write command contains five memory pages of host data, each of the memory pages may be appended with corresponding write temperature data.

In some embodiments, in response to receiving a read command, the memory subsystem controller may first subtract a default write temperature value (during programming and operation of the memory subsystem) from a current temperature value (eg, the current temperature of the memory subsystem). /or set during calibration, set by firmware update, set by user input, etc.) (or vice versa) to determine the temperature compensation value. The memory subsystem controller may then use the temperature compensation value to determine the read offset voltage value. The read offset voltage value may be a voltage offset value applied to the base read voltage value to produce an adjusted read voltage value. The adjusted read voltage value may be applied to a group of memory cells during a read operation. To determine the read offset voltage value associated with the temperature compensation value, the memory subsystem controller may perform a lookup in a data structure, apply a formula or equation to the read offset voltage value, etc. The memory subsystem controller may then execute the read command using the adjusted read voltage value and receive additional read data referenced by the read command.

The memory subsystem controller may obtain the write temperature data from the additional read data and update the current write temperature data associated with the read command. The memory subsystem controller may perform a data integrity check on the retrieved host data to verify that the data stored at the memory cells of the memory page does not contain any errors or that the number of errors is below a predetermined threshold. The data integrity check may identify one or more data integrity indicators (eg, BEC, RBER, etc.) and compare the values of the data integrity indicators to threshold criteria. The memory subsystem controller may use the new current temperature value if the data integrity metric meets the threshold criteria (eg, the BEC or RBER value is above the threshold) (indicating a high error rate associated with the data stored at the memory page) and the written temperature value from the additional read data determines the new temperature compensation value. The memory subsystem controller may then determine a new adjusted read voltage value using the new temperature compensation value and execute the read command using the new adjusted read voltage value. If the data integrity metric fails to meet the threshold criteria (eg, the BEC or RBER value is below the threshold), the memory subsystem controller may use the adjusted read voltage value on subsequent read commands.

Advantages of the present disclosure include, but are not limited to, improving memory subsystem performance by reducing trigger rates due to cross temperature conditions. This results in improvements in memory subsystem performance, reliability and operating life due to reduced trigger rates.

Figure 1 illustrates an example computing system 100 including a memory subsystem 110 in accordance with some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (eg, memory device 140), one or more non-volatile memory devices (eg, memory device 130), or a combination thereof.

Memory subsystem 110 may be a storage device, a memory module, or a hybrid of storage devices and memory modules. Examples of storage devices include solid state drives (SSD), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD ) card and hard disk drive (HDD). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

Computing system 100 may be, for example, a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (such as an aircraft, drone, automobile, or other vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer Computing devices (eg, embedded computers included in vehicles, industrial equipment, or networked commercial devices) or such computing devices that include memory and processing devices.

Computing system 100 may include a host system 120 coupled to one or more memory subsystems 110 . In some embodiments, host system 120 is coupled to different types of memory subsystems 110 . FIG. 1 illustrates an example of a host system 120 coupled to a memory subsystem 110. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, Includes connections such as electrical connections, optical connections, magnetic connections, etc.

Host system 120 may include a processor chipset and a software stack executed by the processor chipset. A processor chipset may include one or more cores, one or more caches, a memory controller (eg, NVDIMM controller), and a storage protocol controller (eg, PCIe controller, SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to and read data from memory subsystem 110.

Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect Express (PCIe) interface, Universal Serial Bus (USB) interface, Fiber Channel, Serial Attached SCSI (SAS) ), double data rate (DDR) memory bus, small computer system interface (SCSI), dual in-line memory module (DIMM) interface (for example, a DIMM slot interface that supports double data rate (DDR)), etc. A physical host interface may be used to transfer data between host system 120 and memory subsystem 110 . When memory subsystem 110 is coupled to host system 120 through a physical host interface (eg, PCIe bus), host system 120 may further utilize an NVM Express (NVMe) interface to access components (eg, memory device 130). The physical host interface may provide an interface for communicating control, address, data, and other signals between memory subsystem 110 and host system 120 . Figure 1 illustrates memory subsystem 110 as an example. Generally speaking, host system 120 may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and/or a combination of communication connections.

Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and/or volatile memory devices. Volatile memory devices, such as memory device 140, may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

Some examples of non-volatile memory devices, such as memory device 130, include NAND-type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are NAND-type flash memories and write-in-place memories. Crosspoint array of volatile memory cells. A crosspoint array of non-volatile memory cells can perform bit storage based on volume resistance changes combined with a stackable cross-gate format data access array. Therefore, in contrast to many flash-based memories, crosspoint non-volatile memories can perform in-place write operations, where the non-volatile memory cells can be programmed without the need to first erase the non-volatile memory cells . NAND flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

Each of memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), can store multiple bits per cell. In some embodiments, each of memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of memory device 130 may be grouped into pages, which may refer to logical units of the memory device for storing data. For some types of memory, such as NAND, pages may be grouped to form blocks.

Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memory (eg, 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of non-volatile memory. Sexual memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), Magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR ) flash memory and electrically erasable programmable read-only memory (EEPROM).

Memory subsystem controller 115 (or, for simplicity, controller 115 ) may communicate with memory device 130 to perform operations such as reading data, writing data, or erasing data at memory device 130 , and other such operations. Memory subsystem controller 115 may include hardware, such as one or more integrated circuits and/or discrete components, buffer memory, or a combination thereof. Hardware may include digital circuitry with dedicated (ie, hard-coded) logic for performing the operations described herein. Memory subsystem controller 115 may be a microcontroller, special purpose logic circuitry (eg, field programmable gate array (FPGA), application specific integrated circuit (ASIC), etc.), or other suitable processor.

Memory subsystem controller 115 may be a processing device that includes one or more processors (eg, processor 117 ) configured to execute instructions stored in local memory 119 . In the illustrated example, local memory 119 of memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of memory subsystem 110 . The operations include handling communications between memory subsystem 110 and host system 120 .

In the illustrated example, local memory 119 of memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of memory subsystem 110 . The operations include handling communications between memory subsystem 110 and host system 120 .

In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, and the like. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although example memory subsystem 110 in FIG. 1 has been illustrated as including memory subsystem controller 115, in another embodiment of the present disclosure, memory subsystem 110 does not include memory subsystem controller 115 and may instead Reliance on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

Generally speaking, memory subsystem controller 115 may receive commands or operations from host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve desired access to memory device 130 . Memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, discarded item collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and logical block addresses associated with memory device 130 ( For example, address translation between logical block address (LBA), namespace) and physical address (such as physical MU address, physical block address). Memory subsystem controller 115 may further include host interface circuitry to communicate with host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access memory device 130 and also convert responses associated with memory device 130 into information for host system 120 .

Memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, memory subsystem 110 may include a cache or buffer (eg, DRAM) and address circuitry (eg, row decoders and column decoders) that may receive addresses from memory subsystem controller 115 and decode all address to access the memory device 130.

In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130 . An external controller (eg, memory subsystem controller 115) may externally manage memory device 130 (eg, perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes on-die control logic (eg, local controller 135 ) and a controller for media management within the same memory device package (eg, memory The original memory device of the subsystem controller 115). An example of a managed memory device is a managed NAND (MNAND) device.

In one embodiment, memory subsystem 110 includes a media management component 113 that may be used to append write temperature data to user data and determine temperature compensation values for read operations performed on memory device 130 and memory device 140 . In some embodiments, memory subsystem controller 115 includes at least a portion of media management component 113 . In some embodiments, media management component 113 is part of host system 120, an application, or an operating system. In other embodiments, local media controller 135 includes at least a portion of media management component 113 and is configured to perform the functionality described herein. Media management component 113 may communicate directly with memory devices 130 and 140 via a synchronization interface. Additionally, data transfer between memory device 130 and memory device 140 may be accomplished within memory subsystem 110 without accessing host system 120 .

The media management component 113 may determine write temperature data for each write operation performed on the memory devices 130, 140 and append the write temperature data to the host data for the corresponding write operation. The media management component may further determine a temperature compensation value and use the temperature compensation value to determine a read offset value to be used during read operations on memory devices 130, 140. Additional details regarding the operation of media management component 113 are described below.

In some embodiments, memory subsystem controller 115, memory device 130, and/or memory device 140 may include a temperature measurement device. The temperature measuring device may be a thermocouple, thermometer, infrared sensor or any other tool capable of determining temperature data such as an operating temperature value. In some embodiments, the temperature measurement device may be a hardware device that is part of and operated by memory subsystem controller 115 . In some embodiments, the temperature measurement device may be a hardware device that is part of and operated by the memory device 130, 140. In such embodiments, memory devices 130 , 140 may periodically send temperature data to media management component 113 , and/or media management component 113 may request (eg, using polling or other requesting methods) data from memory device 130 , temperature data of 140.

Once received by media management component 113, the temperature data may be stored in a register (eg, an 8-bit register) as part of temperature compensation component 113, in a specific memory location on a volatile memory device (eg, memory device 140), locally. In a memory cache on memory 119, a data structure (a format having a set of data values, relationships therebetween, and/or functions or operations applicable to the data values), etc. In some embodiments, each subsequently received or determined temperature data may replace previously stored temperature data. For example, each new operating temperature value received by the media management component 113 from the memory devices 130 , 140 may replace the previously stored operating temperature value in a memory cache or register on the memory subsystem controller 115 . In other embodiments, multiple sets of temperature data may be stored by media management component 113 .

Figure 2 is a flowchart of an example method 200 for performing a write operation in accordance with some embodiments of the present disclosure. Method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, special purpose logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., running or executing on a processing device instructions) or a combination thereof. In some embodiments, method 200 is performed by media management component 113 of FIG. 1 . Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be construed as examples only and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Therefore, not all procedures may be required in every embodiment. Other process flows are possible.

At operation 210, processing logic receives a write command. The write command may be initiated by the host (eg, host 120) or by a memory subsystem controller (eg, memory subsystem controller 113). In some embodiments, in response to receiving a write command, processing logic identifies one or more word lines addressing a set of memory cells (eg, a page) onto which data referenced by the write command is to be programmed.

At operation 220, processing logic determines the operating temperature of the memory subsystem. In some embodiments, processing logic determines the operating temperature of memory device subsystem 110 by performing a temperature reading using a temperature measurement device connected to memory subsystem controller 115 . For example, processing logic may obtain an operating temperature value from a temperature measurement device.

In some embodiments, processing logic requests operating temperature values from a memory device (eg, memory device 130, 140) from a temperature measurement device connected to memory device 130, 140. In response to the request, processing logic may receive from memory device 130, 140 the operating temperature value retrieved from the temperature measurement device.

In some embodiments, the processing logic obtains the operating temperature value from the memory device using a polling method. For example, processing logic may periodically request and/or receive operating temperature values from memory devices 130, 140. The operating temperature value may be stored, for example, in a memory cache located on memory subsystem controller 115 or memory device 140 . To determine the temperature of the memory subsystem at operation 220, processing logic may retrieve the most recently received temperature value stored on a cache or register.

At operation 230, processing logic appends the operating temperature value (eg, the write temperature value) to the write data of the write command. The write data may include data to be programmed by the processing logic into the memory device. For example, a write temperature value may be added to the write data as metadata. Other metadata that can be added to the written data includes error handling data (such as error correction code (ECC) codeword parity data), data version, valid bitmap (which LBAs or logical transfer units contain valid data), etc. In some embodiments, processing logic may append the write temperature value of the memory page referenced by the write operation. For example, if a write command contains write data to be programmed into three memory pages, processing logic may append an operating temperature value to the data for each memory page. In other embodiments, the write temperature value may be appended to the data at any size granularity. In some embodiments, processing logic may encode the operating temperature value using, for example, ECC codeword parity data.

At operation 240, processing logic programs additional write data (eg, write data and write temperature values) to the identified set of memory cells. For example, additional write data may be retrieved from the memory device or cache and programmed onto the memory cell. To program additional write data, processing logic may apply a specific voltage to each memory cell, which causes charge to be retained by each memory cell.

Figure 3 is a flowchart of an example method 300 for performing a read operation in accordance with some embodiments of the present disclosure. Method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, special purpose logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., running or executing on a processing device instructions) or a combination thereof. In some embodiments, method 300 is performed by media management component 113 of FIG. 1 . Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be construed as examples only and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Therefore, not all procedures may be required in every embodiment. Other process flows are possible.

At operation 310, processing logic receives a set of read commands addressing a set of memory pages of the block. In one example, the set of read commands may be sequential read commands for data stored at individual memory pages or sequential memory pages on the same word line. In another example, the set of read commands may be random read commands for data stored at different word lines of the memory device. In some embodiments, each read command in the set of read commands may address a corresponding page. In other embodiments, each read command may address memory at any size granularity. In some embodiments, processing logic may receive a single read command that addresses a set of memory pages of a block. Therefore, processing logic may issue separate read commands for each memory page referenced in a single read command.

At operation 315, processing logic determines a temperature compensation value. In some embodiments, the temperature compensation value may be calculated by subtracting the write temperature value from the current temperature value (eg, the current temperature of memory subsystem 110) (or vice versa). Accordingly, to determine the temperature compensation value, processing logic may determine the current temperature of memory subsystem 110 (using, for example, a temperature measurement device) and determine a write temperature value corresponding to the set of read commands.

To determine the write temperature value, processing logic may retrieve the most recent write temperature value stored in a register, special memory location, cache, etc. Specifically, processing logic may perform read operations on memory pages and retrieve write temperatures from additional temperature data. The processing logic may then store the written temperature value in a register, dedicated memory location, cache, etc. The write temperature value may be updated from additional temperature data from each subsequent read command. This operation of retrieving a written temperature value from the additional temperature data may be in response to performing a read operation (eg, operation 325 discussed below), in response to a data integrity indicator failing to meet threshold criteria (eg, operation 345 discussed below), or in response to Any other operations of method 300 are performed.

In embodiments where the write temperature value is not yet known (e.g., it is not stored in a register, dedicated memory location, cache, etc.), such as when none of the read commands in the set of read commands have been At execution time (so the write temperature value has not yet been retrieved from the additional write data), the processing logic can use the default write temperature value to determine the temperature compensation value. The default write temperature value may be set during programming and/or calibration of the memory subsystem 110, set by a firmware update, set by user input, etc. In some embodiments, the default write temperature value may be stored in a register, dedicated memory location, cache, etc. and updated with actual write temperature data after the data is retrieved during a read operation.

At operation 320, processing logic determines a read offset voltage value using the temperature compensation value. The read offset voltage value may be a voltage offset value applied to the base read voltage value to produce an adjusted read voltage value. The adjusted read voltage value may be applied to a group of memory cells during a read operation. To determine the read offset voltage value associated with the temperature compensation value, processing logic may perform a lookup in the temperature compensation data structure, apply a formula or equation to the temperature compensation value, etc. For example, FIG. 4 is an illustrative example of a temperature compensation data structure 410 in accordance with some embodiments of the present disclosure. Each entry in the data structure 410 includes a temperature compensation value (eg, 5°C, 10°C, etc.) and a read voltage offset (eg, x ₁ V, x ₂ V, etc.) value for each temperature compensation value. In some embodiments, the determined temperature compensation value may be stored in a special register as part of the media management component 113, in a dedicated memory location on a volatile memory device (eg, memory device 140), in a high-speed drive on local memory 119. Cache is medium.

At operation 325, processing logic executes the read command using the adjusted read voltage value. The processing logic may determine the adjusted read voltage value by adding the read voltage offset value to the base read voltage value. In an example, processing logic may use the adjusted read voltage value to instruct the memory device to perform a read operation on the memory page referenced by the read command. In another example, processing logic may send the read voltage offset value to the memory device, which may determine the adjusted read voltage value by adding the voltage offset value to the base read value.

At operation 330, processing logic receives additional read data. For example, the memory device may retrieve additional read data stored at an address referenced by the read command and send the retrieved additional read data to media management component 113 . Additional read data may include host data and the write temperature value of the host data.

At operation 335, processing logic updates the current write temperature data associated with the set of read commands. For example, processing logic may store the write temperature data in specific registers as part of media management component 113, in a dedicated memory location on a volatile memory device (eg, memory device 140), in local memory 119, or the like.

At operation 340, processing logic performs a data integrity check on the retrieved host data. The data integrity check may verify that the data stored at the memory cells of the memory page does not contain any errors or that the number of errors is below a predetermined threshold. During a scan operation, processing logic identifies one or more data integrity metrics, such as a bit error count (BEC) or a raw bit error rate (RBER), which represents the number of bit errors experienced per unit time by the data stored at the data block. number. In some embodiments, during the data integrity check, processing logic reads the original codeword (ie, a fixed number of bits) from the page. The processing logic may apply the codewords to an error correction code (ECC) decoder to produce decoded codewords and compare the decoded codewords to the original codewords. The processing logic may count the number of flipped bits between the decoded codeword and the original codeword, where the ratio of the number of flipped bits to the total number of bits in the codeword represents the RBER.

At operation 345, processing logic determines whether the value of the data integrity indicator (eg, BEC value, RBER value, etc.) meets the threshold criterion (eg, meets or exceeds the threshold, is below the threshold, etc.). Threshold criteria may be determined and set during fabrication of memory subsystem 110 or during programming and/or calibration of memory subsystem 110 . In some embodiments, the threshold criterion may reflect whether processing logic can use ECC to correct errors. In an example, processing logic may determine whether the RBER value or BEC value exceeds a threshold.

If the data integrity metric meets the threshold criteria (eg, the BEC or RBER value is above the threshold) (indicating a high error rate associated with the data stored at the block), then the processing logic continues to operation 315, where the processing logic uses the new The current temperature value and the written temperature value from operation 335 determine the new temperature compensation value. The processing logic may then determine a new adjusted read voltage value using the new temperature compensation value and execute the read command using the new adjusted read voltage value.

If the data integrity metric fails to meet the threshold criteria (eg, the BEC or RBER value is below the threshold), then processing logic continues to operation 350, where processing logic selects a next read command from the set of read commands, and then , continuing to operation 325, where the processing logic executes the next read command using the adjusted read voltage value.

Figure 5A is a block diagram illustrating voltage distribution shifting in accordance with some embodiments of the present disclosure. As shown in Figure 5A, voltage distribution 500 illustrates the two levels '0100' and '0101' of a 16-level QLC memory cell storing four data bits. A memory cell may be programmed to store logic data value '0100' corresponding to distribution 501 within a hotter temperature range by applying a sequence of programming pulses to the memory cell until the programming voltage level reaches a range of values within distribution 501 . Because the temperature associated with a memory cell changes into a cooler temperature range over time (e.g., during the time period between the time the memory cell is programmed and the time the memory cell is read), the programming voltage level (or table ((read voltage)) may be affected and the programming voltage level associated with distribution 501 shifted to distribution 503. Because distribution 503 falls within the range of the distribution associated with logical state value '0101' (distribution 505), there is a possibility of a read error. For example, read voltage level 509 may be encoded to correspond to logic state '0101' rather than '0100'.

Figure 5B is a block diagram illustrating voltage distribution shifting in accordance with some embodiments of the present disclosure. As shown in FIG. 5B , the voltage distribution 530 of two levels '0100' and '0011' of a 16-level QLC memory cell storing four data bits is illustrated. The memory cell may be programmed to store logic data value '0100' corresponding to distribution 531 in a cooler temperature range by applying a sequence of programming pulses to the memory cell until the programming voltage level reaches a range of values within distribution 531 . Because the temperature associated with a memory cell changes into a hotter temperature range over time (e.g., during the time period between the time the memory cell is programmed and the time the memory cell is read), the programming voltage level (or table ((read voltage)) may be affected and the programming voltage level associated with distribution 531 shifted to distribution 533. Because distribution 533 falls within the range of the distribution associated with logical state value '0011' (distribution 535), there is a possibility of a read error. For example, read voltage level 539 may be encoded to correspond to logic state '0011' rather than '0100'.

6 illustrates an example machine of a computer system 600 within which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies discussed herein. In some embodiments, computer system 600 may correspond to a host system (eg, host system 120 of FIG. 1 ) that includes or utilizes a memory subsystem (eg, memory subsystem 110 of FIG. 1 ) or may be used to perform the operations of a controller ( For example, the operating system is executed to perform operations corresponding to media management component 113 of FIG. 1). In alternative embodiments, the machine may be connected (eg, networked) to other machines in a LAN, intranet, extranet, and/or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client in a cloud computing infrastructure or environment terminal machine operation.

The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch or bridge or be capable of (sequentially or otherwise) performing specified Any machine that is a set of instructions for an action to be taken by the machine. Furthermore, while a single machine is illustrated, the term "machine" shall also be taken to include any machine that individually or jointly executes one (or more sets) of instructions to perform any one or more of the methodologies discussed herein. gather.

Example computer system 600 includes a processing device 602, main memory 604 (eg, read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (eg, synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), Static memory 606 (eg, flash memory, static random access memory (SRAM), etc.) and data storage system 618 communicate with each other via bus 630 . Processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or multiple processors implementing a combination of instruction sets. The processing device 602 may also be one or more special purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 to communicate over network 620.

Data storage system 618 may include machine-readable storage media 624 (also referred to as computer-readable media) having stored thereon one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. Instructions 626 may also reside fully or at least partially within main memory 604 and/or within processing device 602 during their execution by computer system 600, which also constitute machine-readable storage media. Machine-readable storage media 624, data storage system 618, and/or main memory 604 may correspond to memory subsystem 110 of FIG. 1 .

In one embodiment, instructions 626 include instructions to implement functionality corresponding to media management component 113 of FIG. 1 . Although machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be understood to include a single medium or multiple media that stores one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Accordingly, the term "machine-readable storage medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to other skilled in the art. Algorithms are herein and generally conceived as a self-consistent sequence of operations that lead to a desired result. Operations are operations that require physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient, sometimes primarily for reasons of convention, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

However, it should be remembered that all these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulates or transforms data represented as physical (electronic) quantities within a computer system's registers and memory, similarly represented as a computer system's memory or registers or other This type of information stores other data on physical quantities within the system.

The present disclosure also relates to apparatus for performing the operations herein. Such a device may be specially constructed for the intended purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program can be stored in a computer-readable storage medium, such as (but not limited to) any type of disk, including floppy disks, optical disks, CD-ROM and magneto-optical disks, read-only memory (ROM), random access memory (RAM) , EPROM, EEPROM, magnetic or optical card or any type of media suitable for storing electronic instructions, each coupled to the computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structure of a variety of these systems will appear as set forth in the description below. Additionally, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure described herein.

The disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that may be used to program a computer system (or other electronic device) to perform processes in accordance with the disclosure. Machine-readable media includes any mechanism for storing information in a form readable by a machine, such as a computer. By way of example, machine-readable (e.g., computer-readable) media includes machine (e.g., computer)-readable storage media, such as read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical Storage media, flash memory devices, etc.

In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be understood that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims (20)

1. A system, comprising:

a memory device; and

A processing device operably coupled to the memory device, the processing device to perform operations comprising:

performing a first read operation on the memory device to retrieve first data;

determining, from the first data, second data indicative of a write temperature associated with the first data, wherein the write temperature is indicative of a temperature measured during a write operation;

determining a read voltage value based on the second data; and

A second read operation is performed on the memory device using the read voltage value to obtain the first data.

2. The system of claim 1, wherein the first data comprises host data and a write temperature.

3. The system of claim 1, wherein the processing device is to perform further operations comprising:

Receiving a write command including host data;

determining an operating temperature value of the memory device; and

The host data and a value reflecting the operating temperature are programmed to the memory device.

4. The system of claim 1, wherein the processing device is to perform further operations comprising:

determining a data integrity index value associated with the first data; and

In response to determining that the data integrity index value meets a threshold criterion, the read voltage value is determined based on the second data.

5. The system of claim 4, wherein the data integrity index value reflects at least one of: bit error count BEC or original bit error rate RBER.

6. The system of claim 4, wherein the threshold criteria indicates whether the processing device is capable of correcting errors using an error correction code, and wherein the data integrity index value satisfies the threshold criteria if the data integrity value is greater than a threshold.

7. The system of claim 1, wherein the processing device is to perform further operations comprising:

in response to determining that the first data obtained from the second read operation passes a data integrity check, performing a third read operation using the read voltage value to obtain third data.

8. The system of claim 1, wherein determining the read voltage value comprises:

determining a temperature compensation value based on the second data and a current temperature value;

determining a read offset voltage value based on the temperature compensation value; and

The read offset voltage value is applied to a base read voltage value.

9. The system of claim 8, wherein determining the read offset voltage value comprises at least one of performing a lookup in a data structure or applying a formula to the temperature compensation value.

10. The system of claim 1, wherein the second data is stored on at least one of a designated register, a particular memory location on a volatile memory device, or a local memory of a memory subsystem controller.

11. A method, comprising:

receiving, by a processor, first data obtained from a memory page of a memory device, wherein the first data comprises host data and write temperature data, wherein the memory page is referenced by a first read command of a set of read commands;

determining a read voltage value based on the write temperature data;

the memory device is instructed to perform a read operation on a second memory page referenced by a second read command of the set of read commands by applying the read voltage value to the second memory page.

12. The method as recited in claim 11, further comprising:

receiving a write command including the host data;

determining an operating temperature value of the memory device; and

The host data and a value reflecting the operating temperature are programmed to the memory device.

13. The method as recited in claim 11, further comprising:

in response to determining that the data integrity index value meets a threshold criterion, a new read voltage value is determined based on new write temperature data obtained from the second memory page.

14. The method of claim 11, wherein determining the read voltage value comprises:

determining a temperature compensation value based on the written temperature data and a current temperature value;

determining a read offset voltage value based on the temperature compensation value; and

The read offset voltage value is applied to a base read voltage value.

15. The method of claim 14, wherein determining the read offset voltage value comprises at least one of performing a lookup in a data structure or applying a formula to the temperature compensation value.

16. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device operably coupled to a memory, perform operations comprising:

Performing a first read operation on the memory device to retrieve first data;

determining, from the first data, second data indicative of a write temperature associated with the first data; and

Determining a read voltage value based on the second data;

a second read operation is performed on the memory device using the read voltage value to obtain the first data.

17. The non-transitory computer-readable storage medium of claim 16, wherein the processing device is to perform further operations comprising:

receiving a write command including host data;

determining an operating temperature value of the memory device; and

The host data and a value reflecting the operating temperature are programmed to the memory device.

18. The non-transitory computer-readable storage medium of claim 16, wherein the processing device is to perform further operations comprising:

determining a data integrity index value associated with the first data; and

In response to determining that the data integrity index value meets a threshold criterion, the read voltage value is determined based on the second data.

19. The non-transitory computer-readable storage medium of claim 16, wherein the processing device is to perform further operations comprising:

In response to determining that the third data obtained from the second read operation passes a data integrity check, performing a third read operation using the read voltage value to obtain third data.

20. The non-transitory computer-readable storage medium of claim 16, wherein determining the read voltage value comprises:

determining a temperature compensation value based on the second data and a current temperature value;

determining a read offset voltage value based on the temperature compensation value; and

The read offset voltage value is applied to a base read voltage value.