CN117112246B

CN117112246B - Control device of spin lock

Info

Publication number: CN117112246B
Application number: CN202311384217.2A
Authority: CN
Inventors: 崔子浩; 石鹏; 马林; 刘奇浩; 颜港; 苏丹丹; 杨茂辉
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2023-10-24
Filing date: 2023-10-24
Publication date: 2024-02-09
Anticipated expiration: 2043-10-24
Also published as: CN117112246A

Abstract

The embodiment of the application provides a control device of spin lock, wherein, the device includes: a target spin lock, a lock acquisition status circuit, and a lock control circuit, wherein an input of the target spin lock is configured to be coupled to the plurality of processors; the output end of the lock acquisition state circuit is connected with the first input end of the lock control circuit, and the input end of the lock acquisition state circuit is connected with the first output end of the target spin lock; the second input end of the lock control circuit is connected with the second output end of the target spin lock, and the output end of the lock control circuit is connected with the third input end of the target spin lock.

Description

Control device of spin lock

Technical Field

The embodiment of the application relates to the field of computers, in particular to a control device of a spin lock.

Background

As processors continue to advance and evolve, the number of cores in a processor continues to increase, and multi-core processors continue to become a necessary condition for a SOC (System on Chip). Compared with the traditional single-core single-thread, the influence of changing the data of the access area is more needed to be considered in the multi-core processing system, and the consistency of the data in the multi-thread running state is ensured. It is therefore particularly important to improve the mechanism in the concurrent processing of a multi-core processor. Because of the limited nature of certain resources in a multiprocessor environment, threads are sometimes required to access data mutually exclusively, and the concept of locks is required to be introduced at this time, only threads that acquire locks can access critical resources. Spin lock (spinlock) one of the lock mechanisms proposed to achieve protection of shared resources can guarantee that at most one keeper of the shared resource is available at any time, i.e. at most one core can be allowed to acquire a specific lock at any time. If a specific spin lock is acquired by a specific core at a certain moment, other threads which do not acquire the spin lock always wait for judging whether a spin lock holder releases the spin lock, which is essentially a busy-wait mechanism plug, so that the system overhead caused by thread switching can be avoided, and compared with a mutual exclusion lock, the conversion between spin locks is faster, and the application range is wider.

In the related art, the implementation scheme of the spin lock is often controlled by software or by a hardware circuit, wherein the former needs to designate a type of area as a storage area for storing the lock state, and the method has the defects of higher complexity, slower operation processing speed and poor safety; the latter is physically implemented by means of actual circuitry, which often requires a large number of registers, which tends to cause redundancy in system performance. In addition, the hardware locks commonly seen at present are often limited to multi-core competing locks, so that the control efficiency of the spin lock is low.

Aiming at the technical problem of lower control efficiency of the spin lock in the related art, no effective solution has been proposed yet.

Disclosure of Invention

The embodiment of the application provides a control device of a spin lock, which at least solves the problem of lower control efficiency of the spin lock in the related technology.

According to one embodiment of the present application, there is provided a control device of a spin lock, including a target spin lock, a lock acquisition state circuit, and a lock control circuit, wherein an input of the target spin lock is configured to be connected to a plurality of processors; the output end of the lock acquisition state circuit is connected with the first input end of the lock control circuit, and the input end of the lock acquisition state circuit is connected with the first output end of the target spin lock; the second input end of the lock control circuit is connected with the second output end of the target spin lock, and the output end of the lock control circuit is connected with the third input end of the target spin lock; the lock acquisition state circuit is configured to acquire target state information of the target spin lock in response to a first allocation request sent by a first processor of the plurality of processors, and output the target state information to the lock control circuit, in a case where the target spin lock acquires the first allocation request, the target spin lock corresponding to a target memory, the first allocation request requesting allocation of the target spin lock to the first processor, the first processor to which the target spin lock is allocated being configured to allow operation of data stored in the target memory; the lock control circuit is configured to, upon receiving the target state information and indicating that the target spin lock is not allocated to a processor, allocate the target spin lock to a first processor of the plurality of processors and output a first allocation result to the first processor through the target spin lock, wherein the first allocation result is used to indicate the first processor to which the target spin lock is allocated.

In one exemplary embodiment, the lock control circuit is further configured to, upon receipt of the target state information, and the target state information indicating that the target spin lock has been assigned to a second processor of the plurality of processors, keep assigning the target spin lock to the second processor and refuse to assign the target spin lock to the first processor.

In an exemplary embodiment, the lock control circuit is further configured to determine whether the second processor is identical to the first processor, resulting in a target determination result, in a case where the target state information is received and the target state information indicates that the target spin lock has been allocated to the second processor; and in the case that the target determination result indicates that the second processor is different from the first processor, sending a second allocation result corresponding to the target determination result to the first processor through the target spin lock, wherein the second allocation result is used for indicating that the target spin lock is allocated to the second processor.

In one exemplary embodiment, the lock control circuit includes a first lock control circuit and a second lock control circuit, wherein one input of the first lock control circuit is connected as a first input of the lock control circuit to the output of the lock acquisition state circuit, the output of the first lock control circuit is connected to one input of the second lock control circuit, the other input of the second lock control circuit is connected as the second input of the lock control circuit to the second output, and the output of the second lock control circuit is connected as an output of the lock control circuit to a third input of the target spin lock; wherein the first lock control circuit is arranged to output an identification of a second processor to the second lock control circuit if the target state information indicates that the target spin lock has been allocated to the second processor; the second lock control circuit is configured to acquire the identification of the first processor if the identification of the second processor is received; outputting a first level signal under the condition that a preset first matching condition is met among a value corresponding to the identifier of the second processor, a value corresponding to the identifier of the first processor and a preset first reference value, wherein the first level signal is used for indicating that the second processor is different from the first processor; and outputting a second level signal under the condition that a preset first matching condition is not met between the value corresponding to the identifier of the second processor, the value corresponding to the identifier of the first processor and a preset first reference value, wherein the second level signal is used for indicating that the second processor is identical to the first processor, and the amplitude of the first level signal is higher than that of the second level signal.

In an exemplary embodiment, the second lock control circuit comprises a first equality module, wherein an output of the first equality module is connected to the third input of the target spin lock, one input of the first equality module is connected as the second input of the lock control circuit to the second output of the target spin lock, wherein the first equality module is arranged to obtain an identification of the first processor from a first bus address output from the second output of the target spin lock, wherein the first allocation request is an allocation request initiated by the first processor to the target spin lock via the first bus address.

In an exemplary embodiment, the second lock control circuit further comprises a first selector module, wherein one input of the first selector module is connected to the output of the first lock control circuit, the output of the first selector module is connected to the third input of the target spin lock, and the other input of the first selector module is connected to the output of the first equivalence module; the first equalization module is further configured to output the second level signal and output the second level signal to the first selector module when a preset first matching condition is not satisfied between a value corresponding to the identifier of the second processor, a value corresponding to the identifier of the first processor, and a preset first reference value; the first selector module is arranged to, upon receipt of the second level signal, output a third allocation result carrying a second reference value indicating that the processor to which the target spin lock has been allocated is the first processor, and to send the third allocation result to the first processor via the target spin lock.

In an exemplary embodiment, the first selector module is further configured to send, to the first processor, the first allocation result carrying a first sum value through the target spin lock, where the target state information indicates that the target spin lock is not allocated to a processor and the target spin lock is allocated to the first processor, and the first sum value is equal to a sum value of a value corresponding to an identifier of the first processor and a preset third reference value.

In one exemplary embodiment, the first lock control circuit is further configured to obtain a set of level signals corresponding to the target spin lock, wherein one level signal of the set of level signals is used to indicate whether the target spin lock is allocated to one of the plurality of processors; the target state information of the target spin lock is determined from the set of level signals.

In an exemplary embodiment, the first lock control circuit includes N selector modules, a first selector module, and a second selector module, wherein one input of the first selector module is connected as the first input to the output of the lock acquisition status circuit, and an output of the second selector module is connected to the input of the second lock control circuit; the output end of the last selector module in the N selector modules is connected with the other input end of the first selector module, the output end of the j selector module in the N selector modules is connected with one input end of the j+1th selector module, one input end of the j selector module is connected with the output end of the j-1th selector module, the other input end of the j selector module is connected with the first output end of the target spin lock, the input end of the first selector module in the N selector modules is connected with the first output end of the target spin lock, the selector modules comprise the N selector modules, N is a positive integer greater than or equal to 1, and j is a positive integer greater than or equal to 2 and less than or equal to N; the first lock control circuit is configured to determine the target state information of the target spin lock from N level signals output by the target spin lock by performing the steps of: determining that the target state information indicates that the target spin lock is allocated to a second processor when the amplitude of the ith level signal in the N level signals is a first amplitude and the amplitudes of all the N level signals except the ith level signal are second amplitudes, wherein the second processor is a processor corresponding to the ith level signal, the first amplitude is greater than the second amplitude, and i is a positive integer greater than or equal to 1 and less than or equal to N; and determining that the target state information indicates that the target spin lock is not allocated to the processor when the magnitudes of the N level signals are all the second magnitudes.

In an exemplary embodiment, the apparatus further comprises a lock release state circuit, wherein an input of the lock release state circuit is connected to a third output of the target spin lock, an output of the lock release state circuit is connected to a further input of the lock control circuit, the further input of the lock control circuit being a further input of a second selector module in the first lock control circuit; the lock release state circuit is configured to release the target spin lock allocated to the first processor in response to a target release request that requests release of the target spin lock allocated to the first processor, when the target spin lock is allocated to the first processor and a target release request initiated by the first processor to the target spin lock is acquired, wherein the first processor that released the target spin lock is configured to prohibit operation on data in the target memory.

According to still another embodiment of the present application, there is also provided a control method of a spin lock, including: acquiring a first allocation request initiated by a first processor to a target spin lock corresponding to a target memory, wherein the first allocation request is used for requesting to allocate the target spin lock to the first processor, and the first processor allocated with the target spin lock is set to allow operation on data stored in the target memory; obtaining target state information of the target spin lock in response to the first allocation request, wherein the target state information indicates whether the target spin lock has been allocated to a processor; and in the case that the target state information indicates that the target spin lock is not allocated to a processor, allocating the target spin lock to the first processor, and sending a first allocation result to the first processor, wherein the first allocation result is used for indicating the first processor to which the target spin lock is allocated.

In one exemplary embodiment, after the acquiring the target state information of the target spin lock, the method further comprises: in the event that the target state information indicates that the target spin lock has been allocated to a second processor, the allocation of the target spin lock to the second processor is maintained and the allocation of the target spin lock to the first processor is denied.

In one exemplary embodiment, in the event that the target state information indicates that the target spin lock has been assigned to a second processor, the method further comprises: determining whether the second processor is the same as the first processor or not, and obtaining a target determination result; and in the case that the target determination result indicates that the second processor is different from the first processor, sending a second allocation result corresponding to the target determination result to the first processor, wherein the second allocation result is used for indicating that the target spin lock is allocated to the second processor.

In one exemplary embodiment, the method further comprises: and if the target determination result indicates that the second processor is the same as the first processor, sending a third allocation result corresponding to the target determination result to the first processor, wherein the third allocation result is used for indicating that the target spin lock is allocated to the first processor.

In one exemplary embodiment, the sending, to the first processor, a second allocation result corresponding to the target determination result if the target determination result indicates that the second processor is different from the first processor, includes: acquiring an identifier of the second processor from the target state information, wherein the target state information carries the identifier of the second processor to which the target spin lock is allocated; carrying the identification of the second processor on the second allocation result; and sending the second allocation result to the first processor.

In an exemplary embodiment, the determining whether the second processor is the same as the first processor, to obtain the target determination result, includes: acquiring an identification of the first processor; determining that the second processor is different from the first processor under the condition that a preset first matching condition is met between a value corresponding to the identifier of the second processor, a value corresponding to the identifier of the first processor and a preset first reference value; and determining that the second processor is identical to the first processor under the condition that a preset first matching condition is not met between the value corresponding to the identifier of the second processor, the value corresponding to the identifier of the first processor and a preset first reference value.

In an exemplary embodiment, the obtaining the identification of the first processor includes: the identification of the first processor is obtained from a first bus address of the target spin lock, wherein the first allocation request is an allocation request initiated by the first processor to the target spin lock through the first bus address.

In one exemplary embodiment, the sending the first allocation result to the first processor includes: and sending the first distribution result carrying a first sum value to the first processor, wherein the first sum value is equal to the sum value of the value corresponding to the identifier of the first processor and a preset third reference value.

In one exemplary embodiment, the obtaining the target state information of the target spin lock includes: obtaining a set of allocation states corresponding to the target spin lock, wherein one allocation state in the set of allocation states is used for indicating whether the target spin lock is allocated to one processor in the set of processors; and determining the target state information of the target spin lock according to the group of allocation states.

In one exemplary embodiment, the determining the target state information of the target spin lock from the set of allocation states comprises: determining the target state information of the target spin lock according to N allocation states, wherein the set of allocation states includes the N allocation states, one allocation state of the N allocation states being used to indicate whether the target spin lock is allocated to one processor of N processors, the set of processors including the N processors, N being a positive integer greater than or equal to 1: determining that the target state information indicates that the target spin lock is allocated to a second processor when an ith allocation state is a high level state and allocation states other than the ith allocation state are low level states in the N allocation states, wherein the second processor is a processor corresponding to the ith allocation state, and i is a positive integer greater than or equal to 1 and less than or equal to N; and determining that the target state information indicates that the target spin lock is not allocated to a processor when all of the N allocation states are the low level states.

In one exemplary embodiment, the method further comprises: obtaining a target release request initiated by the first processor to the target spin lock under the condition that the target spin lock is distributed to the first processor, wherein the target release request is used for requesting to release the target spin lock distributed to the first processor; and releasing the target spin lock allocated to the first processor in response to the target release request, wherein the first processor releasing the target spin lock is configured to disable operation on data in the target memory.

In one exemplary embodiment, the releasing the target spin lock allocated to the first processor includes: and writing a preset fourth reference value into a target storage address corresponding to the target spin lock, wherein the target spin lock written with the fourth reference value into the target storage address is set to be not allocated to any processor.

According to a further embodiment of the present application, there is also provided a computer readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

According to a further embodiment of the present application, there is also provided an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

According to the embodiment of the application, under the condition that the first processor wants to operate the data stored in the memory, the first processor needs to request to acquire the spin lock corresponding to the memory, under the condition that the state information of the spin lock can be acquired through the lock acquisition state circuit and transmitted to the lock control circuit, the lock control circuit can indicate that the spin lock is not allocated to the processor under the condition that the state information is received and the state information is used for indicating that the spin lock is idle, under the condition that the lock control circuit allocates the spin lock to the first processor and returns an allocation result to the first processor, wherein the allocation result is used for indicating the first processor to which the spin lock is allocated, by the mode, the state information of the spin lock transmitted by the lock acquisition state circuit is acquired, and the lock control circuit automatically determines whether the spin lock is allocated to the processor requesting to allocate the spin lock, so that the problem that the control efficiency of the spin lock is low can be solved, and the effect of improving the control efficiency of the spin lock is achieved.

Drawings

FIG. 1 is a flow chart of a method of controlling a spin lock according to an embodiment of the present application;

FIG. 2 is a schematic diagram of input and output signals of an alternative spin lock according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a spin lock assigned to core number 00 according to an embodiment of the present application;

FIG. 4 is a schematic diagram of checking occupancy and output values of a spin lock in an alternative quad-core system according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a circuit of a lock acquired state in an alternative lock state circuit configuration according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a circuit of a lock released state in an alternative lock state circuit configuration according to an embodiment of the present application;

FIG. 7 is a schematic diagram of acquisition and release of spin locks in an alternative multi-core concurrent processing application scenario according to an embodiment of the present application;

FIG. 8 is a schematic diagram of acquisition and release of spin locks in an alternative single core multi-threaded application scenario according to an embodiment of the present application;

FIG. 9 is a decision circuit of an alternative single core multithreading mechanism in accordance with an embodiment of the present application;

FIG. 10 is a block diagram of a control device of a spin lock according to an embodiment of the present application;

FIG. 11 is a schematic illustration of an alternative spin lock control apparatus according to an embodiment of the present application;

FIG. 12 is a schematic diagram of an alternative lock control circuit according to an embodiment of the present application;

FIG. 13 is a schematic diagram I of an alternative second lock control circuit according to an embodiment of the present application;

FIG. 14 is a schematic diagram II of an alternative second lock control circuit according to an embodiment of the present application;

FIG. 15 is a schematic diagram of an alternative first lock control circuit according to an embodiment of the present application;

fig. 16 is a schematic diagram ii of an alternative spin lock control device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.

It should be noted that the terms "first," "second," and the like in the description and the claims of the embodiments of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

First, some proper nouns appearing in the embodiments of the present application are explained as follows:

SPINLOCK: spin-lock is a lock introduced to prevent multiprocessor concurrency, and when one thread tries to acquire a lock, if the lock is already occupied by another thread, the thread cannot acquire the lock, and the thread waits for a period of time to try to acquire again. This mechanism of waiting for lock release, using cyclic locking, is known as spin locking.

Thread: in one process, there may be multiple execution links at the same time, these execution links are called threads, which are the minimum units of scheduling and allocation for the CPU (Central Processing Unit ).

Verilog HDL (Verilog Hardware Description Language, hardware description language) is a language that describes the structure and behavior of digital system hardware in text form, with which logic diagrams, logic expressions, and logic functions performed by a digital logic system can be represented.

Verdi: a hardware simulation tool.

In this embodiment, a control device for a spin lock is provided, including a target spin lock, a lock acquisition state circuit, and a lock control circuit, where an input terminal of the target spin lock is configured to be connected to a plurality of processors; the output end of the lock acquisition state circuit is connected with the first input end of the lock control circuit, and the input end of the lock acquisition state circuit is connected with the first output end of the target spin lock; the second input end of the lock control circuit is connected with the second output end of the target spin lock, and the output end of the lock control circuit is connected with the third input end of the target spin lock; the lock acquisition state circuit is configured to acquire target state information of the target spin lock in response to a first allocation request sent by a first processor of the plurality of processors, and output the target state information to the lock control circuit, in a case where the target spin lock acquires the first allocation request, the target spin lock corresponding to a target memory, the first allocation request requesting allocation of the target spin lock to the first processor, the first processor to which the target spin lock is allocated being configured to allow operation of data stored in the target memory; the lock control circuit is configured to, upon receiving the target state information and indicating that the target spin lock is not allocated to a processor, allocate the target spin lock to a first processor of the plurality of processors and output a first allocation result to the first processor through the target spin lock, wherein the first allocation result is used to indicate the first processor to which the target spin lock is allocated.

Alternatively, in the present embodiment, the target spin lock may be, but is not limited to being, connected to a plurality of processors, it being understood that the target spin lock is configured to allow receiving allocation requests of the plurality of processors, fig. 11 is a schematic diagram of an alternative spin lock control apparatus according to an embodiment of the present application, as shown in fig. 11, including a target spin lock 1102, a lock acquisition state circuit 1104, and a lock control circuit 1106, wherein an input of the target spin lock 1102 is configured to be connected to the plurality of processors (e.g., processor 1, processor 2, processor 3, etc.); an output of the lock acquisition state circuit 1104 is connected to a first input of the lock control circuit 1106, and an input of the lock acquisition state circuit 1104 is connected to a first output of the target spin lock 1102; a second input of the lock control circuit 1106 is coupled to a second output of the target spin lock 1102 and an output of the lock control circuit 1106 is coupled to a third input of the target spin lock 1102.

Alternatively, in the present embodiment, in the case where the target state information indicates that the target spin lock has been allocated to the second processor among the plurality of processors, it is understood that the target spin lock has been allocated to the second processor, and in such a case, the lock control circuit keeps allocating the target spin lock to the second processor and refuses to allocate the target spin lock to the first processor, in such a manner that it is achieved that only the target spin lock is allocated to one processor at the same time, improving the allocation rationality of the spin lock.

Alternatively, in the present embodiment, in the case where the target state information indicates that the target spin lock has been allocated to the second processor, it may be determined, but is not limited to, by the lock control circuit, whether the second processor is the same processor as the first processor, and it is understood that the second processor to which the target spin lock is allocated may be the same processor as the first processor or a different processor.

Alternatively, in this embodiment, fig. 12 is a schematic diagram of an alternative lock control circuit according to an embodiment of the present application, as shown in fig. 12, the lock control circuit 1106 includes a first lock control circuit 1106-1 and a second lock control circuit 1106-2, one input of the first lock control circuit 1106-1 is connected to an output of the lock acquisition state circuit 1104 as a first input of the lock control circuit 1106, an output of the first lock control circuit 1106-1 is connected to one input of the second lock control circuit 1106-2, another input of the second lock control circuit 1106-2 is connected to a second output of the target spin lock 1102 as a second input of the lock control circuit 1106, and an output of the second lock control circuit 1106-2 is connected to a third input of the target spin lock 1102 as an output of the lock control circuit 1106.

Optionally, in this embodiment, fig. 13 is a schematic diagram of an optional second lock control circuit according to an embodiment of the present application, as shown in fig. 13, where the second lock control circuit 1106-2 includes a first equivalent module, an output terminal of the first equivalent module is connected to a third input terminal of the target spin lock 1102, and an input terminal of the first equivalent module is connected as a second input terminal of the lock control circuit to a second output terminal of the target spin lock 1102, where the first equivalent module is configured to obtain an identifier of the first processor from a first bus address output from the second output terminal of the target spin lock 1102, and where the first allocation request is an allocation request initiated by the first processor to the target spin lock 1102 through the first bus address.

Optionally, in this embodiment, fig. 14 is a schematic diagram two of an optional second lock control circuit according to an embodiment of the present application, as shown in fig. 14, where the second lock control circuit 1106-2 further includes a first selector module, where one input of the first selector module is connected to the output of the first lock control circuit 1106-1, the output of the first selector module is connected to the third input of the target spin lock 1102, and the other input of the first selector module is connected to the output of the first equivalent module.

Optionally, in this embodiment, in the case of allocating the target spin lock to the first processor, the first allocation result carrying the first sum value is sent to the first processor through the target spin lock, and it is understood that the allocation result carrying the first sum value is returned to the first processor, where the first sum value may be, but is not limited to, equal to the sum value of the decimal, binary, or hexadecimal value of the identifier of the first processor and the preset third reference value.

Alternatively, in this embodiment, the first lock control circuit may, but is not limited to, obtain a set of level signals of the target spin lock, and it is understood that each of the plurality of processors has a one-to-one correspondence of level signals, and may, but is not limited to, determine the state information of the target spin lock according to the set of level signals.

Optionally, in this embodiment, the first amplitude is greater than the second amplitude, for example, the level signal having the first amplitude is a high level signal, and the level signal having the second amplitude is a low level signal. Only one of the N level signals can be present at a first magnitude, it being understood that the target spin lock can only be assigned to one of the plurality of processors.

Alternatively, in the present embodiment, fig. 15 is a schematic diagram of an optional first lock control circuit according to the embodiment of the present application, as shown in fig. 15, which may be but not limited to being explained and illustrated by taking the example that the first lock control circuit includes 3 selector modules (for example, selector module 1, selector module 2, and selector module 3), the first lock control circuit 1106-1 includes selector module 1, selector module 2, and selector module 3, the first selector module, and the second selector module, where one input of the first selector module is connected as a first input to the output of the lock acquisition status circuit 1104, and the output of the second selector module is connected to the input of the second lock control circuit 1106-2; the output of the selector module 3 is connected to the other input of the first selector module, the output of the selector module 2 is connected to one input of the selector module 3, one input of the selector module 2 is connected to the output of the selector module 1, the other input of the selector module is connected to the first output of the target spin lock 1102, and the input of the selector module 1 is connected to the first output of the target spin lock 1102.

Optionally, in this embodiment, fig. 16 is a schematic diagram two of an optional spin lock control apparatus according to an embodiment of the present application, as shown in fig. 16, a target spin lock 1102, a lock acquisition state circuit 1104, a lock control circuit 1106, and a lock release state circuit 1108, where an input terminal of the target spin lock 1102 is configured to be connected to a plurality of processors (e.g., processor 1, processor 2, processor 3, etc.); an output of the lock acquisition state circuit 1104 is connected to a first input of the lock control circuit 1106, and an input of the lock acquisition state circuit 1104 is connected to a first output of the target spin lock 1102; a second input of the lock control circuit 1106 is connected to a second output of the target spin lock 1102, and an output of the lock control circuit 1106 is connected to a third input of the target spin lock 1102; an input of the lock release state circuit 1108 is coupled to a third output of the target spin lock 1102 and an output of the lock release state circuit 108 is coupled to a further input of the lock control circuit 1106, the further input of the lock control circuit being the other input of the second selector module in the first lock control circuit 1106-1. It will be appreciated that the other input of the second selector module is connected to the output of the lock release state circuit 108.

In this embodiment, a control method of a spin lock is provided, fig. 1 is a flowchart of a control method of a spin lock according to an embodiment of the present application, and as shown in fig. 1, the flowchart includes the following steps:

step S202, a first allocation request initiated by a first processor to a target spin lock corresponding to a target memory is acquired, wherein the first allocation request is used for requesting to allocate the target spin lock to the first processor, and the first processor allocated with the target spin lock is set to allow operation on data stored in the target memory;

step S204, responding to the first allocation request, and acquiring target state information of the target spin lock, wherein the target state information indicates whether the target spin lock is allocated to a processor or not;

step S206, in a case where the target state information indicates that the target spin lock is not allocated to a processor, allocating the target spin lock to the first processor, and sending a first allocation result to the first processor, where the first allocation result is used to indicate the first processor to which the target spin lock is allocated.

Through the steps, when the first processor wants to operate on the data stored in the memory, the first processor needs to request to acquire the spin lock corresponding to the memory, in this case, the lock acquiring state circuit is used for acquiring the state information of the spin lock and transmitting the state information to the lock control circuit, and the lock control circuit can indicate that the spin lock is not allocated to the processor when receiving the state information and the state information is used for indicating that the spin lock is idle, in this case, the lock control circuit allocates the spin lock to the first processor and returns an allocation result to the first processor, wherein the allocation result is used for indicating the first processor to which the spin lock is allocated.

The main execution body of the above steps may be a server, a terminal, or the like, but is not limited thereto.

In the technical solution provided in step S202, in order to ensure consistency of data stored in the target memory accessed by different processors, the processor may, but is not limited to, need to acquire the target spin lock corresponding to the target memory before the processor operates on the data stored in the target memory. The target spin lock can only be allocated to one processor at a time, and it is understood that only one processor can operate on data stored in the target memory at a time.

The spin lock operates on the principle that when a particular core (or processor) wants to access a shared resource protected by the spin lock, the lock corresponding to the shared resource must be obtained first, and likewise, after the shared resource is accessed, the spin lock must be released. During the acquisition of a spin lock, if the spin lock is not held by any of the cores, this will immediately be acquired by the execution units of the cores that are ready to acquire the spin lock. If the spin lock is already occupied by another core, the operation of acquiring the spin lock will continue to spin until the spin lock is released by the current holder.

Alternatively, in an embodiment, the target memory may be, but is not limited to being, corresponding to one or more spin locks, for example, the data stored in the target memory may be, but is not limited to being, divided into a plurality of sub-data, one spin lock corresponding to one or more sub-data, it being understood that the target memory may be, but is not limited to being, corresponding to a plurality of spin locks, in which case the target spin lock is one of the one or more spin locks, and the processor to which the target spin lock is allocated is configured to allow access to a portion of the data stored in the target memory, wherein the portion of the data is the sub-data corresponding to the target spin lock of the plurality of sub-data.

Optionally, in an embodiment, the target memory may also, but is not limited to, correspond to one target spin lock, in which case the processor assigned the target spin lock is configured to allow access to all data stored in the target memory.

Alternatively, in an embodiment, the processor may include, but is not limited to, a CPU, MCU (Microcontroller Unit, micro control unit), or the like.

In the solution provided in the above step S204, in the case where the target state information indicates that the target spin lock is not allocated to the processor, it may indicate that the target spin lock is idle, and in such a case, the target spin lock is allowed to be allocated to the first processor.

Alternatively, in this embodiment, in the case where the target state information indicates that the target spin lock has been allocated to the processor, it may be indicated that the target spin lock is not allowed to be allocated to the first processor. By the mode, the spin lock is distributed to one processor at the same time, so that the data in the memory is only allowed to be operated by one processor at the same time, and the stability of the data in the memory is improved.

Optionally, in this embodiment, the spin lock circuit may determine the state information of the spin lock by, but not limited to, an output signal, and fig. 2 is a schematic diagram of input and output signals of an optional spin lock according to an embodiment of the present application, and as shown in fig. 2, the spin lock circuit mainly relies on the output signal to determine a specific mechanism of processing and check the holding condition of the spin lock, where the input signal includes a clock signal CLK, a reset signal rst_n, a read-write enable signal (e.g., a read enable signal RDEN, a write enable signal WREN), written specific data WDATA, and a bus address ADDR, and the output signal is read data RDATA. The bus address includes specific information of the core and specific address information of the lock. The logic unit of the circuit combines specific bus addresses, and each lock corresponding to each core has a unique bus address. In addition, multiple cores may share addresses that store locks. When a lock is held by a core, a normal value or other values are output, and a state information of 'locked' is output in an internal circuit (the state information is only transmitted inside the spin lock, and the state information is taken as a judgment basis of the output value of the read data before the read data finally passes through the spin lock and does not belong to the integral output of the spin lock circuit).

In one exemplary embodiment, after obtaining the target state information of the target spin lock, the method further comprises: in the event that the target state information indicates that the target spin lock has been allocated to a second processor, the allocation of the target spin lock to the second processor is maintained and the allocation of the target spin lock to the first processor is denied.

Alternatively, in this embodiment, in the case where the target state information indicates that the target spin lock has been allocated to the second processor, it may be indicated that the target spin lock is not allowed to be allocated to the first processor, in which case allocation of the target spin lock to the second processor may be, but is not limited to, kept and allocation of the target spin lock to the first processor is denied, in such a manner that it is ensured that allocation of the target spin lock to only one processor at the same time is achieved.

In one exemplary embodiment, in the case where the target state information indicates that the target spin lock has been assigned to the second processor, the method further comprises: determining whether the second processor is the same as the first processor or not, and obtaining a target determination result; and in the case that the target determination result indicates that the second processor is different from the first processor, sending a second allocation result corresponding to the target determination result to the first processor, wherein the second allocation result is used for indicating that the target spin lock is allocated to the second processor.

Alternatively, in this embodiment, the second processor may be a different processor than the first processor, and it is understood that the target spin lock has been assigned to a second processor that is different from the first processor, in which case the second assignment result may be, but is not limited to, sent to the first processor, where the second assignment result is used to indicate that the target spin lock is assigned to the second processor. In this way, it is achieved that the second processor to which the target spin lock is currently allocated is returned to the first processor while maintaining allocation of the target spin lock to the second processor and refusing allocation of the target spin lock to the first processor.

In an exemplary embodiment, the above method further comprises: and if the target determination result indicates that the second processor is the same as the first processor, sending a third allocation result corresponding to the target determination result to the first processor, wherein the third allocation result is used for indicating that the target spin lock is allocated to the first processor.

Alternatively, in this embodiment, the second processor may be the same processor as the first processor, and it is understood that the target spin lock has been assigned to the first processor, in which case if the first processor again requests the assignment of the target spin lock to the first processor, a third assignment result may be sent to the first processor, but is not limited to.

In one exemplary embodiment, the second allocation result corresponding to the target determination result may be transmitted to the first processor in a case where the target determination result indicates that the second processor is different from the first processor, by, but not limited to: acquiring an identifier of the second processor from the target state information, wherein the target state information carries the identifier of the second processor to which the target spin lock is allocated; carrying the identification of the second processor on the second allocation result; and sending the second allocation result to the first processor.

Alternatively, in this embodiment, the processors have identifiers corresponding to each other, and the identifiers of the different processors may be, but not limited to, different, so that it is achieved that the different processors are distinguished by the different identifiers.

Optionally, in this embodiment, the value of the identifier of the second processor carried in the target state information under the target system may be carried in the second allocation result, and the second allocation result is sent to the first processor, where the target system may include, but is not limited to, decimal system, binary system, hexadecimal system, or the like.

In one exemplary embodiment, the determination of whether the second processor is the same as the first processor may be, but is not limited to, performed by: acquiring an identification of the first processor; determining that the second processor is different from the first processor under the condition that a preset first matching condition is met between a value corresponding to the identifier of the second processor, a value corresponding to the identifier of the first processor and a preset first reference value; and determining that the second processor is identical to the first processor under the condition that a preset first matching condition is not met between the value corresponding to the identifier of the second processor, the value corresponding to the identifier of the first processor and a preset first reference value.

Optionally, in this embodiment, the value corresponding to the identifier of the second processor, the value corresponding to the identifier of the first processor, and the preset first reference value may be, but are not limited to, a value under a target system, and the target system may be, but is not limited to, binary, decimal, hexadecimal, and so on.

For example, the target system is decimal, and the value corresponding to the identifier of the second processor, the value corresponding to the identifier of the first processor, and the preset first reference value may be, but not limited to, 2, 1, and 1, respectively.

Optionally, in this embodiment, when a preset first matching condition is satisfied between the value corresponding to the identifier of the second processor and the first reference value corresponding to the sum of the value corresponding to the identifier of the first processor, it may be indicated that the identifier of the first processor and the identifier of the second processor are different, and it may be understood that the first processor and the second processor are different processors, that is, the second processor to which the target spin lock is allocated is different from the second processor to which allocation of the target spin lock to the first processor is requested.

Alternatively, in this embodiment, when the preset first matching condition is not satisfied between the value corresponding to the identifier of the second processor, the value corresponding to the identifier of the first processor, and the preset first reference value, it may be indicated that the identifier of the first processor is identical to the identifier of the second processor, and in this case, it is determined that the second processor and the first processor are identical processors, that is, the second processor to which the target spin lock is allocated is identical to the second processor to which allocation of the target spin lock is requested.

In one exemplary embodiment, the first matching condition includes: the difference between the value corresponding to the identifier of the second processor and the value corresponding to the identifier of the first processor is not equal to the first reference value.

Alternatively, in this embodiment, in the case where the difference between the value corresponding to the identifier of the second processor and the value corresponding to the identifier of the first processor is not equal to the first reference value, it is understood that the second processor is a different processor from the first processor.

Alternatively, in this embodiment, in the case where the difference between the value corresponding to the identifier of the second processor and the value corresponding to the identifier of the first processor is equal to the first reference value, it is understood that the second processor is the same processor as the first processor.

In one exemplary embodiment, the identification of the first processor may be obtained, but is not limited to, by: the identification of the first processor is obtained from a first bus address of the target spin lock, wherein the first allocation request is an allocation request initiated by the first processor to the target spin lock through the first bus address.

Alternatively, in this embodiment, different spin locks may, but are not limited to, correspond to different bus addresses, and it is understood that the same processor initiates an allocation request to different spin locks via different bus addresses, in which case the different bus addresses include the identity of the same processor. For example, processor 1 initiates an allocation request to spin lock 1 via bus address 1 and processor 2 initiates an allocation request to spin lock 2 via bus address 2, where bus address 1 and bus address 2 are different bus addresses, and each of bus address 1 and bus address 2 includes an identification of processor 1.

Alternatively, in this embodiment, the allocation request initiated by the different processors to the target spin lock may, but is not limited to, include an allocation request initiated by a different bus address to the target spin lock, and it is understood that the different processors initiate an allocation request by a different bus address to the target spin lock.

Optionally, in this embodiment, the first bus address may also include, but is not limited to, a target memory address including a target spin lock, and in a case where the processor initiates an allocation request to the target spin lock through the corresponding bus address, the bus addresses corresponding to the different processors may include, but are not limited to, the target memory address including the target spin lock.

For example, processor 1 initiates an allocation request to spin lock 1 via bus address 1 and processor 2 initiates an allocation request to spin lock 1 via bus address 2, where bus address 1 and bus address 2 are different bus addresses, and both bus address 1 and bus address 2 include the memory address of spin lock 1.

It should be noted that, the number of locks and the number of cores may be reflected in the bus address bit width, for example, in the case where the number of cores is 4 and the number of spin locks is 128, if a spin lock is represented by data with 3 bits wide, then the bit width 2 of the core identifier, the address bit width 7 of the spin lock, and the bit width of the spin lock with 3 bits are included in the bus address, and it is understood that the bus address bit width is 12.

In one exemplary embodiment, the identification of the first processor may be obtained from the first bus address of the target spin lock, but is not limited to, by: the identification of the first processor is read from a target bit in the first bus address.

Optionally, in this embodiment, but not limited to, a bit of a preset number of bits in the first bus address may be used as the target bit, for example, the first two bits in the bus address are indicated as which core specifically accesses the address space of the spin lock, and by this way, the lock address of the spin lock and the identifier of the processor are combined with the bus address, so that the processing speed is increased, and the control efficiency of the spin lock is improved.

In one exemplary embodiment, a third allocation result corresponding to the targeting result may be, but is not limited to, sent to the first processor by: and sending the third allocation result carrying a preset second reference value to the first processor, wherein the second reference value is used for indicating that the processor to which the target spin lock is allocated is the first processor.

Alternatively, in this embodiment, in the case where the second processor and the fourth processor are the same processor, the third allocation result carrying the preset second reference value may be sent to the fourth processor, and it may be understood that, in the case where the processor to which the target spin lock is currently requested to be allocated and the processor to which the target spin lock is already allocated are the same, the processor to which the target spin lock is currently requested to be allocated is the third allocation result carrying the preset second reference value.

For example, in the case where a spin lock has been allocated to processor 1, if processor 1 initiates an allocation request to a spin lock again, requesting that the spin lock be allocated to processor 1, an allocation result carrying a preset second reference value may be returned to processor 1 in such a case, but not limited to; in the case that a spin lock has been allocated to processor 2, if processor 2 in turn initiates an allocation request to a spin lock requesting that the spin lock be allocated to processor 2, an allocation result carrying a preset second reference value may be returned to processor 2 in such a case, but not limited to.

Alternatively, in this embodiment, the second reference value may include at least one of a preset number, a preset letter, or a preset character string, for example, the second reference value may be 19a, or the second reference value may be 3' b111, or the like, which is not limited in this application.

In one exemplary embodiment, the target state information of the target spin lock may be obtained, but is not limited to, by: obtaining a set of allocation states corresponding to the target spin lock, wherein one allocation state in the set of allocation states is used for indicating whether the target spin lock is allocated to one processor in the set of processors; and determining the target state information of the target spin lock according to the group of allocation states.

Alternatively, in this embodiment, there may be multiple processors each requesting to acquire the same target spin lock allocation, and it is understood that the allocation status of the target spin lock is different in the case of allocating the target spin lock to different processors.

Alternatively, in the present embodiment, each allocation state in the set of allocation states may be, but is not limited to being represented by at least one of an letter, a number, or a string, and may be, but is not limited to carrying an identification of the processor to which the target spin lock is requested to be allocated.

In one exemplary embodiment, the target state information for the target spin lock may be determined from a set of allocation states, but is not limited to, by: determining the target state information of the target spin lock according to N allocation states, wherein the set of allocation states includes the N allocation states, one allocation state of the N allocation states being used to indicate whether the target spin lock is allocated to one processor of N processors, the set of processors including the N processors, N being a positive integer greater than or equal to 1: determining that the target state information indicates that the target spin lock is allocated to a second processor when an ith allocation state is a high level state and allocation states other than the ith allocation state are low level states in the N allocation states, wherein the second processor is a processor corresponding to the ith allocation state, and i is a positive integer greater than or equal to 1 and less than or equal to N; and determining that the target state information indicates that the target spin lock is not allocated to a processor when all of the N allocation states are the low level states.

Alternatively, in this embodiment, the target spin lock can only be assigned to one processor at a time, and it is understood that for one spin lock, there may be only one of the N assigned states that is a high state.

Alternatively, in this embodiment, in the case where the N allocation states are all low-level states, it may be, but is not limited to, determined that the target spin lock is not allocated to any processor, and it is understood that the target spin lock is not occupied by any processor.

In one exemplary embodiment, the determination of the target state information may be, but is not limited to, that the target spin lock is assigned to the second processor by: acquiring a target sum value between a value corresponding to the initial identifier of the second processor and a preset target reference value, and taking the target sum value as a value corresponding to the identifier of the second processor; and carrying the target and the value in the target state information.

Optionally, in this embodiment, in order to improve the security of the target state information, the identifier of the processor to which the target spin lock is allocated may be, but is not limited to, processed, for example, to obtain a target sum value between a value corresponding to the initial identifier of the second processor and a preset target reference value.

Optionally, in this embodiment, the value corresponding to the initial identifier of the second processor and the preset target reference value may, but are not limited to, all values under a target system, where the target system may, but is not limited to, include decimal system, binary system, hexadecimal system, and so on, and this application is not limited thereto.

For example, the value corresponding to the identifier of the second processor under decimal is 0, in this case, the sum value 1 of 0 and 1 of the target reference value under decimal (the target reference value may be, but is not limited to, 2, 4, etc., which is not limited in this application) may be, but is not limited to, carried in the second allocation result.

In one exemplary embodiment, the target state information may be determined, but is not limited to, by: the processor to which the target spin lock is assigned is set to null in the target state information.

Alternatively, in this embodiment, in a case where the target spin lock is not allocated to the processor, the identifier of the processor to which the target spin lock is allocated may be set to be null in the target state information, or a preset reference identifier may be carried in the target state information, where the reference identifier is used to indicate that the target spin lock is not allocated to the processor.

Alternatively, in this embodiment, the preset reference identifier may include at least one of letters, numbers, and character strings, for example, but not limited to lock_000.

In the solution provided in the above step S206, in the case where the target spin lock has been allocated to the first processor, if there are other processors different from the first processor requesting allocation of the target spin lock to the first processor, in such a case, allocation of the target spin lock to the first processor is kept and allocation of the target spin lock to the processor is refused, and the allocation result returned to the processor is used to indicate the first processor to which the target spin lock has been allocated.

Optionally, in this embodiment, after the target spin lock is allocated to the first processor, the first processor may operate on at least a portion of the data stored in the target memory through the target spin lock, but is not limited to.

For example, the first processor may operate on all data stored in the target memory by, but not limited to, one target spin lock in the case of the target memory, and may operate on part of the data stored in the target memory by, but not limited to, the target spin lock in the case of the target memory corresponding to a plurality of spin locks, wherein the part of the data is the data corresponding to the target spin lock in the target memory.

Alternatively, in the present embodiment, the core basic circuit structure of the spin lock mainly includes a lock state circuit structure and a lock control circuit structure. The lock state circuit structure comprises a lock release state and a lock acquired state, and the lock control circuit structure comprises information of whether the lock is acquired by a specific core or not and locking after the lock is acquired. The circuit module can be subjected to multiple instantiations according to the number of the locks to meet the requirement.

Taking the number of cores as 4 as an example, the cores are numbered 0, 1, 2 and 3 cores, respectively, represented by binary numbers 00, 01, 10 and 11, respectively, for a total of two bits. The first two bit signals in the bus address are thus indicated as specifically which core accesses the address space of the spin lock. The corresponding Verilog (hardware description language) program may be written and converted to a circuit configuration diagram by veridi, but is not limited thereto. The states when the four cores respectively acquire the spin LOCK are defined as lock_001, lock_010, lock_011 and lock_100, respectively, and the states when the spin LOCK is in idle are defined as lock_000. The state of the spin lock is determined by the value of the read data output. Then for a particular spin lock, the five states are mutually exclusive and may only be one of the five states described above, i.e., the spin lock is in an idle state, the spin lock is occupied by a number 00 core, the spin lock is occupied by a number 01 core, the spin lock is occupied by a number 10 core, or the spin lock is occupied by a number 11 core.

Fig. 3 is a schematic diagram of assigning spin LOCKs to core No. 00 according to an embodiment of the present application, as shown in fig. 3, when core No. 00 acquires a spin LOCK through a read operation under the condition that a read enable signal is pulled high, the lock_001 state is at a high level, and the output value of the selector is 3b'001. Then for a particular spin lock, when the output value is 3b'001, this indicates that the spin lock has been occupied by a number 00 core.

Similarly, in the four-core architecture, fig. 4 is a schematic diagram of the occupancy and output values of the check spin lock in an alternative four-core system according to an embodiment of the present application, as shown in fig. 4, since a specific spin lock is only idle and occupied by one core of the four cores in these five states, and these five states are independent of each other. Therefore, when core number 01 occupies the spin LOCK, lock_010 is in a high state, the corresponding selector output value is set to be 3b'010, and the output is transmitted to the low level of the 1-out-of-2 selector for judging that core number 00 occupies the spin LOCK. Since lock_001 is at low level at this time, the final output result is 3b'010. That is, for a particular spin lock, when the read data output is 3b'010, it is indicated that the spin lock is occupied by core number 01; for another example, when core 10 occupies the spin LOCK, lock_011 is set to a high state, the output value of its corresponding selector is set to 3b '011, and this value is transferred to the low level of the selector for determining core 01 occupies the spin LOCK, and since lock_010 is set to low level, this value is transferred to the low level of core 00 occupies the spin LOCK, and since lock_001 is also set to low level, the read data finally outputted is set to 3b'011. It will be appreciated that the direction of transmission of the output value is from left to right.

It will be appreciated that for a particular spin lock, when the output value is 3b'011, this spin lock is indicated to be occupied by core number 10; when the 11 # core occupies the spin LOCK, lock_100 is at a high level, the output value of the corresponding selector is 3b '100, the output is further transmitted to the low level position of the selector for judging that the 10 # core occupies the spin LOCK, the signal state of lock_011 is at a low level, therefore, the transmitted 3b'100 is further transmitted to the low level position of the selector for judging that the 01 # core occupies the spin LOCK, the signal of lock_010 is also at a low level according to the logic relation, thus, 3b '100 is further transmitted to the low level position for judging that the 00 # core occupies the spin LOCK, finally, since the signal of lock_001 is transmitted at a low level, namely, for a certain spin LOCK, if the corresponding output value is 3b'100, the spin LOCK is occupied by the 11 # core.

The output result of the core lock control circuit is further selected by the lock control state circuit, and finally the rising edge signal of the clock signal is output. In addition, if the output is not 0, i.e., a spin lock is occupied, the signal indicating "locked" after the spin lock is acquired will go high. And is passed out in the internal circuitry. Also available from the design circuit described above, in the internal circuit, when one spin lock is not occupied by any core, its output in the internal circuit is 0. Fig. 5 is a schematic diagram of a circuit of a LOCK acquired state in an alternative LOCK state circuit structure according to an embodiment of the present application, as shown in fig. 5, the circuit of the LOCK acquired state may include, but is not limited to, or a module, an and module, and an equal module, etc., when the spin LOCK is unoccupied (i.e., the internal output is 3b' 000) and any one of lock_001, lock_010, lock_011, or lock_100 is at a high level, that is, it indicates that the spin LOCK has been occupied by a certain core at this time, and the state of the spin LOCK acquired is at a high level. The output value delivered from the lock control circuit will be further passed to the high level position of the selector controlled by the lock acquired state when the lock acquired state is high. This value is passed further into the low level of the lock released state and out with the rising clock edge.

In one exemplary embodiment, the first allocation result may be, but is not limited to, sent to the first processor by: and sending the first distribution result carrying a first sum value to the first processor, wherein the first sum value is equal to the sum value of the value corresponding to the identifier of the first processor and a preset third reference value.

Alternatively, in the present embodiment, the first reference value and the third reference value may be, but are not limited to, the same or different reference values.

Alternatively, in this embodiment, the value corresponding to the identifier of the first processor and the third reference value may, but are not limited to, be a value under the same target system, where the target system may, but is not limited to, include binary system, decimal system, hexadecimal system, and so on, and this application is not limited thereto.

For example, in decimal, the identification of the first processor may, but is not limited to, include the number of the first processor, e.g., the number of the first processor is 5, the third reference value may, but is not limited to, 1 (or 0, or 3, etc., as this application is not limited to), in which case the sum of 5 and 1, 6, may, but is not limited to, be sent to the first processor in the allocation result.

In one exemplary embodiment, the above method may further include, but is not limited to, by: obtaining a target release request initiated by the first processor to the target spin lock under the condition that the target spin lock is distributed to the first processor, wherein the target release request is used for requesting to release the target spin lock distributed to the first processor; and releasing the target spin lock allocated to the first processor in response to the target release request, wherein the first processor releasing the target spin lock is configured to disable operation on data in the target memory.

Optionally, in this embodiment, after the first processor completes the operation on the data in the target memory through the target spin lock, the target spin lock may be released, but not limited to, in which case the first processor may initiate a target release request to the target spin lock, so that the target spin lock may be allocated to other processors.

Alternatively, in this embodiment, fig. 6 is a schematic diagram of a circuit of a lock released state in an alternative lock state circuit structure according to an embodiment of the present application, and as shown in fig. 6, the circuit may include, but is not limited to, a two-part spin lock being occupied by a core and release of the spin lock after inputting a release command, and the circuit of the lock released state may include, but is not limited to, or a module, an and module, and an equal module, etc., and the state of the spin lock is occupied when the internal output in the lock basic circuit structure is not 0. For example, when the internal output of the 00 core is 3'b001, or the internal output of the 01 core is 3' b010, or the internal output of the 10 core is 3'b011, or the internal output of the 11 core is 3' b100, the spin lock is in an occupied state. The circuit in the lock released state judges whether the core holding the spin lock and the core initiating the lock releasing command to the spin lock are the same core or not when the command to release the lock is acquired, and then the spin lock is released and can be occupied again when the core holding the spin lock and the core initiating the lock releasing command to the spin lock are the same core. For example, the release command carries the number 2'b00 of the core which initiates the release lock to the spin lock, which indicates a release command initiated by the 00 core, and if the core which currently occupies the spin lock is 3' b001, in this case, the core which holds the spin lock and the core which initiates the release lock to the spin lock are the same core, the spin lock is released from the 00 core in response to the release command; if the core number currently occupying the spin lock is 3' b010, in such a case, the core holding the spin lock and the core initiating the lock release command to the spin lock are not the same core, the spin lock is not released from the 01 core.

The lock state and the lock control circuit together form a circuit for acquiring and releasing a specific lock in the four-core system, and it can be seen that, for a specific lock, if the lock is acquired by performing a read operation on an X-core, if the return value is the number of the core plus 1, the lock is in an idle state before and is currently occupied by the X-core. If the output value is Y, this indicates that the lock is currently a core occupation numbered Y minus one.

The circuit module may be instantiated multiple times for multiple lock addresses. And determines by address selection which core in particular has obtained which lock. Taking 128 locks as an example, the locks occupy a total of 27 address spaces, a total of seven bit signals. Thus in a four core system, the third through ninth bit signals in the bus address are indicated as core specific access to the address space of the lock, since the first two bit signals indicate which core the specific core is to access the address space of the lock. Combining specific core numbers with lock addresses in conjunction with bus accesses reduces the time required for the overall process. The locks can be divided into different groups by the 128, and the basic circuit module is further subjected to multiple instantiations in the groups, the output result of the basic circuit is transmitted step by step in the spin lock system, the read data is finally transmitted to the outside of the spin lock, and the actual occupation condition of the check lock can be judged through the final output value of the spin lock. The above is the occupation condition of the lock to the core under the multi-core concurrent processing mechanism. It should be noted that, in the embodiment of the present application, only the circuit of the spin lock in the 4-core system is explained and illustrated, and the present application is not limited to this, and the present application can be extended to 6 cores or more in practice. In addition, the number of the locks can be flexibly adjusted according to actual needs.

In one exemplary embodiment, the target spin lock assigned to the first processor may be released, but is not limited to, by: and writing a preset fourth reference value into a target storage address corresponding to the target spin lock, wherein the target spin lock written with the fourth reference value into the target storage address is set to be not allocated to any processor.

Alternatively, in this embodiment, in a case where the spin lock allocated to the processor needs to be released, the processor holding the spin lock may release the lock that it has acquired by writing a preset fourth reference value into the address where the spin lock is stored, but may not be limited to, in a case where the write enable signal is pulled high; the fourth reference value may be, but is not limited to, 0, 1, etc., which is not limited by the present application.

Alternatively, in the present embodiment, the target memory address may be, but is not limited to, an address representing an address space in which the target spin lock is stored.

In one exemplary embodiment, after said releasing said target spin lock allocated to said first processor, the above method further comprises: acquiring a second allocation request initiated by a third processor to the target spin lock corresponding to the target memory, wherein the second allocation request is used for requesting to allocate the target spin lock to the third processor, and the third processor allocated with the target spin lock is set to allow operation on data stored in the target memory; obtaining the target state information of the target spin lock in response to the second allocation request, wherein the target state information indicates whether the target spin lock has been allocated to a processor; and in the case that the target state information indicates that the target spin lock is not allocated to a processor, allocating the target spin lock to the third processor, and sending a fourth allocation result to the third processor, wherein the fourth allocation result is used for indicating the third processor to which the target spin lock is allocated.

Alternatively, in this embodiment, where the target spin lock has been released from the first processor, it may be appreciated that the target spin lock is not allocated to the first processor, in which case there may be multiple processors desiring to acquire the target spin lock, e.g., a third processor, in which case the third processor may, but is not limited to, initiate an allocation request to the target spin lock requesting allocation of the target spin lock to the third processor.

In one exemplary embodiment, the fourth allocation result may be sent to the third processor, but is not limited to, by: acquiring an identification of the third processor; and sending the fourth distribution result carrying a third sum value to the third processor, wherein the third sum value is equal to the sum value of the value corresponding to the identifier of the third processor and a preset sixth reference value.

Alternatively, in this embodiment, in the case where the target spin lock is allocated to the third processor, the value corresponding to the identifier of the third processor under the target system may be obtained, and the sixth reference value and the identifier of the third processor may be, but are not limited to, the values under the target system.

In order to better understand the method for controlling the spin lock in the embodiments of the present application, the application scenario of the method for controlling the spin lock in the embodiments of the present application is explained and illustrated below in conjunction with the optional embodiments, which may be, but not limited to, applied to the embodiments of the present application.

The application scenario of the control method of the spin lock in the embodiment of the present application may be, but is not limited to, multi-core concurrent processing, and it may be understood that in the application scenario of multi-core concurrent processing, the application scenario includes multiple processors, where the multiple processors may each initiate an allocation request to a target spin lock, and the multiple processors may be, but are not limited to, cascaded. Fig. 7 is a schematic diagram of acquiring and releasing a spin lock in an optional multi-core concurrent processing application scenario according to an embodiment of the present application, as shown in fig. 7, the acquiring and releasing of the spin lock may be implemented, but is not limited to, by the following steps:

in step S801, a certain core of the multi-core system initiates a read operation, for example, but not limited to, the acquisition of the spin lock in the multi-core system may be implemented by initiating a read operation to the spin lock, and for a mechanism of multi-core concurrent processing, different cores acquire the spin lock through different addresses, and when a read enable signal is pulled high, a specific core in the SOC multi-core system sends a read signal to an address where the spin lock is stored.

Step S802, determining whether the spin lock is available, performing step S803 in the case where the spin lock is in an available state, and performing step S804 in the case where the spin lock is in an unavailable state.

In step S803, the spin lock is occupied by the core, and a normal value (corresponding to the first sum value) is returned to indicate that the spin lock has been obtained, at which time the core can access the address data managed by the spin lock.

In step S804, other values are returned, wherein the other values indicate that the spin lock is already occupied by other cores, for example, when the spin lock is acquired by a certain core, no other core can acquire the spin lock, and if the other cores perform a read operation on the spin lock, other values (which are not equal to the normal values and are equivalent to the target and the value) are returned to indicate that the spin lock is already occupied by a certain core.

In step S805, the core holding the spin lock writes a preset fourth reference value into the address where the spin lock is stored to release the spin lock that has been obtained, for example, when the write enable signal is pulled high, the core holding the spin lock may, but is not limited to, release the spin lock that has been obtained by writing a preset fourth reference value (e.g., 0) into the address where the spin lock is stored, and after the core holding the spin lock releases the spin lock, the other cores may continue to obtain the spin lock through the read operation.

The application scenario of the spin lock control method in the embodiment of the present application may be, but is not limited to, including a single-core multithreading, and it may be understood that in the application scenario of the single-core multithreading, one processor is included, and multiple threads corresponding to one processor may each initiate a distribution request to a target spin lock, but are not limited to. FIG. 8 is a schematic diagram of acquiring and releasing a spin lock in an alternative single-core multithreading application scenario according to an embodiment of the present application, as shown in FIG. 8, for a single-core multithreading mechanism, the manner of acquiring the spin lock and releasing the lock is the same as in a multi-core concurrent processing mechanism, except that when a certain core has acquired a certain spin lock through a read operation, if a read signal is sent again to an address space storing the spin lock, an illegal value (corresponding to a second reference value) is returned. Acquisition and release of spin locks may be accomplished, but are not limited to, by:

in step S901, a certain checkup spin lock initiates a pass-through read operation.

Step S902, determining whether the spin lock is available, and in the case where the spin lock is in an available state, performing step S903.

Step S903, the acquisition of the spin lock is completed, and a normal value is returned, which indicates that the spin lock has been acquired, at which time the core can access the address data managed by the spin lock.

Step S904, determining whether the core transmits a read signal to the occupied lock address for the second time, performing step S905 if the core transmits a read signal to the occupied lock address for the second time, and performing step S903 if the core does not transmit a read signal to the occupied lock address for the second time.

Step S905 returns an illegal value.

For a single core, there may be a case where the same core accesses the same address twice or more in succession, and it is understood that the same core accesses the same spin lock continuously, so a status signal for determining whether a lock is acquired is "locked" is added to the spin lock circuit. The "locked" status signal is low when the internal output of the basic circuit in the spin lock circuit is 0, i.e. for a particular lock, when no core occupies it. When the internal output signal is not 0, the state signal will be pulled high on the next clock rising edge, indicating that the lock has been occupied. The status signal is transmitted out of the spin lock step by step together with the internal output value via different lock address packets. Before the data is finally read out of the spin lock, a determination is made according to the "locked" status signal, and fig. 9 is a determination circuit of an alternative single-core multithreading mechanism according to an embodiment of the present application, and as shown in fig. 9, the determination circuit of the single-core multithreading mechanism may include, but is not limited to, an equal module, an and module, a selector, and a subtract module. When the "locked" status signal and the internal output signal are passed to the outermost layer of the spin lock, it is indicated that the lock has been occupied by a core at the last moment if the "locked" status signal is high, and that it is the core itself that occupies the lock at the last moment if the number of the core performing the read operation (i.e. the first two bits of the bus address in a four core system represent the number) is equal to the internal output signal minus one. The whole process is simplified as follows: a core performs a read operation to a lock for a second occupation after occupying the lock, at which point an illegal value (e.g., 3' b 111) is read. When the "locked" status signal and the internal output signal are passed to the spin lock outermost layer, if the "locked" status signal is low, it means that the lock was not occupied by any core at the previous time and the lock is occupied at this time. The internal output signal is normally read, and a normal value is read at the moment, and the normal value is subtracted by one to represent the number of the core occupying the lock; furthermore, when the "locked" status signal and the internal output signal are passed to the outermost layer of the spin lock, if the "locked" status signal is high, but the number of the core performing the read operation (i.e., the first two bits of the bus address in the four-core system represent digits) is not equal to the internal output signal minus one, it means that the last time occupied the lock is the other core, at which point a further value is read, and the other value minus one means the number of the core occupying the lock.

By the spin lock control method in the embodiment of the application, a multi-core concurrent processing mechanism is supported, a single-core multi-thread processing mechanism is supported, a mode of realizing self-selection lock by adopting a hardware circuit is safer compared with software, cascade connection among a plurality of CPUs can be realized, meanwhile, the use of a large number of registers in a hardware system is avoided, the design scheme is simple and convenient, the complexity is effectively reduced, and the circuit area is reduced. And simultaneously, the lock address and the number of the core are combined with the bus address, so that the processing speed is increased. And may support expansion of core co-locks, such as expanding a lock to 256 or 512 locks, expanding a core to 8 or 16 cores, etc. In addition, a status signal of "locked" is introduced in the basic circuit of the lock to indicate whether the lock is occupied at the arrival of the last clock rising edge. And the mechanism of the spin lock can be judged according to the state and the internal output result, and the mechanism of the spin lock and the occupation condition of the core are described through the final read data.

It should be noted that the circuit in the implementation of the present application may be, but not limited to, a logic circuit.

From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially or portions contributing to the prior art may be embodied in the form of a software product stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk), including several instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the methods described in the embodiments of the present application.

The embodiment also provides a control device of the spin lock, which is used for implementing the above embodiment and the preferred implementation, and is not described again. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

Fig. 10 is a block diagram of a control device of a spin lock according to an embodiment of the present application, as shown in fig. 10, including:

a first obtaining module 1002, configured to obtain a first allocation request initiated by a first processor to a target spin lock corresponding to a target memory, where the first allocation request is used to request that the target spin lock be allocated to the first processor, and the first processor to which the target spin lock is allocated is configured to allow operation on data stored in the target memory;

a second obtaining module 1004, configured to obtain, in response to the first allocation request, target state information of the target spin lock, where the target state information indicates whether the target spin lock has been allocated to a processor;

A first processing module 1006, configured to, if the target state information indicates that the target spin lock is not allocated to a processor, allocate the target spin lock to the first processor, and send a first allocation result to the first processor, where the first allocation result is used to indicate the first processor to which the target spin lock is allocated.

By means of the device, when the first processor wants to operate data stored in the memory, the first processor needs to request to acquire the spin lock corresponding to the memory, in such a case, the lock acquiring state circuit can acquire the state information of the spin lock and transmit the state information to the lock control circuit, and the lock control circuit can indicate that the spin lock is not allocated to the processor when receiving the state information and the state information is used for indicating that the spin lock is idle, in such a case, the lock control circuit allocates the spin lock to the first processor and returns an allocation result to the first processor, wherein the allocation result is used for indicating the first processor to which the spin lock is allocated, and in such a manner, the lock control circuit automatically determines whether to allocate the spin lock to the processor requesting to allocate the spin lock according to the state information of the spin lock transmitted by the lock acquiring state circuit.

In one exemplary embodiment, the apparatus further comprises:

and a second processing module configured to keep the target spin lock allocated to the second processor and refuse to allocate the target spin lock to the first processor, after the target state information of the target spin lock is acquired, in a case where the target state information indicates that the target spin lock has been allocated to the second processor.

In one exemplary embodiment, the apparatus further comprises:

a determining module, configured to determine whether the second processor is the same as the first processor, and obtain a target determination result, where the target state information indicates that the target spin lock has been allocated to the second processor;

and the first sending module is used for sending a second allocation result corresponding to the target determination result to the first processor when the target determination result indicates that the second processor is different from the first processor, wherein the second allocation result is used for indicating that the target spin lock is allocated to the second processor.

In one exemplary embodiment, the apparatus further comprises:

And the second sending module is used for sending a third allocation result corresponding to the target determination result to the first processor when the target determination result indicates that the second processor is the same as the first processor, wherein the third allocation result is used for indicating that the target spin lock is allocated to the first processor.

In an exemplary embodiment, the first transmitting module includes:

a first obtaining unit, configured to obtain an identifier of the second processor from the target state information, where the target state information carries an identifier of the second processor to which the target spin lock is allocated;

the carrying unit is used for carrying the identifier of the second processor on the second allocation result;

and the first sending unit is used for sending the second allocation result to the first processor.

In one exemplary embodiment, the determining module includes:

the second acquisition unit is used for acquiring the identification of the first processor;

a first determining unit, configured to determine that the second processor is different from the first processor when a preset first matching condition is satisfied between a value corresponding to the identifier of the second processor, a value corresponding to the identifier of the first processor, and a preset first reference value;

And the second determining unit is used for determining that the second processor is identical with the first processor under the condition that a preset first matching condition is not met among the value corresponding to the identifier of the second processor, the value corresponding to the identifier of the first processor and a preset first reference value.

In an exemplary embodiment, the second obtaining unit is configured to:

the identification of the first processor is obtained from a first bus address of the target spin lock, wherein the first allocation request is an allocation request initiated by the first processor to the target spin lock through the first bus address.

In one exemplary embodiment, the first processing module includes:

and the second sending unit is used for sending the first distribution result carrying a first sum value to the first processor, wherein the first sum value is equal to the sum value of the value corresponding to the identifier of the first processor and a preset third reference value.

In one exemplary embodiment, the second acquisition module includes:

a third obtaining unit, configured to obtain a set of allocation states corresponding to the target spin lock, where one allocation state in the set of allocation states is used to indicate whether the target spin lock is allocated to one processor in the set of processors;

And a third determining unit, configured to determine the target state information of the target spin lock according to the set of allocation states.

In an exemplary embodiment, the third determining unit is configured to:

determining the target state information of the target spin lock according to N allocation states, wherein the set of allocation states includes the N allocation states, one allocation state of the N allocation states being used to indicate whether the target spin lock is allocated to one processor of N processors, the set of processors including the N processors, N being a positive integer greater than or equal to 1:

determining that the target state information indicates that the target spin lock is allocated to a second processor when an ith allocation state is a high level state and allocation states other than the ith allocation state are low level states in the N allocation states, wherein the second processor is a processor corresponding to the ith allocation state, and i is a positive integer greater than or equal to 1 and less than or equal to N;

and determining that the target state information indicates that the target spin lock is not allocated to a processor when all of the N allocation states are the low level states.

In one exemplary embodiment, the apparatus further comprises:

a third obtaining module, configured to obtain, when the target spin lock is allocated to the first processor, a target release request initiated by the first processor to the target spin lock, where the target release request is used to request release of the target spin lock allocated to the first processor;

and a release module, configured to release the target spin lock allocated to the first processor in response to the target release request, where the first processor that releases the target spin lock is configured to prohibit an operation on data in the target memory.

In one exemplary embodiment, the release module includes:

and the writing unit is used for writing a preset fourth reference value into a target storage address corresponding to the target spin lock, wherein the target spin lock written with the fourth reference value into the target storage address is set to be unassigned to any processor.

It should be noted that each of the above modules may be implemented by software or hardware, and for the latter, it may be implemented by, but not limited to: the modules are all located in the same processor; alternatively, the above modules may be located in different processors in any combination.

Embodiments of the present application also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

In one exemplary embodiment, the computer readable storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.

Embodiments of the present application also provide an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

In an exemplary embodiment, the electronic apparatus may further include a transmission device connected to the processor, and an input/output device connected to the processor.

Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.

It will be appreciated by those skilled in the art that the modules or steps of the embodiments of the application described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than what is shown or described, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the embodiments of the present application, but rather, various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principles of the embodiments of the present application should be included in the protection scope of the embodiments of the present application.

Claims

1. A control device of a spin lock, comprising a target spin lock, a lock acquisition state circuit, and a lock control circuit, wherein an input of the target spin lock is configured to be coupled to a plurality of processors; the output end of the lock acquisition state circuit is connected with the first input end of the lock control circuit, and the input end of the lock acquisition state circuit is connected with the first output end of the target spin lock; the second input end of the lock control circuit is connected with the second output end of the target spin lock, and the output end of the lock control circuit is connected with the third input end of the target spin lock;

the lock acquisition state circuit is configured to acquire target state information of the target spin lock in response to a first allocation request sent by a first processor of the plurality of processors, and output the target state information to the lock control circuit, in a case where the target spin lock acquires the first allocation request, the target spin lock corresponding to a target memory, the first allocation request requesting allocation of the target spin lock to the first processor, the first processor to which the target spin lock is allocated being configured to allow operation of data stored in the target memory;

The lock control circuit is configured to, upon receiving the target state information and indicating that the target spin lock is not allocated to a processor, allocate the target spin lock to a first processor of the plurality of processors and output a first allocation result to the first processor through the target spin lock, wherein the first allocation result is used to indicate the first processor to which the target spin lock is allocated;

the lock control circuit comprises a first lock control circuit and a second lock control circuit, wherein one input end of the first lock control circuit is used as a first input end of the lock control circuit to be connected with the output end of the lock acquisition state circuit, the output end of the first lock control circuit is connected with one input end of the second lock control circuit, the other input end of the second lock control circuit is used as a second input end of the lock control circuit to be connected with the second output end, and the output end of the second lock control circuit is used as an output end of the lock control circuit to be connected with a third input end of the target spin lock;

Wherein the first lock control circuit is arranged to output an identification of a second processor to the second lock control circuit if the target state information indicates that the target spin lock has been allocated to the second processor;

the second lock control circuit is configured to acquire the identification of the first processor if the identification of the second processor is received; outputting a first level signal under the condition that a preset first matching condition is met among a value corresponding to the identifier of the second processor, a value corresponding to the identifier of the first processor and a preset first reference value, wherein the first level signal is used for indicating that the second processor is different from the first processor; and outputting a second level signal under the condition that a preset first matching condition is not met between the value corresponding to the identifier of the second processor, the value corresponding to the identifier of the first processor and a preset first reference value, wherein the second level signal is used for indicating that the second processor is identical to the first processor, and the amplitude of the first level signal is higher than that of the second level signal.

2. The apparatus of claim 1, wherein the lock control circuit is further configured to, upon receiving the target state information and the target state information indicating that the target spin lock has been assigned to a second processor of the plurality of processors, remain assigned to the second processor and refuse to assign the target spin lock to the first processor.

3. The apparatus of claim 2, wherein the lock control circuit is further configured to determine whether the second processor is the same as the first processor, resulting in a target determination, if the target state information is received and the target state information indicates that the target spin lock has been assigned to the second processor; and in the case that the target determination result indicates that the second processor is different from the first processor, sending a second allocation result corresponding to the target determination result to the first processor through the target spin lock, wherein the second allocation result is used for indicating that the target spin lock is allocated to the second processor.

4. The apparatus of claim 1, wherein the second lock control circuit comprises a first equalization module, wherein,

an output of the first equalization module is connected to the third input of the target spin lock, an input of the first equalization module is connected to the second output of the target spin lock as the second input of the lock control circuit, wherein,

the first equality module is configured to obtain an identification of the first processor from a first bus address output from the second output of the target spin lock, wherein the first allocation request is an allocation request initiated by the first processor to the target spin lock via the first bus address.

5. The apparatus of claim 4, wherein the second lock control circuit further comprises a first selector module, wherein,

one input end of the first selector module is connected with the output end of the first lock control circuit, the output end of the first selector module is connected with the third input end of the target spin lock, and the other input end of the first selector module is connected with the output end of the first equivalent module;

the first equalization module is further configured to output the second level signal and output the second level signal to the first selector module when a preset first matching condition is not satisfied between a value corresponding to the identifier of the second processor, a value corresponding to the identifier of the first processor, and a preset first reference value;

the first selector module is arranged to, upon receipt of the second level signal, output a third allocation result carrying a second reference value indicating that the processor to which the target spin lock has been allocated is the first processor, and to send the third allocation result to the first processor via the target spin lock.

6. The apparatus of claim 1, wherein the first selector module is further configured to send, to the first processor via the target spin lock, the first allocation result carrying a first sum value, where the first sum value is equal to a sum value of a value corresponding to an identification of the first processor and a preset third reference value, if the target state information indicates that the target spin lock is not allocated to a processor and the target spin lock is allocated to the first processor.

7. The apparatus of claim 1, wherein the first lock control circuit is further configured to obtain a set of level signals corresponding to the target spin lock, wherein one of the set of level signals is used to indicate whether the target spin lock is assigned to one of the plurality of processors; the target state information of the target spin lock is determined from the set of level signals.

8. The apparatus of claim 7, wherein the first lock control circuit comprises N selector modules, a first selector module, and a second selector module, wherein,

one input end of the first selector module is used as the first input end to be connected with the output end of the lock acquisition state circuit, and the output end of the second selector module is connected with the input end of the second lock control circuit;

The output end of the last selector module in the N selector modules is connected with the other input end of the first selector module, the output end of the j selector module in the N selector modules is connected with one input end of the j+1th selector module, one input end of the j selector module is connected with the output end of the j-1th selector module, the other input end of the j selector module is connected with the first output end of the target spin lock, the input end of the first selector module in the N selector modules is connected with the first output end of the target spin lock, the selector modules comprise the N selector modules, N is a positive integer greater than or equal to 1, and j is a positive integer greater than or equal to 2 and less than or equal to N;

the first lock control circuit is configured to determine the target state information of the target spin lock from N level signals output by the target spin lock by performing the steps of: determining that the target state information indicates that the target spin lock is allocated to a second processor when the amplitude of the ith level signal in the N level signals is a first amplitude and the amplitudes of all the N level signals except the ith level signal are second amplitudes, wherein the second processor is a processor corresponding to the ith level signal, the first amplitude is greater than the second amplitude, and i is a positive integer greater than or equal to 1 and less than or equal to N; and determining that the target state information indicates that the target spin lock is not allocated to the processor when the magnitudes of the N level signals are all the second magnitudes.

9. The apparatus of claim 1, further comprising a lock release status circuit, wherein,

the input end of the lock release state circuit is connected with the third output end of the target spin lock, the output end of the lock release state circuit is connected with the other input end of the lock control circuit, and the other input end of the lock control circuit is the other input end of the second selector module in the first lock control circuit;

the lock release state circuit is configured to release the target spin lock allocated to the first processor in response to a target release request that requests release of the target spin lock allocated to the first processor, when the target spin lock is allocated to the first processor and a target release request initiated by the first processor to the target spin lock is acquired, wherein the first processor that released the target spin lock is configured to prohibit operation on data in the target memory.

10. A control method of a spin lock, characterized by being performed by a control device of a spin lock, the control device of a spin lock comprising a target spin lock, a lock acquisition state circuit, and a lock control circuit, wherein the method comprises:

Acquiring a first allocation request initiated by a first processor to a target spin lock corresponding to a target memory, wherein the first allocation request is used for requesting to allocate the target spin lock to the first processor, and the first processor allocated with the target spin lock is set to allow operation on data stored in the target memory;

obtaining target state information of the target spin lock in response to the first allocation request, wherein the target state information indicates whether the target spin lock has been allocated to a processor;

assigning the target spin lock to the first processor and sending a first assignment result to the first processor, wherein the first assignment result is used for indicating the first processor to which the target spin lock is assigned, in the case that the target state information indicates that the target spin lock is not assigned to a processor;

in the case where the lock control circuit includes a first lock control circuit and a second lock control circuit, and the target state information indicates that the target spin lock has been allocated to a second processor, the first lock control circuit outputs an identification of the second processor to the second lock control circuit;

The second lock control circuit obtains the identification of the first processor under the condition that the identification of the second processor is received; under the condition that a preset first matching condition is met between a value corresponding to the identifier of the second processor, a value corresponding to the identifier of the first processor and a preset first reference value, the second lock control circuit outputs a first level signal, wherein the first level signal is used for indicating that the second processor and the first processor are different; and under the condition that a preset first matching condition is not met between the value corresponding to the identifier of the second processor, the value corresponding to the identifier of the first processor and a preset first reference value, the second lock control circuit outputs a second level signal, wherein the second level signal is used for indicating that the second processor is identical to the first processor, and the amplitude of the first level signal is higher than that of the second level signal.

11. The method of claim 10, wherein after the obtaining the target state information of the target spin lock, the method further comprises:

in the event that the target state information indicates that the target spin lock has been allocated to a second processor, the allocation of the target spin lock to the second processor is maintained and the allocation of the target spin lock to the first processor is denied.

12. The method of claim 11, wherein in the event that the target state information indicates that the target spin lock has been assigned to a second processor, the method further comprises:

determining whether the second processor is the same as the first processor or not, and obtaining a target determination result;

and in the case that the target determination result indicates that the second processor is different from the first processor, sending a second allocation result corresponding to the target determination result to the first processor, wherein the second allocation result is used for indicating that the target spin lock is allocated to the second processor.

13. The method according to claim 12, wherein the method further comprises:

and if the target determination result indicates that the second processor is the same as the first processor, sending a third allocation result corresponding to the target determination result to the first processor, wherein the third allocation result is used for indicating that the target spin lock is allocated to the first processor.

14. The method of claim 12, wherein the sending, to the first processor, a second allocation result corresponding to the target determination result if the target determination result indicates that the second processor is different from the first processor, comprises:

Acquiring an identifier of the second processor from the target state information, wherein the target state information carries the identifier of the second processor to which the target spin lock is allocated;

carrying the identification of the second processor on the second allocation result;

and sending the second allocation result to the first processor.

15. The method of claim 12, wherein determining whether the second processor is the same as the first processor results in a target determination result comprises:

acquiring an identification of the first processor;

determining that the second processor is different from the first processor under the condition that a preset first matching condition is met between a value corresponding to the identifier of the second processor, a value corresponding to the identifier of the first processor and a preset first reference value;

and determining that the second processor is identical to the first processor under the condition that a preset first matching condition is not met between the value corresponding to the identifier of the second processor, the value corresponding to the identifier of the first processor and a preset first reference value.

16. The method of claim 15, wherein the obtaining the identification of the first processor comprises:

17. The method of claim 10, wherein the sending the first allocation result to the first processor comprises:

and sending the first distribution result carrying a first sum value to the first processor, wherein the first sum value is equal to the sum value of the value corresponding to the identifier of the first processor and a preset third reference value.

18. The method of claim 10, wherein the obtaining target state information for the target spin lock comprises:

obtaining a set of allocation states corresponding to the target spin lock, wherein one allocation state in the set of allocation states is used for indicating whether the target spin lock is allocated to one processor in the set of processors;

and determining the target state information of the target spin lock according to the group of allocation states.

19. The method of claim 18, wherein said determining said target state information for said target spin lock from said set of allocation states comprises:

20. The method according to claim 10, wherein the method further comprises:

Obtaining a target release request initiated by the first processor to the target spin lock under the condition that the target spin lock is distributed to the first processor, wherein the target release request is used for requesting to release the target spin lock distributed to the first processor;

and releasing the target spin lock allocated to the first processor in response to the target release request, wherein the first processor releasing the target spin lock is configured to disable operation on data in the target memory.

21. The method of claim 20, wherein the releasing the target spin lock allocated to the first processor comprises:

and writing a preset fourth reference value into a target storage address corresponding to the target spin lock, wherein the target spin lock written with the fourth reference value into the target storage address is set to be not allocated to any processor.

22. The method of claim 10, wherein the step of determining the position of the first electrode is performed,

the input end of the target spin lock is connected with a plurality of processors; the output end of the lock acquisition state circuit is connected with the first input end of the lock control circuit, and the input end of the lock acquisition state circuit is connected with the first output end of the target spin lock; the second input end of the lock control circuit is connected with the second output end of the target spin lock, and the output end of the lock control circuit is connected with the third input end of the target spin lock;

The lock control circuit comprises a first lock control circuit and a second lock control circuit, wherein one input end of the first lock control circuit is used as a first input end of the lock control circuit to be connected with the output end of the lock acquisition state circuit, the output end of the first lock control circuit is connected with one input end of the second lock control circuit, the other input end of the second lock control circuit is used as a second input end of the lock control circuit to be connected with the second output end, and the output end of the second lock control circuit is used as an output end of the lock control circuit to be connected with a third input end of the target spin lock.

23. A computer readable storage medium, characterized in that a computer program is stored in the computer readable storage medium, wherein the computer program, when being executed by a processor, implements the steps of the method of any of claims 10 to 22.

24. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method as claimed in any one of claims 10 to 22 when the computer program is executed.