CN117097329A - Digital signal processing method and system - Google Patents
Digital signal processing method and system Download PDFInfo
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- CN117097329A CN117097329A CN202311300360.9A CN202311300360A CN117097329A CN 117097329 A CN117097329 A CN 117097329A CN 202311300360 A CN202311300360 A CN 202311300360A CN 117097329 A CN117097329 A CN 117097329A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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Abstract
The application relates to the technical field of computers and provides a digital signal processing method and a digital signal processing system. The method comprises the following steps: generating, by the first loop, a first current control signal based on a comparison result between the first digital signal and the reference digital signal, and controlling a first voltage controlled oscillator of the first loop based on the first current control signal to generate an output digital signal; based on the comparison result, a phase difference between the signals is determined, and based on the phase difference, the first parallel path is selectively connected or disconnected. When connected, the first parallel path generates a second current control signal based on the comparison result and is superimposed to the first current control signal. The loop bandwidth of the first loop when the first parallel path is connected is greater than the loop bandwidth when it is disconnected. In this way, the lock time is reduced and noise immunity is achieved.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a digital signal processing method and system.
Background
With the development of artificial intelligence, cloud computing and other technologies, high-speed digital signal transmission is widely applied. In high-speed digital communication applications, such as SERializer de-SERializer (SERializer/DESerializer, SERDES), it is necessary to recover clock signals and data signals from a high-speed serial signal. In the prior art, a long time is required for convergence of the phase error and entering a locking state in simulation and practical application, which is unfavorable for quick response and control of design cost.
Therefore, the application provides a digital signal processing method and a digital signal processing system, which are used for solving the technical problems in the prior art.
Disclosure of Invention
In a first aspect, the present application provides a digital signal processing method. The digital signal processing method comprises the following steps: generating a first current control signal based on a comparison result between a first digital signal and a reference digital signal through a first loop, and controlling a first voltage-controlled oscillator included in the first loop to generate an output digital signal based on the first current control signal, wherein the first digital signal is obtained by frequency division of the output digital signal; and selectively connecting or disconnecting a first parallel path based on the phase difference, wherein when the first parallel path is connected, the first parallel path generates a second current control signal based on the comparison result and the second current control signal is superimposed to the first current control signal, and a loop bandwidth of the first loop when the first parallel path is connected is greater than a loop bandwidth of the first loop when the first parallel path is disconnected.
According to the first aspect of the application, the first parallel communication path is selectively connected or disconnected, so that the phase error convergence speed is improved, the locking time is reduced, the quick response and the cost reduction are facilitated, the anti-noise performance is good, the hierarchical structure of the original circuit is not disturbed, and the hardware cost of the original circuit is not increased.
In a possible implementation manner of the first aspect of the present application, the first loop includes a first charge pump and a first loop filter, the comparison result is input to the first charge pump, and an output of the first charge pump is filtered by the first loop filter to obtain the first current control signal.
In a possible implementation manner of the first aspect of the present application, the first loop further includes a first phase frequency detector, the first phase frequency detector is configured to receive the first digital signal and the reference digital signal and generate the comparison result between the first digital signal and the reference digital signal, and the first voltage controlled oscillator is configured to generate the output digital signal based on the first current control signal.
In a possible implementation manner of the first aspect of the present application, the first parallel path includes a first switch, wherein the first switch is closed when the first parallel path is communicated based on the phase difference, and the first switch is opened when the first parallel path is opened based on the phase difference.
In a possible implementation manner of the first aspect of the present application, the first parallel path further includes a second charge pump and a second loop filter, when the first parallel path is connected, the comparison result is input to the second charge pump, an output of the second charge pump is filtered by the second loop filter to obtain the second current control signal, and the first switch is connected in series with the second charge pump and the second loop filter.
In a possible implementation manner of the first aspect of the present application, the first parallel path is disconnected when the phase difference is smaller than a first phase difference threshold value, and the first parallel path is connected when the phase difference is larger than the first phase difference threshold value.
In a possible implementation manner of the first aspect of the present application, when the first parallel path is disconnected, the first loop operates in a low bandwidth operation mode, and when the first parallel path is connected, the first loop operates in a high bandwidth mode, wherein a signal transmission path of the first loop in the low bandwidth operation mode is consistent with a signal transmission path of the first loop in the high bandwidth operation mode.
In a possible implementation manner of the first aspect of the present application, the larger the loop bandwidth of the first loop, the higher the convergence speed of the phase error of the first loop, and the distribution of the zero point pole of the loop filter transfer function of the first loop in the low bandwidth operation mode with respect to the loop bandwidth of the first loop in the low bandwidth operation mode is consistent with the distribution of the zero point pole of the loop filter transfer function of the first loop in the high bandwidth operation mode with respect to the loop bandwidth of the first loop in the high bandwidth operation mode.
In a possible implementation manner of the first aspect of the present application, the first parallel path further includes a phase lock detection module, where the phase lock detection module is configured to: and determining the phase difference based on the comparison result, judging whether the phase difference is within a preset phase difference range, if so, disconnecting the first parallel passage, and if not, connecting the first parallel passage.
In a possible implementation manner of the first aspect of the present application, the digital signal processing method further includes: and selectively switching on or off a second parallel path based on the frequency difference, wherein when the second parallel path is switched on, the second parallel path generates a third current control signal based on the frequency difference and the third current control signal is superimposed to the first current control signal, the first loop together with the second parallel path forming a frequency locked loop when the second parallel path is switched on.
In a possible implementation manner of the first aspect of the present application, the second parallel path includes a frequency difference measurement module, a voltage-controlled current source, a capacitor and a second switch, where the frequency difference measurement module is configured to receive the first digital signal and the reference digital signal and determine the frequency difference, the frequency difference is input to the voltage-controlled current source, and an output of the voltage-controlled current source obtains the third current control signal through the capacitor.
In a possible implementation manner of the first aspect of the present application, the second parallel path is connected when the frequency difference exceeds a first frequency difference range; disconnecting the second parallel path and connecting the first parallel path when the frequency difference is within the first frequency difference range and the phase difference exceeds a first phase difference range; when the frequency difference is within the first frequency difference range and the phase difference is within the first phase difference range, the second parallel path is disconnected and the first parallel path is disconnected.
In a possible implementation manner of the first aspect of the present application, the digital signal processing method is used for a first frequency-locking phase-locking operation of a phase-locked loop circuit, where the first frequency-locking phase-locking operation includes: the first parallel path is disconnected and the second parallel path is connected until the frequency difference is within the first frequency difference range, then the first parallel path is connected and the second parallel path is disconnected until the phase difference is within the first phase difference range, and then the first parallel path is disconnected and the second parallel path is disconnected.
In a possible implementation manner of the first aspect of the present application, the digital signal processing method is used for a second frequency-locking phase-locking operation of the phase-locked loop circuit, where the second frequency-locking phase-locking operation includes: and connecting the first parallel path and disconnecting the second parallel path until the phase difference is within the first phase difference range, disconnecting the first parallel path and disconnecting the second parallel path, wherein the phase-locked loop circuit selects the first frequency-locking operation or the second frequency-locking operation based on an initial process angle condition and an initial frequency difference.
In a second aspect, the embodiment of the application also provides a digital signal processing system. The digital signal processing system includes: a first loop, wherein the first loop is configured to: generating a first current control signal based on a comparison result between a first digital signal and a reference digital signal, and controlling a first voltage-controlled oscillator included in the first loop to generate an output digital signal based on the first current control signal, wherein the first digital signal is obtained by frequency division of the output digital signal; a first parallel path, wherein the first parallel path is selectively connected or disconnected based on a phase difference between the first digital signal and the reference digital signal, the phase difference being determined based on the comparison result, the first parallel path generating a second current control signal based on the comparison result and the second current control signal being superimposed to the first current control signal when the first parallel path is connected, a loop bandwidth of the first loop being greater than a loop bandwidth of the first loop when the first parallel path is disconnected.
According to the second aspect of the application, the first parallel communication path is selectively connected or disconnected, so that the phase error convergence speed is improved, the locking time is reduced, the quick response and the cost reduction are facilitated, the anti-noise performance is good, the hierarchical structure of the original circuit is not disturbed, and the hardware cost of the original circuit is not increased.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a digital signal processing method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a digital signal processing system according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a digital signal processing system according to another embodiment of the present application;
fig. 4 is a schematic structural diagram of a computing device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
It should be understood that in the description of the application, "at least one" means one or more than one, and "a plurality" means two or more than two. In addition, the words "first," "second," and the like, unless otherwise indicated, are used solely for the purposes of description and are not to be construed as indicating or implying a relative importance or order.
Fig. 1 is a flow chart of a digital signal processing method according to an embodiment of the present application. As shown in fig. 1, the data signal processing method includes the following steps.
Step S110: and generating a first current control signal based on a comparison result between a first digital signal and a reference digital signal through a first loop, and controlling a first voltage-controlled oscillator included in the first loop to generate an output digital signal based on the first current control signal, wherein the first digital signal is obtained by frequency division of the output digital signal.
Step S120: and selectively connecting or disconnecting a first parallel path based on the phase difference, wherein when the first parallel path is connected, the first parallel path generates a second current control signal based on the comparison result and the second current control signal is superimposed to the first current control signal, and a loop bandwidth of the first loop when the first parallel path is connected is greater than a loop bandwidth of the first loop when the first parallel path is disconnected.
The digital signal processing method shown in fig. 1 is suitable for high-speed data communication applications such as SERializer/deserializer (SERializer/DESerializer, SERDES). The clock signal is recovered from the high-speed serial signal and then the data signal is recovered by a clock data recovery (Clock Data Recovery, CDR) circuit. The CDR typically employs a phase-locked loop (PLL) structure. The basic structure of the PLL includes a Phase Detector (PD), a Loop Filter (LF), and a voltage controlled oscillator (voltage controlled oscillator, VCO). Some PLLs use a phase frequency detector (phase-frequency detector). The voltage controlled oscillator is used to generate a modulated output frequency from an input control voltage, i.e. a modulation signal. The output of the voltage controlled oscillator is input through a feedback loop to a phase detector for phase detection (frequency phase detection if a phase frequency detector) for example by comparing the edges of two input signals, one being the reference clock signal and the other being the output signal of the VCO via the feedback loop. The error voltage output by the phase detector is filtered by a loop filter (generally, low pass) and high frequency components are filtered to obtain a control voltage of the voltage-controlled oscillator, so that the frequency of the output signal of the voltage-controlled oscillator can be changed. The PLL internally passes through the phase discriminator, the loop filter and the voltage-controlled oscillator, and based on the feedback principle, a negative feedback mechanism is realized, so that the output frequency of the voltage-controlled oscillator is subjected to negative feedback processing, thereby being consistent with the signal frequency (for example, a high-speed serial signal received by a clock data recovery circuit) and the phase difference is also fixed, and thus, frequency and phase locking are realized. The PLL compares errors in frequency and phase of the voltage controlled oscillator based on a feedback principle and generates a corresponding error voltage such that the frequency of the voltage controlled oscillator coincides with the signal frequency (and the phase difference is also fixed) to allow the voltage controlled oscillator to output a desired recovered clock signal. In chip design simulation verification and practical application, it is necessary to wait until the PLL is completely stable, i.e., enters a locked state, before accurately measuring deterministic jitter and performing other operations. The length of time the PLL enters the locked state, i.e., the lock time, is determined primarily by the operating bandwidth of the PLL. In particular, since the PLL operates on a principle that relies on a negative feedback mechanism, i.e. having the output of the VCO (optionally via a frequency divider) input to the phase detector via a feedback loop as one of the inputs, the other input of the phase detector is the reference clock. In this way the phase detector compares the phase difference of the two inputs and generates a phase error voltage, for example by comparing the edges of the two input signals. The phase error voltage is filtered and then used as the control voltage of the VCO, thereby affecting the frequency of the output voltage of the VCO. In this way, the frequency of the output voltage of the VCO is gradually changed to make the frequencies of the two input signals of the phase discriminator consistent, that is, the frequency of the VCO output signal converges to the frequency of the reference clock after passing through the frequency divider, and finally the VCO output signal after converging with the phase error obtains the output clock after passing through the frequency divider. Such a negative feedback mechanism, depending on the convergence speed of the phase error of the PLL, needs to wait until the PLL is completely stable, i.e. enters a locked state (the two input signals of the phase detector are at the same frequency or in phase with the same frequency), in order to accurately measure deterministic jitter. Factors that affect the PLL reaching a locked state or steady state are: the phase detector settings such as gain, loop filter settings such as gain, initial static frequency (or natural oscillation frequency) of the VCO, and the bandwidth of the PLL. The bandwidth of the PLL is the frequency range in which the PLL can lock, and a larger PLL bandwidth means a larger frequency range that can be locked by the PLL, but this also means more noise. For a low-bandwidth PLL, noise immunity is high because the PLL bandwidth is small, but this also affects the phase error convergence speed of the PLL, resulting in a long lock time for the PLL to enter a locked state. Therefore, the embodiment of the application provides a digital signal processing method and a digital signal processing system, which not only have larger phase-locked loop bandwidth, faster phase error convergence speed and shorter locking time, but also have good anti-noise performance, and are described in detail below.
Referring to the above steps, in step S110, a first current control signal is generated through a first loop based on a comparison result between a first digital signal and a reference digital signal, and a first voltage controlled oscillator included in the first loop is controlled to generate an output digital signal based on the first current control signal. The first digital signal is obtained by frequency division of the output digital signal. Thus, with the first loop, a feedback mechanism is constructed that can generate a first current control signal based on a comparison between the first digital signal and the reference digital signal to thereby control the first voltage controlled oscillator to generate an output digital signal. When the first loop enters the locking state, the frequency of the first digital signal and the phase difference of the reference digital signal are the same, and the phase difference is also within a certain range, namely the convergence of the phase error of the first digital signal relative to the reference digital signal is realized. In step S120, a phase difference between the first digital signal and the reference digital signal is determined based on the comparison result, and a first parallel path is selectively connected or disconnected based on the phase difference. Wherein when the first parallel path is communicated, the first parallel path generates a second current control signal based on the comparison result and the second current control signal is superimposed to the first current control signal, a loop bandwidth of the first loop when the first parallel path is communicated being greater than a loop bandwidth of the first loop when the first parallel path is disconnected. Here, the second current control signal generated by the first parallel path is superimposed on the first current control signal, thereby controlling the first voltage controlled oscillator to generate an output digital signal. Thus, when the first parallel path is connected, the second current control signal generated by the first parallel path based on the comparison result is superimposed on the first current control signal, and the first current control signal is generated based on the comparison result between the first digital signal and the reference digital signal through the first loop, as mentioned above. Thus, when the first parallel path is connected, generating, by the first loop, a first current control signal based on a comparison result between the first digital signal and the reference digital signal; and generating, by the first parallel path, a second current control signal based on a comparison result between the first digital signal and the reference digital signal; the second current control signal is superimposed to the first current control signal to control the first voltage controlled oscillator to generate an output digital signal. This means that when the first parallel path is connected, the first parallel path provides an additional feedback mechanism on the basis of the feedback mechanism provided by the first loop, and that the two feedback mechanisms are in parallel relation, i.e. the finally generated current control signals are superimposed together for influencing the output digital signal generated by the first voltage controlled oscillator. And, the loop bandwidth of the first loop when the first parallel path is connected is greater than the loop bandwidth of the first loop when the first parallel path is disconnected. The first loop may be regarded as a multi-stage system, the locking time of which is mainly determined by the bandwidth of the multi-stage system, and through the first parallel path, the multi-stage system corresponding to the first loop is optimized, which is equivalent to increasing the loop bandwidth, that is, increasing the frequency range capable of being locked through the first loop, thereby improving the convergence speed of the phase error, reducing the locking time, and contributing to quick response and cost reduction. Further, the first parallel path is connected or disconnected, that is, the first parallel path is selectively connected or disconnected, so that the feedback mechanism of the first loop is not affected, and the data transmission process of the first loop is not changed; the effect of the first parallel path on the first loop is achieved by superimposing the second current control signal to the first current control signal. Therefore, when the first parallel path is communicated, the loop parameters of the multi-order system corresponding to the first loop are equivalently adjusted, so that the loop bandwidth of the first loop when the first parallel path is communicated is larger than the loop bandwidth of the first loop when the first parallel path is disconnected; when the first parallel path is disconnected, the switching to the multi-stage system of the first loop is meant, so that the first parallel path does not disturb the hierarchical structure of the original circuit and does not increase the hardware overhead of the original circuit. Further, the first parallel passage is selectively connected or disconnected based on the phase difference. This means that when the phase difference is smaller than a certain value or falls within a certain range, the first parallel path may be disconnected, which is equivalent to reducing the loop bandwidth, so that the noise immunity of the system may be improved. In addition, through the optimization design of the first parallel path, the response speed of the system can be increased, meanwhile, each pole and each zero point of the original system can be increased in equal proportion (for example, the loop parameters of the first parallel path can be designed by referring to the loop parameters, pole distribution and zero point distribution of the multi-order system corresponding to the first loop), so that the stability of the system is maintained. In summary, the digital signal processing method shown in fig. 1 improves the convergence speed of the phase error, reduces the locking time, is conducive to quick response and cost reduction by selectively connecting or disconnecting the first parallel path, has good anti-noise performance, and does not disturb the hierarchical structure of the original circuit or increase the hardware overhead of the original circuit.
In a possible implementation manner, the first loop includes a first charge pump and a first loop filter, the comparison result is input to the first charge pump, and the output of the first charge pump is filtered by the first loop filter to obtain the first current control signal. In some embodiments, the first loop further comprises a first phase frequency detector for receiving the first digital signal and the reference digital signal and generating the comparison between the first digital signal and the reference digital signal, the first voltage controlled oscillator for generating the output digital signal based on the first current control signal. Thus, with the first loop, a feedback mechanism is constructed that can generate a first current control signal based on a comparison between the first digital signal and the reference digital signal to thereby control the first voltage controlled oscillator to generate an output digital signal.
In one possible embodiment, the first parallel path includes a first switch, wherein the first switch is closed when the first parallel path is communicated based on the phase difference, and the first switch is opened when the first parallel path is opened based on the phase difference. The first parallel path further comprises a second charge pump and a second loop filter, when the first parallel path is communicated, the comparison result is input to the second charge pump, the output of the second charge pump is filtered by the second loop filter to obtain the second current control signal, and the first switch is connected with the second charge pump and the second loop filter in series. In this way, with the first parallel path, a feedback mechanism is constructed that can generate a second current control signal based on a result of comparison between a first digital signal and a reference digital signal, and the second current control signal is superimposed to the first current control signal. Selective connection or disconnection of the first parallel path based on the phase difference is achieved by the first switch.
In one possible embodiment, the first parallel path is disconnected when the phase difference is less than a first phase difference threshold, and the first parallel path is connected when the phase difference is greater than the first phase difference threshold. Therefore, when the phase difference is smaller than a certain value or falls within a certain range, the first parallel path can be disconnected by utilizing the first phase difference threshold value, so that the loop bandwidth is equivalently reduced, and the anti-noise performance of the system can be improved.
In one possible embodiment, when the first parallel path is opened, the first loop operates in a low bandwidth operation mode, and when the first parallel path is opened, the first loop operates in a high bandwidth mode, wherein a signal transmission path of the first loop in the low bandwidth operation mode coincides with a signal transmission path of the first loop in the high bandwidth operation mode. As such, the first parallel path is connected or disconnected, i.e. the first parallel path is selectively connected or disconnected, meaning that the first loop is switched to operate in a low bandwidth operation mode or a high bandwidth operation mode. The first parallel communication path is communicated or disconnected, so that a feedback mechanism of the first loop is not influenced, and the data transmission process of the first loop is not changed; the effect of the first parallel path on the first loop is achieved by superimposing the second current control signal to the first current control signal. Therefore, when the first parallel path is communicated, the loop parameters of the multi-order system corresponding to the first loop are equivalently adjusted, so that the loop bandwidth of the first loop when the first parallel path is communicated is larger than the loop bandwidth of the first loop when the first parallel path is disconnected; when the first parallel path is disconnected, the switching to the multi-stage system of the first loop is meant, so that the first parallel path does not disturb the hierarchical structure of the original circuit and does not increase the hardware overhead of the original circuit. Therefore, the first parallel path is selectively connected or disconnected, so that the first loop can be switched between the low-bandwidth working mode and the high-bandwidth mode, and the switching of the working mode of the first loop does not influence the signal transmission path of the first loop, so that the hardware cost is greatly reduced. In some embodiments, the greater the loop bandwidth of the first loop, the higher the convergence rate of the phase error of the first loop, and the distribution of the zero poles of the loop filter transfer function of the first loop in the low bandwidth mode of operation relative to the loop bandwidth of the first loop in the low bandwidth mode of operation is consistent with the distribution of the zero poles of the loop filter transfer function of the first loop in the high bandwidth mode of operation relative to the loop bandwidth of the first loop in the high bandwidth mode of operation. In this way, by optimally designing the first parallel path, the system response speed can be increased while the poles and zeros of the original system are increased in equal proportion (for example, the loop parameters of the first parallel path can be designed with reference to the loop parameters, pole distribution and zero distribution of the multi-order system corresponding to the first loop), so that the system stability can be maintained. Wherein when the first loop is switched from the low bandwidth operating mode to the high bandwidth operating mode, or from the high bandwidth operating mode to the low bandwidth operating mode, the loop filter transfer function of the first loop maintains a constant pole zero distribution relative to the loop bandwidth in the current operating mode. The loop bandwidth of the first loop in the low-bandwidth operation mode is smaller than the loop bandwidth of the first loop in the high-bandwidth operation mode, so that the loop bandwidth of the first loop can be increased or decreased as the operation mode is switched, and thus the zero and the pole of the loop filter transfer function of the first loop can be changed in equal proportion according to the new loop bandwidth, so that the relative positions (or relative proportions) of the zero and the pole under the new loop bandwidth are consistent with the phase positions (or relative proportions) of the zero and the pole under the old loop bandwidth. In some embodiments, the first parallel path further comprises a phase lock detection module for: and determining the phase difference based on the comparison result, judging whether the phase difference is within a preset phase difference range, if so, disconnecting the first parallel passage, and if not, connecting the first parallel passage. In this way, the phase lock detection module is utilized to determine the phase difference and further increase the convergence speed of the phase error.
In one possible implementation manner, the digital signal processing method further includes: and selectively switching on or off a second parallel path based on the frequency difference, wherein when the second parallel path is switched on, the second parallel path generates a third current control signal based on the frequency difference and the third current control signal is superimposed to the first current control signal, the first loop together with the second parallel path forming a frequency locked loop when the second parallel path is switched on. As such, the second parallel path is selectively turned on or off based on the frequency difference, and a third current control signal is generated based on the frequency difference through the second parallel path and is superimposed to the first current control signal. In this way, with the second parallel path, a feedback mechanism based on the frequency difference is constructed, and by superimposing the third current control signal to the first current control signal, the effect on the first loop is exerted, without affecting the feedback mechanism of the first loop, nor changing the data transmission process of the first loop. The first loop and the second parallel path form a frequency locking loop together when the second parallel path is communicated, so that frequency locking can be achieved quickly by combining the first loop and the second parallel path, and frequency difference convergence and response speed improvement are facilitated. In some embodiments, the second parallel path includes a frequency difference measurement module, a voltage controlled current source, a capacitor, and a second switch, wherein the frequency difference measurement module is configured to receive the first digital signal and the reference digital signal and determine the frequency difference, the frequency difference is input to the voltage controlled current source, and an output of the voltage controlled current source obtains the third current control signal via the capacitor. In this way, a feedback mechanism based on the frequency difference is constructed by using the modules and devices included in the second parallel path. In some embodiments, the second parallel path is communicated when the frequency difference exceeds a first frequency difference range; disconnecting the second parallel path and connecting the first parallel path when the frequency difference is within the first frequency difference range and the phase difference exceeds a first phase difference range; when the frequency difference is within the first frequency difference range and the phase difference is within the first phase difference range, the second parallel path is disconnected and the first parallel path is disconnected. In this way, with the first parallel passage and the second parallel passage, a multi-stage locking operation can be achieved. When the frequency difference exceeds the first frequency difference range, the second parallel passage is communicated, so that the frequency acceleration locking operation is realized; when the frequency difference is within the first frequency difference range and the phase difference exceeds a first phase difference range, disconnecting the second parallel path and connecting the first parallel path, thereby realizing a phase acceleration locking operation; when the frequency difference is within the first frequency difference range and the phase difference is within the first phase difference range, the second parallel passage is disconnected and the first parallel passage is disconnected, so that normal bandwidth locking operation is realized, and the anti-noise performance of the system can be effectively improved. Therefore, by utilizing the connection and disconnection of the first parallel passage and the second parallel passage and making judgment based on the frequency difference and the phase difference, the locking operation of stages and multiple stages can be realized, so that the frequency acceleration locking, the phase acceleration locking and the normal bandwidth locking are realized, the response speed of the system is further improved, and the locking time is reduced. In some embodiments, the digital signal processing method is for a first frequency-lock phase-lock operation of a phase-lock loop circuit, the first frequency-lock phase-lock operation comprising: the first parallel path is disconnected and the second parallel path is connected until the frequency difference is within the first frequency difference range, then the first parallel path is connected and the second parallel path is disconnected until the phase difference is within the first phase difference range, and then the first parallel path is disconnected and the second parallel path is disconnected. Thus, frequency acceleration locking is facilitated by the first frequency-locking phase-locking operation. In some embodiments, the digital signal processing method is for a second frequency-lock phase-lock operation of the phase-locked loop circuit, the second frequency-lock phase-lock operation comprising: and connecting the first parallel path and disconnecting the second parallel path until the phase difference is within the first phase difference range, disconnecting the first parallel path and disconnecting the second parallel path, wherein the phase-locked loop circuit selects the first frequency-locking operation or the second frequency-locking operation based on an initial process angle condition and an initial frequency difference. Thus, by the second frequency-locking phase-locking operation, the phase acceleration locking is facilitated. In addition, considering the influence of the initial frequency difference, that is, the difference between the initial static frequency (or natural oscillation frequency) of the first voltage-controlled oscillator and the frequency of the reference digital signal, and considering the influence of the initial process angle condition, for example, the chip performance difference under different process-voltage-temperature combinations, the selection of the first frequency-locking phase-locking operation or the second frequency-locking phase-locking operation according to different initial states of the circuit can be realized, so that the response speed is further improved and the locking time is reduced. For example, in some application scenarios, the initial frequency difference may be larger, which means that the difference between the initial static frequency (or natural oscillation frequency) of the first voltage controlled oscillator and the frequency of the reference digital signal is larger, which is suitable for implementing the first frequency-locking and phase-locking operation to achieve frequency-accelerated locking. In addition, different process-voltage-temperature combinations can correspond to different states of the chip or to different simulation environments, so that corresponding frequency and phase locking operation can be adopted to dynamically adjust simulation time, and simulation efficiency is improved.
Fig. 2 is a schematic diagram of a digital signal processing system according to an embodiment of the present application. The digital signal processing system includes a first loop 210 and a first parallel path 212. The first loop 210 is configured to: a first current control signal is generated based on a comparison result between the first digital signal 203 and the reference digital signal 202, and an output digital signal 204 is generated based on a first voltage controlled oscillator 226 included in the first loop 210 controlled by the first current control signal, the first digital signal 203 being obtained by dividing the output digital signal 204. The first parallel path 212 is selectively connected or disconnected based on a phase difference between the first digital signal 203 and the reference digital signal 202, the phase difference being determined based on the comparison result. When the first parallel path 212 is connected, the first parallel path 212 generates a second current control signal based on the comparison result and the second current control signal is superimposed on the first current control signal, and a loop bandwidth of the first loop 210 when the first parallel path 212 is connected is greater than a loop bandwidth of the first loop 210 when the first parallel path 212 is disconnected. The first loop 210 includes a first charge pump 222 and a first loop filter 224, the comparison result is input to the first charge pump 222, and the output of the first charge pump 222 is filtered by the first loop filter 224 to obtain the first current control signal. The first loop 210 further comprises a first phase frequency detector 220, the first phase frequency detector 220 being configured to receive the first digital signal 203 and the reference digital signal 202 and to generate the comparison result between the first digital signal 203 and the reference digital signal 202, the first voltage controlled oscillator 226 being configured to generate the output digital signal 204 based on the first current control signal. The first parallel path 212 includes a first switch 234. Wherein the first switch 234 is closed when the first parallel path 212 is communicated based on the phase difference, and the first switch 234 is opened when the first parallel path 212 is opened based on the phase difference. The first parallel path 212 further includes a second charge pump 230 and a second loop filter 232, when the first parallel path 212 is connected, the comparison result is input to the second charge pump 230, the output of the second charge pump 230 is filtered by the second loop filter 232 to obtain the second current control signal, and the first switch 234 is connected in series with the second charge pump 230 and the second loop filter 232. The first parallel path 212 further includes a phase lock detection module 236. The phase lock detection module 236 is configured to: and determining the phase difference based on the comparison result, judging whether the phase difference is within a preset phase difference range, if so, disconnecting the first parallel passage 212, and if not, connecting the first parallel passage 212. Also shown in fig. 2 are a first frequency divider 290 and a second frequency divider 292. The first frequency divider 290 is configured to divide the output digital signal 204 to obtain the first digital signal 203. The second divider 292 is configured to divide the output digital signal 204 generated by the first voltage controlled oscillator 226.
The digital signal processing system shown in fig. 2 improves the convergence speed of the phase error, reduces the locking time, is conducive to quick response and cost reduction by selectively connecting or disconnecting the first parallel path 212, has good noise immunity, and does not disturb the hierarchical structure of the original circuit or increase the hardware overhead of the original circuit. Also, as can be seen from fig. 2, the first parallel communication path 212 is connected or disconnected, so that the feedback mechanism of the first loop 210 is not affected, and the data transmission process of the first loop 210 is not changed; the first parallel path 212 affects the first loop 210 by superimposing the second current control signal onto the first current control signal. Therefore, when the first parallel path 212 is connected, it is equivalent to adjusting the loop parameters of the multi-order system corresponding to the first loop 210, so that the loop bandwidth of the first loop 210 when the first parallel path 212 is connected is greater than the loop bandwidth of the first loop 210 when the first parallel path 212 is disconnected; when the first parallel path 212 is disconnected, it means that the multi-stage system of the first loop 210 is switched, so that the first parallel path 212 does not disturb the hierarchical structure of the original circuit and does not increase the hardware overhead of the original circuit. Therefore, by selectively connecting or disconnecting the first parallel path 212, the first loop 210 can be switched between the low-bandwidth operation mode and the high-bandwidth operation mode, and the switching of the operation mode of the first loop 210 does not affect the signal transmission path of the first loop 210, so that the hardware overhead is greatly reduced.
Fig. 3 is a schematic diagram of a digital signal processing system according to another embodiment of the present application. Fig. 3 differs from fig. 2 in that the digital signal processing system shown in fig. 3 further comprises a second parallel path 214. In addition, for the elements and related details in fig. 3 repeated with fig. 2, reference may be made to the above-mentioned embodiments, and the details are not repeated here. The second parallel path 214 is for: a frequency difference between the first digital signal 203 and the reference digital signal 202 is determined, and a second parallel path 214 is selectively turned on or off based on the frequency difference. When the second parallel path 214 is connected, the second parallel path 214 generates a third current control signal based on the frequency difference and the third current control signal is superimposed to the first current control signal, the first loop 210 together with the second parallel path 214 forming a frequency locked loop when the second parallel path 214 is connected. The second parallel path 214 includes a frequency difference measurement module 250, a voltage controlled current source 252, a capacitor 254, and a second switch 256. The frequency difference measurement module 250 is configured to receive the first digital signal 203 and the reference digital signal 202 and determine the frequency difference, where the frequency difference is input to the voltage-controlled current source 252, and the output of the voltage-controlled current source 252 obtains the third current control signal via the capacitor 254. The second switch 256 is used to connect or disconnect the second parallel path 214. The frequency difference determined by the frequency difference measurement module 250 may be used to control the turning off and on of the second switch 256 to selectively turn on or off the second parallel path 214 based on the frequency difference. When the second parallel path 214 is connected based on the frequency difference, the second switch 256 is closed; when the second parallel path 214 is opened based on the frequency difference, the second switch 256 is opened. It can be seen that the frequency difference measurement module 250, the voltage controlled current source 252 and the second switch 256 are connected in series.
The digital signal processing system shown in fig. 3 improves the convergence speed of the phase error, reduces the locking time, is conducive to quick response and cost reduction by selectively connecting or disconnecting the first parallel path 212, has good noise immunity, and does not disturb the hierarchical structure of the original circuit or increase the hardware overhead of the original circuit. Also, the digital signal processing system shown in fig. 3 constructs a feedback mechanism based on a frequency difference using the second parallel path 214, and by superimposing the third current control signal to the first current control signal to exert an influence on the first loop 210, the feedback mechanism of the first loop 210 is not influenced, and the data transmission process of the first loop 210 is not changed. By utilizing the connection and disconnection of the first parallel path 212 and the second parallel path 214, and making a judgment based on the frequency difference and the phase difference, a staged and multistage locking operation can be realized, so that frequency acceleration locking, phase acceleration locking and normal bandwidth locking are realized, the response speed of the system is further improved, and the locking time is reduced.
Fig. 4 is a schematic structural diagram of a computing device according to an embodiment of the present application, where the computing device 400 includes: one or more processors 410, a communication interface 420, and a memory 430. The processor 410, communication interface 420, and memory 430 are interconnected by a bus 440. Optionally, the computing device 400 may further include an input/output interface 450, where the input/output interface 450 is connected to an input/output device for receiving parameters set by a user, etc. The computing device 400 can be used to implement some or all of the functionality of the device embodiments or system embodiments of the present application described above; the processor 410 can also be used to implement some or all of the operational steps of the method embodiments described above in connection with the embodiments of the present application. For example, specific implementations of the computing device 400 performing various operations may refer to specific details in the above-described embodiments, such as the processor 410 being configured to perform some or all of the steps of the above-described method embodiments or some or all of the operations of the above-described method embodiments. For another example, in an embodiment of the present application, the computing device 400 may be used to implement some or all of the functionality of one or more components of the apparatus embodiments described above, and the communication interface 420 may be used in particular for communication functions and the like necessary to implement the functionality of those apparatuses, components, and the processor 410 may be used in particular for processing functions and the like necessary to implement the functionality of those apparatuses, components.
It should be appreciated that the computing device 400 of fig. 4 may include one or more processors 410, and that the processors 410 may cooperatively provide processing power in a parallelized connection, a serialized connection, a serial-parallel connection, or any connection, or that the processors 410 may constitute a processor sequence or processor array, or that the processors 410 may be separated into primary and secondary processors, or that the processors 410 may have different architectures such as heterogeneous computing architectures. In addition, the computing device 400 shown in FIG. 4, the associated structural and functional descriptions are exemplary and not limiting. In some example embodiments, computing device 400 may include more or fewer components than shown in fig. 4, or combine certain components, or split certain components, or have a different arrangement of components.
The processor 410 may have various specific implementations, for example, the processor 410 may include one or more of a central processing unit (central processing unit, CPU), a graphics processor (graphic processing unit, GPU), a neural network processor (neural-network processing unit, NPU), a tensor processor (tensor processing unit, TPU), or a data processor (data processing unit, DPU), and the embodiment of the present application is not limited in particular. Processor 410 may also be a single-core processor or a multi-core processor. Processor 410 may be comprised of a combination of a CPU and hardware chips. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof. The processor 410 may also be implemented solely with logic devices incorporating processing logic, such as an FPGA or digital signal processor (digital signal processor, DSP) or the like. The communication interface 420 may be a wired interface, which may be an ethernet interface, a local area network (local interconnect network, LIN), etc., or a wireless interface, which may be a cellular network interface, or use a wireless local area network interface, etc., for communicating with other modules or devices.
The memory 430 may be a nonvolatile memory such as a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Memory 430 may also be volatile memory, which may be random access memory (random access memory, RAM) used as external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). Memory 430 may also be used to store program code and data such that processor 410 invokes the program code stored in memory 430 to perform some or all of the operational steps of the method embodiments described above, or to perform corresponding functions in the apparatus embodiments described above. Moreover, computing device 400 may contain more or fewer components than shown in FIG. 4, or may have a different configuration of components.
The bus 440 may be a peripheral component interconnect express (peripheral component interconnect express, PCIe) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, a unified bus (Ubus or UB), a computer quick link (compute express link, CXL), a cache coherent interconnect protocol (cache coherent interconnect for accelerators, CCIX), or the like. The bus 440 may be divided into an address bus, a data bus, a control bus, and the like. The bus 440 may include a power bus, a control bus, a status signal bus, and the like in addition to a data bus. But is shown with only one bold line in fig. 4 for clarity of illustration, but does not represent only one bus or one type of bus.
The method and the device provided by the embodiment of the application are based on the same inventive concept, and because the principle of solving the problem by the method and the device is similar, the embodiment, the implementation, the example or the implementation of the method and the device can be mutually referred, and the repetition is not repeated. Embodiments of the present application also provide a system comprising a plurality of computing devices, each of which may be structured as described above. The functions or operations that may be implemented by the system may refer to specific implementation steps in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein.
Embodiments of the present application also provide a computer-readable storage medium having stored therein computer instructions which, when executed on a computer device (e.g., one or more processors), implement the method steps of the method embodiments described above. The specific implementation of the processor of the computer readable storage medium in executing the above method steps may refer to specific operations described in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein again.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. The application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Embodiments of the application may be implemented, in whole or in part, in software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. The computer program product includes one or more computer instructions. When loaded or executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc. that contain one or more collections of available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, tape), optical media, or semiconductor media. The semiconductor medium may be a solid state disk, or may be a random access memory, flash memory, read only memory, erasable programmable read only memory, electrically erasable programmable read only memory, register, or any other form of suitable storage medium.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. Each flow and/or block of the flowchart and/or block diagrams, and combinations of flows and/or blocks in the flowchart and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit or scope of the embodiments of the application. The steps in the method of the embodiment of the application can be sequentially adjusted, combined or deleted according to actual needs; the modules in the system of the embodiment of the application can be divided, combined or deleted according to actual needs. The present application is also intended to include such modifications and alterations if they come within the scope of the claims and the equivalents thereof.
Claims (15)
1. A digital signal processing method, characterized in that the digital signal processing method comprises:
generating a first current control signal based on a comparison result between a first digital signal and a reference digital signal through a first loop, and controlling a first voltage-controlled oscillator included in the first loop to generate an output digital signal based on the first current control signal, wherein the first digital signal is obtained by frequency division of the output digital signal;
And selectively connecting or disconnecting a first parallel path based on the phase difference, wherein when the first parallel path is connected, the first parallel path generates a second current control signal based on the comparison result and the second current control signal is superimposed to the first current control signal, and a loop bandwidth of the first loop when the first parallel path is connected is greater than a loop bandwidth of the first loop when the first parallel path is disconnected.
2. The digital signal processing method according to claim 1, wherein the first loop includes a first charge pump and a first loop filter, the comparison result is input to the first charge pump, and an output of the first charge pump is filtered by the first loop filter to obtain the first current control signal.
3. The digital signal processing method of claim 2, wherein the first loop further comprises a first phase-frequency detector for receiving the first digital signal and the reference digital signal and generating the comparison between the first digital signal and the reference digital signal, and wherein the first voltage-controlled oscillator is for generating the output digital signal based on the first current control signal.
4. The digital signal processing method according to claim 1, wherein the first parallel path includes a first switch, wherein the first switch is closed when the first parallel path is communicated based on the phase difference, and wherein the first switch is opened when the first parallel path is opened based on the phase difference.
5. The digital signal processing method according to claim 4, wherein the first parallel path further includes a second charge pump and a second loop filter, the comparison result is input to the second charge pump when the first parallel path is communicated, the output of the second charge pump is filtered by the second loop filter to obtain the second current control signal, and the first switch is connected in series with the second charge pump and the second loop filter.
6. The digital signal processing method according to claim 1, wherein the first parallel path is disconnected when the phase difference is smaller than a first phase difference threshold, and the first parallel path is connected when the phase difference is larger than the first phase difference threshold.
7. The digital signal processing method according to claim 1, wherein the first loop circuit operates in a low bandwidth operation mode when the first parallel path is opened, and operates in a high bandwidth mode when the first parallel path is closed, wherein a signal transmission path of the first loop circuit in the low bandwidth operation mode coincides with a signal transmission path of the first loop circuit in the high bandwidth operation mode.
8. The digital signal processing method according to claim 7, wherein the larger the loop bandwidth of the first loop is, the higher the phase error of the first loop is subjected to convergence speed, and the distribution of the zero point pole of the loop filter transfer function of the first loop in the low bandwidth operation mode with respect to the loop bandwidth of the first loop in the high bandwidth operation mode is identical to the distribution of the zero point pole of the loop filter transfer function of the first loop in the high bandwidth operation mode with respect to the loop bandwidth of the first loop in the low bandwidth operation mode.
9. The digital signal processing method of claim 7, wherein the first parallel path further comprises a phase lock detection module for: and determining the phase difference based on the comparison result, judging whether the phase difference is within a preset phase difference range, if so, disconnecting the first parallel passage, and if not, connecting the first parallel passage.
10. The digital signal processing method according to claim 1, characterized in that the digital signal processing method further comprises:
And selectively switching on or off a second parallel path based on the frequency difference, wherein when the second parallel path is switched on, the second parallel path generates a third current control signal based on the frequency difference and the third current control signal is superimposed to the first current control signal, the first loop together with the second parallel path forming a frequency locked loop when the second parallel path is switched on.
11. The digital signal processing method of claim 10, wherein the second parallel path includes a frequency difference measurement module, a voltage controlled current source, a capacitor, and a second switch, wherein the frequency difference measurement module is configured to receive the first digital signal and the reference digital signal and determine the frequency difference, the frequency difference is input to the voltage controlled current source, and an output of the voltage controlled current source is provided with the third current control signal via the capacitor.
12. The method for digital signal processing according to claim 10, wherein,
when the frequency difference exceeds a first frequency difference range, the second parallel path is communicated;
Disconnecting the second parallel path and connecting the first parallel path when the frequency difference is within the first frequency difference range and the phase difference exceeds a first phase difference range;
when the frequency difference is within the first frequency difference range and the phase difference is within the first phase difference range, the second parallel path is disconnected and the first parallel path is disconnected.
13. The digital signal processing method of claim 12, wherein the digital signal processing method is used for a first frequency-locking phase-locking operation of a phase-locked loop circuit, the first frequency-locking phase-locking operation comprising: the first parallel path is disconnected and the second parallel path is connected until the frequency difference is within the first frequency difference range, then the first parallel path is connected and the second parallel path is disconnected until the phase difference is within the first phase difference range, and then the first parallel path is disconnected and the second parallel path is disconnected.
14. The digital signal processing method of claim 13, wherein the digital signal processing method is used for a second frequency-locking phase-locking operation of the phase-locked loop circuit, the second frequency-locking phase-locking operation comprising: and connecting the first parallel path and disconnecting the second parallel path until the phase difference is within the first phase difference range, disconnecting the first parallel path and disconnecting the second parallel path, wherein the phase-locked loop circuit selects the first frequency-locking operation or the second frequency-locking operation based on an initial process angle condition and an initial frequency difference.
15. A digital signal processing system, the digital signal processing system comprising:
a first loop, wherein the first loop is configured to: generating a first current control signal based on a comparison result between a first digital signal and a reference digital signal, and controlling a first voltage-controlled oscillator included in the first loop to generate an output digital signal based on the first current control signal, wherein the first digital signal is obtained by frequency division of the output digital signal;
a first parallel path, wherein the first parallel path is selectively connected or disconnected based on a phase difference between the first digital signal and the reference digital signal, the phase difference being determined based on the comparison result, the first parallel path generating a second current control signal based on the comparison result and the second current control signal being superimposed to the first current control signal when the first parallel path is connected, a loop bandwidth of the first loop being greater than a loop bandwidth of the first loop when the first parallel path is disconnected.
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