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CN117097307A - Loop oscillator circuit - Google Patents

Loop oscillator circuit Download PDF

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Publication number
CN117097307A
CN117097307A CN202310879135.9A CN202310879135A CN117097307A CN 117097307 A CN117097307 A CN 117097307A CN 202310879135 A CN202310879135 A CN 202310879135A CN 117097307 A CN117097307 A CN 117097307A
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CN
China
Prior art keywords
unit
trigger
current
circuit
loop
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Granted
Application number
CN202310879135.9A
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Chinese (zh)
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CN117097307B (en
Inventor
冯伟
王彦浩
王本川
黄强
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Beijing Thinking Semiconductor Technology Co ltd
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Beijing Thinking Semiconductor Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The present disclosure relates to a loop oscillator circuit comprising: the frequency detection unit is connected with the loop oscillation unit and is used for collecting the current oscillation frequency of the loop oscillation unit and converting the current oscillation frequency into a voltage signal serving as a voltage control signal for current calibration; the correction unit is respectively connected with the frequency detection unit and the loop oscillation unit, and comprises a plurality of parallel current branches which are connected with the loop oscillation unit in an on-off manner, and is used for determining a target current branch which is communicated with the loop oscillation unit in the plurality of parallel current branches according to the magnitude relation between the voltage control signal and the first reference voltage, and controlling the conduction of the target current branch so as to enable the target branch current in the target current branch to be input into the loop oscillation unit; the loop oscillation unit is used for generating the oscillation frequency calibrated at this time according to the input target branch current. Thus, the precision of the loop oscillator is improved on the basis of not increasing the design cost, the chip area and the power consumption.

Description

Loop oscillator circuit
Technical Field
The present disclosure relates to the technical field of circuit components, and in particular, to a loop oscillator circuit.
Background
In order to meet the design requirements of low power consumption and low cost in the photovoltaic power line carrier chip, a precise clock signal with low power consumption is required, but the oscillation frequency of the RC loop oscillator inside the common chip is easily affected by the Process (Process), voltage (Voltage) and Temperature (Temperature), so the accuracy of the oscillation frequency is not high. In some applications requiring high precision oscillation frequencies, it is difficult to meet the high precision design requirements due to limitations in the number of adjustment bits and constraints in adjustment costs, even with manual modulation. If an external crystal oscillator is adopted, on one hand, the price of the external oscillator is higher, the extra cost is increased, and on the other hand, a phase-locked loop module is required to be added in the chip, so that the chip area is increased, the power consumption of the chip is increased, and the overall design cost of the oscillator is further increased.
Disclosure of Invention
It is an object of the present disclosure to provide a loop oscillator circuit to solve the problems in the related art.
To achieve the above object, the present disclosure provides a loop oscillator circuit including:
the frequency detection unit is connected with the loop oscillation unit and is used for collecting the current oscillation frequency of the loop oscillation unit and converting the current oscillation frequency into a voltage signal to be used as a voltage control signal for the current calibration, wherein the current oscillation frequency is the oscillation frequency of the loop oscillation unit corrected last time;
The correction unit is respectively connected with the frequency detection unit and the loop oscillation unit, and comprises a plurality of parallel current branches which are connected with the loop oscillation unit in an on-off mode, and is used for determining a target current branch which is communicated with the loop oscillation unit in the plurality of parallel current branches according to the magnitude relation between the voltage control signal and the first reference voltage, and controlling the conduction of the target current branch so as to enable the target branch current in the target current branch to be input into the loop oscillation unit;
and the loop oscillation unit is used for generating the oscillation frequency calibrated at this time according to the input target branch current.
Optionally, the frequency detection unit includes: the switching capacitor comprises an equivalent resistance circuit of a switching capacitor, a first operational amplifier, a first MOS tube and a voltage generating circuit;
the equivalent resistance circuit of the switch capacitor comprises a pair of complementary switches and a first capacitor, and the loop oscillation unit is connected with the complementary switches to control the closing of the complementary switches according to the current oscillation frequency of the loop oscillation unit so as to obtain the equivalent resistance value of the first capacitor;
the positive input end of the first operational amplifier is used for inputting a second reference voltage, the negative input end of the first operational amplifier is connected with the first end of the first MOS tube and the first end of the equivalent resistance circuit of the switch capacitor, the output end of the first operational amplifier is connected with the second end of the first MOS tube, and the second end of the equivalent resistance circuit of the switch capacitor is grounded;
The third end of the first MOS tube is connected with the voltage generation circuit and is used for inputting an equivalent current value of an equivalent resistance circuit of the switch capacitor into the voltage generation circuit;
the voltage generation circuit is used for generating a voltage control signal calibrated at this time according to the equivalent current value.
Optionally, the first MOS transistor is a first NMOS transistor; the voltage generation circuit comprises a first PMOS tube, a second PMOS tube and a first resistor;
the drain electrode of the first PMOS tube is connected with the grid electrode and is respectively connected with the drain electrode of the first NMOS tube, the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with a power supply, and the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube;
the drain electrode of the second PMOS tube is connected with the grid electrode and is respectively connected with the first end of the first resistor and the drain electrode of the first NMOS tube, and the second end of the first resistor is grounded;
the correction unit is connected with the first end of the first resistor.
Optionally, the loop oscillator circuit is an on-chip loop oscillator circuit;
the first resistor is an off-chip resistor and/or the first capacitor is an off-chip capacitor.
Optionally, the frequency detection unit further includes: and the second reference voltage selection unit is connected with the positive input end of the first operational amplifier and is used for inputting the second reference voltage to the positive input end of the first operational amplifier.
Optionally, the correction unit includes a voltage comparison unit, a logic control unit, and a current adjustment unit;
the voltage comparison unit is connected with the frequency detection unit and is used for comparing the magnitude relation between the voltage control signal and the first reference voltage and outputting a comparison result;
the current regulation unit comprises an initial current generation circuit and a plurality of parallel current branches, wherein the initial current generation circuit is connected with the plurality of parallel current branches in parallel;
the logic control unit is respectively connected with the voltage comparison unit and the plurality of parallel current branches, and is used for determining a target current branch communicated with the loop oscillation unit in the plurality of parallel current branches according to the comparison result output by the voltage comparison unit and generating a conduction control signal, wherein the conduction control signal is used for controlling the conduction of the target current branch.
Optionally, the logic control unit includes a logic control circuit and a clock generation circuit;
the logic control circuit comprises a JK trigger array, a first AND gate circuit and a D trigger array, wherein the JK trigger array comprises M JK triggers, the D trigger array comprises M+3 first D triggers, the number of the first AND gate circuits is M, and M is an integer larger than 1;
The output end Q of the ith first D trigger is connected with the data input end D of the ith-1 first D trigger, i is an integer which sequentially takes values between M+1 and 1, the data input ends D of the Mth+1 first D trigger and the Mth+3 first D trigger are grounded, the data input end D of the Mth+2 first D trigger is connected with the output end Q of the first D trigger, the output end Q of the Mth+2 first D trigger is connected with the clock input end CK of the Mth+3 first D trigger, the clock input ends CK of the first D trigger to the Mth+2 first D trigger are used for inputting clock signals generated by the clock generating circuit, the reset ends of the first D trigger to the Mth first D trigger and the Mth+2 first D trigger are used for inputting frequency correction control signals, and the output ends of the Mth+1 first D trigger and the Mth+3 first D trigger are used for setting the frequency correction signals;
the first input end of the jth first and gate circuit is connected with the output end of the voltage comparing unit 301, the second input end of the jth first and gate circuit is connected with the output end Q of the jth first D flip-flop, the output end of the jth first and gate circuit is connected with the K end of the jth JK flip-flop, the J end of the jth JK flip-flop is connected with the data input end D of the jth first D flip-flop, wherein the value range of J is [1, m ];
The reset end of each JK trigger is used for inputting a frequency correction control signal, the clock input end CK of each JK trigger is used for inputting a clock signal generated by the clock generating circuit, and the conduction control signal comprises a signal output by the output end Q of each JK trigger.
Optionally, the clock generating circuit comprises a second AND gate circuit, a second D trigger, a delay unit, an exclusive OR circuit and an inverter;
the first input end of the second AND gate circuit is connected with the output end Q of the M+3th first D trigger, the second input end of the second AND gate circuit is connected with the output end of the inverter, the output end of the second AND gate circuit is used for outputting a clock signal, and the output end of the second AND gate circuit is connected with the clock input end CK of the second D trigger;
the output end QN of the second D trigger is connected with the input end of the delay unit and the second input end of the exclusive-or circuit, the output end of the delay unit is respectively connected with the first input end of the exclusive-or circuit and the data input end D of the second D trigger, and the setting end of the second D trigger is used for inputting the frequency correction control signal;
the output end of the exclusive-or circuit is connected with the input end of the inverter.
Optionally, the initial current generation circuit includes: the second operational amplifier, the second NMOS tube, the second resistor, the third PMOS tube and the fourth PMOS tube;
the positive input end of the second operational amplifier is used for inputting a third reference voltage, the negative input end of the second operational amplifier is connected with the source electrode of the second NMOS tube and the first end of the second resistor, and the output end of the second operational amplifier is connected with the grid electrode of the second NMOS tube;
the source electrode of the second NMOS tube is connected with the first end of the second resistor, the second end of the second resistor is grounded, the drain electrode of the second NMOS tube is connected with the grid electrode and the drain electrode of the third PMOS tube and the grid electrode and the drain electrode of the fourth PMOS tube, the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the loop oscillation unit;
the current branches in parallel connection comprise M current branches, each current branch comprises a PMOS tube and a switch, the grid electrode of the PMOS in each current branch is connected with the grid electrode of the third PMOS tube, and the drain electrode of the PMOS tube in each current branch is connected with the loop oscillation unit through the switch in the current branch;
The switch in the jth current branch is connected with the output end Q of the jth JK trigger and is used for being controlled to be closed and opened by a signal output by the output end Q of the jth JK trigger.
Optionally, the voltage comparing unit includes a comparator and a first reference voltage selecting unit;
the positive input end of the comparator is used for inputting a voltage control signal, the negative input end of the comparator is connected with the first reference voltage selection unit and used for inputting a first reference voltage, and the output end of the comparator is connected with the logic control unit and used for outputting a comparison result to the logic control unit.
By adopting the technical scheme, the loop oscillator circuit comprises a correction unit, wherein the correction unit can determine a target current branch communicated with the loop oscillator unit in a plurality of parallel current branches according to the magnitude relation between the voltage control signal and the first reference voltage, and control the conduction of the target current branch so as to enable the target branch current in the target current branch to be input into the loop oscillator unit 20, and the loop oscillator unit 20 generates the current calibrated oscillation frequency according to the input target branch current. Therefore, the correction unit adjusts the oscillation frequency of the loop oscillation unit by adjusting the current input into the loop oscillation unit, the oscillation frequency of the loop oscillation unit can be quickly adjusted on the basis of not increasing the design cost, the chip area and the power consumption, the oscillation frequency precision of the loop oscillation unit can be further improved, and the precision of the loop oscillator is further improved.
Additional features and advantages of the present disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:
fig. 1 is a block diagram of a loop oscillator, according to an example embodiment.
Fig. 2 is a schematic diagram of a loop oscillator circuit, shown in accordance with an exemplary embodiment.
Fig. 3 is a schematic diagram of a logic control unit, according to an example embodiment.
Fig. 4 is a schematic diagram of a reference voltage selection unit according to an exemplary embodiment.
Detailed Description
Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the disclosure, are not intended to limit the disclosure.
It should be noted that, all actions for acquiring signals, information or data in the present disclosure are performed under the condition of conforming to the corresponding data protection rule policy of the country of the location and obtaining the authorization given by the owner of the corresponding device.
The present disclosure provides a loop oscillator circuit that corrects an oscillation frequency of a loop oscillator by a correction unit built in the loop oscillator circuit so that the loop oscillator outputs a high-precision oscillation frequency, and thus, can improve the precision of the oscillation frequency of the loop oscillator without increasing design cost, chip area, and power consumption.
Fig. 1 is a block diagram of a loop oscillator, according to an example embodiment. As shown in fig. 1, the loop oscillator includes a frequency detection unit 10, a loop oscillation unit 20, and a correction unit 30. The frequency detection unit 10 is connected to the loop oscillation unit 20, and is configured to collect a current oscillation frequency of the loop oscillation unit 20, and convert the current oscillation frequency into a voltage signal as a voltage control signal for current calibration, where the current oscillation frequency is an oscillation frequency of the loop oscillation unit 20 after the previous calibration.
The correction unit 30 is connected to the frequency detection unit 10 and the loop oscillation unit 20, and the correction unit 30 includes a plurality of parallel current branches connected to the loop oscillation unit 20 in an on-off manner. The correction unit 30 is configured to determine a target current branch connected to the loop oscillation unit 20 from a plurality of parallel current branches according to a magnitude relation between the voltage control signal and the first reference voltage, and control the target current branch to be turned on so that a target branch current in the target current branch is input to the loop oscillation unit 20.
The loop oscillation unit 20 is configured to generate the oscillation frequency calibrated at this time according to the input target branch current.
In the present disclosure, the oscillation frequency of the present calibration of the loop oscillation unit 20 can be obtained for each correction.
Further, the correction unit 30 corrects the oscillation frequency of the loop oscillation unit 20 means correcting the current value input to the loop oscillation unit 20, that is, correcting the power supply current of the loop oscillation unit 20. Illustratively, the correction unit 30 determines a target current branch to be connected to the loop oscillation unit 20 from a plurality of parallel current branches according to the magnitude relation between the voltage control signal and the first reference voltage, and further controls the target current branch to be turned on so that the target branch current of the target current branch is input to the loop oscillation unit 20.
For example, the corresponding relation between the voltage difference and the power supply current required by the loop oscillation unit 20 is preset, the correction unit 30 determines the power supply current required by the loop oscillation unit 20 according to the voltage value represented by the voltage control signal and the voltage difference and the corresponding relation of the first reference voltage, further determines the target current branch to be communicated with the loop oscillation unit 20 according to the branch current of each current branch, and controls the conduction of the target current branch to provide the required power supply current for the loop oscillation unit 20.
In the present disclosure, the branch currents in the current branches may be the same or different, which is not specifically limited in the present disclosure.
The loop oscillation unit 20 is composed of a multi-stage RC delay unit, and generates different oscillation frequencies by adjusting its supply current. That is, the correction unit 30 controls the loop oscillation unit 20 to generate different oscillation frequencies by adjusting the supply current of the loop oscillation unit 20.
In addition, in order for the loop oscillation unit 20 to be self-oscillating, the loop gain a of the loop oscillation unit 20 should be greater than 2. In the present disclosure, the loop oscillation unit 20 may include a 5-stage delay unit in consideration of the speed, power consumption, area, and loop gain of the loop oscillation unit 20.
By adopting the technical scheme, the loop oscillator circuit comprises a correction unit, wherein the correction unit can determine a target current branch communicated with the loop oscillator unit in a plurality of parallel current branches according to the magnitude relation between the voltage control signal and the first reference voltage, and control the conduction of the target current branch so as to enable the target branch current in the target current branch to be input into the loop oscillator unit 20, and the loop oscillator unit 20 generates the current calibrated oscillation frequency according to the input target branch current. Therefore, the correction unit adjusts the oscillation frequency of the loop oscillation unit by adjusting the current input into the loop oscillation unit, the oscillation frequency of the loop oscillation unit can be quickly adjusted on the basis of not increasing the design cost, the chip area and the power consumption, the oscillation frequency precision of the loop oscillation unit can be further improved, and the precision of the loop oscillator is further improved.
In one embodiment, the frequency detection unit 10 may include: the switching capacitor comprises an equivalent resistance circuit of a switching capacitor, a first operational amplifier, a first MOS tube and a voltage generating circuit.
The equivalent resistance circuit of the switch capacitor comprises a pair of complementary switches CK and CKB and a first capacitor, and the loop oscillation unit 20 is connected with the complementary switches CK and CKB so as to control the complementary switches CK and CKB to be closed according to the current oscillation frequency of the loop oscillation unit 20, so that the equivalent resistance value of the first capacitor is obtained; the positive input end of the first operational amplifier is used for inputting a second reference voltage, the negative input end of the first operational amplifier is connected with the first end of the first MOS tube and the first end of the equivalent resistance circuit of the switch capacitor, the output end of the first operational amplifier is connected with the second end of the first MOS tube, and the second end of the equivalent resistance circuit of the switch capacitor is grounded; the third end of the first MOS tube is connected with the voltage generating circuit and is used for inputting the equivalent current value of the equivalent resistance circuit of the switch capacitor into the voltage generating circuit; the voltage generation circuit is used for generating a voltage control signal calibrated at this time according to the equivalent current value. The first MOS transistor may be an NMOS transistor or a PMOS transistor, and in this disclosure, the first MOS transistor is described as an example of the first NMOS transistor.
Fig. 2 is a schematic diagram of a loop oscillator circuit, shown in accordance with an exemplary embodiment. As shown in fig. 2, the equivalent resistance circuit of the above-mentioned switched capacitor includes a first capacitor C1 and a pair of complementary switches. A pair of complementary switches may be referred to as switch CK and switch CKB, respectively, with switch CKB being closed when switch CK is open and switch CKB being open when switch CK is closed. In fig. 2, the switch CKB is connected in parallel with the first resistor R1, and is connected in series with the switch CK after the two are connected in parallel. The loop oscillation unit 20 is connected to the switches CK and CKB, and controls the closing of the switches CK and CKB according to the current oscillation frequency of the loop oscillation unit 20. Wherein the switches CK, CKB are closed according to the current oscillation frequency of the loop oscillation unit 20.
In fig. 2, the positive input terminal of the first operational amplifier AMP1 is used for inputting the second reference voltage V ref2 The negative input end of the first operational amplifier AMP1 is connected with the source electrode of the first NMOS tube N1, and the output end of the first operational amplifier AMP1 is connected with the grid electrode of the first NMOS tube N1. The source of the first NMOS tube N1 is connected with the first end of the switch CK, the second end of the switch CK is respectively connected with the first end of the first capacitor C1 and the first end of the switch CKB, and the second end of the first capacitor C1 and the second end of the switch CKB are grounded. The drain electrode of the first NMOS transistor N1 is connected to a voltage generating circuit, and is configured to input an equivalent current value of an equivalent resistance circuit of the switch capacitor to the voltage generating circuit, so as to generate a voltage control signal.
For example, in fig. 2, the resistance value r0=1/(f×c) of the equivalent resistance of the switched capacitor, where f represents the current oscillation frequency of the loop oscillation unit 20, and C represents the capacitance value of the first capacitor C1. From the above formula, the resistance of the equivalent resistor is inversely proportional to the product of the current oscillation frequency and the capacitance, i.e. the higher the current oscillation frequency is, the larger the capacitance is, and the smaller the resistance of the equivalent resistor is. If the capacitance value is determined, the corresponding frequency of the loop oscillating unit is determined by determining the resistance value of the equivalent resistor.
In fig. 2, an equivalent resistance circuit of the switched capacitor, the first NMOS transistor N1, and the first operational amplifier AMP1 constitute a negative feedback circuit. From the principle of deficiency and short, we know V ref2 ＝V fb1 Therefore, the equivalent current value i=vr of the equivalent resistance circuit of the switch capacitor ef2 /R 0 ＝V ref2 * f is C, and thus the second reference voltage V is obtained ref2 The equivalent current value is in linear proportion to the oscillation frequency under the condition that the capacitance value C of the first capacitor C1 is unchanged.
Further, the frequency detection unit 10 may further include: and a second reference voltage selecting unit. The second reference voltage selecting unit is connected with the positive input end of the first operational amplifier and is used for inputting a second reference voltage to the positive input end of the first operational amplifier. Illustratively, as shown in fig. 2, the second reference voltage selecting unit 101 is connected to the positive input terminal of the first operational amplifier AMP1 for inputting the second reference voltage to the positive input terminal of the first operational amplifier AMP 1.
The frequency detection unit 10 may further include a second capacitor C2, as shown in fig. 2, where a first end of the second capacitor C2 is connected to the negative input end of the first operational amplifier AMP1 and a second end of the second capacitor is grounded, so as to obtain a relatively accurate equivalent current value.
The performance of the first operational amplifier AMP1 in the frequency detection unit 10 directly determines the performance of frequency detection as a core block of frequency detection. The dc amplification factor of the first operational amplifier APM1 determines the accuracy of frequency detection, the bandwidth of the first operational amplifier AMP1 determines the detection speed of frequency detection, and the noise of the first operational amplifier AMP1 affects the jitter of the output frequency, so the present disclosure needs to increase the dc amplification factor and bandwidth of the first operational amplifier AMP1 and reduce the noise and temperature drift characteristics of the first operational amplifier AMP 1.
In one embodiment, the voltage generation circuit may include a first PMOS transistor, a second PMOS transistor, and a first resistor. As shown in fig. 2, the drain electrode of the first PMOS transistor P1 is connected to the gate electrode, and is connected to the drain electrode of the first NMOS transistor N1, the source electrode of the first PMOS transistor P1 and the source electrode of the second PMOS transistor P2 are connected to the power supply VDD, and the gate electrode of the first PMOS transistor P1 is connected to the gate electrode of the second PMOS transistor. The drain electrode of the second PMOS tube P2 is connected with the grid electrode, and is respectively connected with the first end of the first resistor R1 and the drain electrode of the first NMOS tube, and the second end of the first resistor R1 is grounded. The first PMOS transistor P1 and the second PMOS transistor P2 form a mirror current source.
In the frequency detection unit 10, an equivalent current value is mirrored onto a branch of the first resistor R1 by a mirrored current source formed by the first PMOS transistor P1 and the second PMOS transistor P2, and a voltage related to the oscillation frequency is generated and recorded as a voltage control signal for the current calibration. Wherein the voltage control signal generated by the voltage generating circuit can be expressed as V control ＝V ref2 *f*C*R 1 ，R 1 The resistance value of the first resistor R1 is characterized. As can be seen from the above formula, if V ref2 C and R 1 Du ShiDetermining a value, voltage control signal V control Only the oscillation frequency f and is linear.
It should be appreciated that the present disclosure provides a loop oscillator circuit that is an on-chip loop oscillator circuit for ensuring the voltage control signal V control The first resistor R1 may be an off-chip resistor and/or the first capacitor C1 may be an off-chip capacitor. Because the accuracy of the off-chip resistor and/or the off-chip capacitor is higher, the voltage control signal V determined based on the off-chip resistor and/or the off-chip capacitor with higher accuracy control The accuracy of (2) is also high.
By adopting the technical scheme, the frequency detection unit can generate a relatively accurate voltage control signal by utilizing the off-chip resistor and/or the off-chip capacitor with relatively high precision, so that the precision of adjusting the oscillation frequency of the loop oscillator circuit is improved, and the precision of the loop oscillator circuit is further improved.
In one embodiment, the correction unit 30 may include a voltage comparison unit 301, a logic control unit 302, and a current adjustment unit 303.
The voltage comparing unit 301 is connected to the frequency detecting unit 10, and is configured to compare the magnitude relation between the voltage control signal and the first reference voltage, and output a comparison result.
The current adjustment unit 303 includes an initial current generation circuit and a plurality of parallel current branches, the initial current generation circuit being connected in parallel with the plurality of parallel current branches.
The logic control unit 302 is respectively connected to the voltage comparing unit 301 and the plurality of parallel current branches, and is configured to determine a target current branch connected to the loop oscillating unit 20 from the plurality of parallel current branches according to the comparison result output by the voltage comparing unit 301, and generate a conduction control signal, where the conduction control signal is used to control conduction of the target current branch.
Alternatively, the voltage comparing unit 301 includes a comparator and a first reference voltage selecting unit. As shown in fig. 2, a positive input terminal of the comparator COMP1 is connected to a first terminal of the first resistor R1 for inputting a voltage control signal, a negative input terminal of the comparator COMP1 is connected to the first reference voltage selecting unit for inputting the first reference voltage, and an output terminal of the comparator COMP1 is connected to the logic control unit 302 for outputting a comparison result to the logic control unit 302.
For example, if the voltage value represented by the voltage control signal is greater than the first reference voltage, the comparator COMP1 outputs a high level, and if the voltage value represented by the voltage control signal is less than the first reference voltage, the comparator COMP1 outputs a low level.
In one embodiment, the logic control unit 302 may include a logic control circuit 3021 and a clock generation circuit 3022. First, the structure of the logic control unit 302 will be described.
The logic control circuit 3021 includes a JK flip-flop array, a first and gate circuit, and a D flip-flop array. The JK trigger array comprises M JK triggers, the D trigger array comprises M+3 first D triggers, the number of the first AND gates is M, and M is an integer larger than 1.
The output end Q of the ith first D trigger is connected with the data input end D of the ith-1 first D trigger, i is an integer which sequentially takes values between M+1 and 1, the data input ends D of the Mth+1 first D trigger and the Mth+3 first D trigger are grounded, the data input end D of the Mth+2 first D trigger is connected with the output end Q of the first D trigger, the output end Q of the Mth+2 first D trigger is connected with the clock input end CK of the Mth+3 first D trigger, the clock input ends CK of the first to Mth+2 first D triggers are used for inputting clock signals generated by the clock generation circuit 3022, the reset ends of the first to Mth first D triggers and the Mth+2 first D trigger are used for inputting frequency correction control signals, and the output ends Q of the Mth+1 first D trigger and the Mth+3 first D trigger are used for setting the clock signals of the Mth+2 trigger, and the output ends Q of the Mth+1 first D trigger and the Mth+3 first D trigger are connected with the clock input end CK of the Mth+3 first D trigger.
The first input end of the jth first and circuit is connected with the output end of the voltage comparing unit 301, the second input end of the jth first and circuit is connected with the output end Q of the jth first D trigger, the output end of the jth first and circuit is connected with the K end of the jth JK trigger, the J end of the jth JK trigger is connected with the data input end D of the jth first D trigger, wherein the value range of J is [1, M ].
The reset terminal of each JK flip-flop is used for inputting a frequency correction control signal, the clock input terminal CK of each JK flip-flop is used for inputting a clock signal generated by the clock generating circuit 3022, and the on control signal includes a signal output by the output terminal Q of each JK flip-flop.
Fig. 3 is a schematic diagram of a logic control unit, according to an example embodiment. As shown in fig. 3, it is assumed that m=8, i.e., the JK flip-flop array includes 8 JK flip-flops, respectively designated JK0, JK1 … … JK7, and the D flip-flop array includes 11 first D flip-flops, respectively designated D0, D1 … … D10. The number of first AND gates is 8, denoted A0, A1 … … A7, respectively. The output end Q of the first D flip-flop D8 is connected to the data output end D of D7, the output end Q of D7 is connected to the data output end D of D6, … …, and the output end Q of D1 is connected to the data output end D of D0. The data input terminals D of D8 and D10 are grounded, the data input terminal D of D9 is connected to the output terminal Q of D0, the output terminal Q of D9 is connected to the clock input terminal CK of D10, the clock input terminals CK of D0 to D9 are used for inputting the clock signal CLK generated by the clock generating circuit 3022, the reset terminals reset of D0 to D7, D9 are used for inputting the frequency correction control signal STRAT, the set terminals set of D8 and D10 are used for inputting the frequency correction control signal STRAT, and the output terminal Q of D10 is connected to the clock generating circuit 3022.
As shown in FIG. 3, a first input terminal of A7-A0 is used for inputting the comparison result V comp The second input end of A7 is connected with the output end Q of D7, the output end of A7 is connected with the K end of JK7, the J end of A7 is connected with the data input end D of D7, the clock input end CK of JK7 is used for inputting a clock signal CLK, and the reset end reset of JK7 is used for inputting a frequency correction control signal STRAT. It should be understood that the connection relationship of each JK flip-flop in JK6-JK0 is similar to the connection relationship of JK7, and this disclosure will not be repeated. In fig. 3, the output terminals of JK1 … … JK7 respectively output signals DS7 … … DS0, and the on control signal includes each signal DS7 … … DS0.
It should be understood that in fig. 3, D5-D2, A5-A2, and JK5-JK2 are omitted, wherein connection relationships of the omitted components are similar to connection manners of D7-D6, A7-A6, and JK7-JK6 shown in fig. 3, and are not repeated herein.
Further, the clock generation circuit 3022 may include a first and gate circuit, a second D flip-flop, a delay unit, an exclusive or circuit, and an inverter. The first input end of the second AND gate circuit is connected with the output end Q of the M+3th first D trigger, the second input end of the second AND gate circuit is connected with the output end of the inverter, the output end of the second AND gate circuit is used for outputting a clock signal, and the output end of the second AND gate circuit is connected with the clock input end CK of the second D trigger; the output end QN of the second D trigger is connected with the input end of the delay unit and the second input end of the exclusive-or circuit, the output end of the delay unit is respectively connected with the first input end of the exclusive-or circuit and the data input end D of the second D trigger, and the setting end of the second D trigger is used for inputting a frequency correction control signal; the output end of the exclusive OR circuit is connected with the input end of the inverter.
Illustratively, as shown in fig. 3, the first input terminal of the second and circuit A8 is connected to the output terminal Q of D10, the second input terminal of A8 is connected to the output terminal of the inverter INV1, the output terminal of A8 outputs the clock signal CLK, and the output terminal of A8 is connected to the clock input terminal CK of D11. The output end QN of D11 is connected to the input end of the delay unit DEL1 and the second input end of the exclusive-or circuit XRO, the output end of the delay unit DEL1 is connected to the first input end of the exclusive-or circuit XRO and the data input end of D11, the set end set of D11 is used for inputting the frequency correction control signal STRAT, and the output end of the exclusive-or circuit XRO is connected to the input end of the inverter INV 1.
The operation principle of the logic control unit 302 will be described below.
As shown in fig. 3, the frequency correction control signal STRAT is a pulse signal and is active high. When STRAT has low level changed to high level, D8, D10 and D11 are set, D0 to D7, JK0 to JK7 are cleared, and one end of the second and gate A8 in the clock generation circuit 3022 is set to 1.
Before the rising edge of the clock signal CLK arrives, the output Q of D8 is high and the output Q of D7 is low due to the setting of STRAT, so the J end of JK7 is high and the K end of JK7 is low, and when the rising edge of the first clock signal CLK arrives, the signal DS7 output from the output of JK7 is high, i.e., DS7 is 1.
Since the output terminal Q of D7 is low, the data input terminal D of D6 is low, i.e., the J terminal of JK6 is low. Since the data input terminal D of D6 is low, the output terminal Q of D6 is low, i.e., the output terminal A6 is low, and the K terminal JK6 is low, at this time, the signal DS6 output from the output terminal JK6 is low, i.e., DS6 is 0. Similarly, DS5 to DS0 are all low. That is, at the time of arrival of the rising edge of the first clock signal CLK, DS7 is set to 1, and DS6 to DS0 are set to 0.
At the rising edge of the second clock signal CLK, the output terminal Q of D7 is 1, so that the output signal of A7 is high or low and V comp Decision, if V comp If the signal output from the output terminal of the A7 is high, the K terminal of the JK7 is 1, the j terminal is 0, and the signal DS7 output from the output terminal of the JK7 is low, i.e., DS7 is 0. If V is comp If the signal output from the output terminal of A7 is low, the K terminal of JK7 is 0, the j terminal is 0, and the signal DS7 output from the output terminal of JK7 is DS7 when the rising edge of the first clock signal CLK arrives, i.e., at this time, the signal DS7 output from the output terminal of JK7 is high, i.e., DS7 is 1.
By the above way, the output terminal Q of JK7 is set to 1, and then according to the comparison result V comp The output Q of JK7 is set to 0 or remains constant at 1 by the rising edge of the clock signal CLK.
That is, when the rising edge of the first clock signal CLK arrives, the signals DS7 output from the output terminals of JK7 are set to 1, and the signals output from the output terminals of JK6-JKJ0 are all set to 0. When the rising edge of the second clock signal CLK arrives, the signal DS7 output by the output terminal of JK7 is cleared or maintained, and at the same time, the signal DS6 output by the output terminal of JK6 is set to 1, and the signals output by the output terminals of JK5-JKJ0 are all set to 0. Similarly, when the rising edge of the third clock signal CLK arrives, the signals output by the output terminals of JK7 and JK6 are cleared or maintained, and at the same time, the signal DS5 output by the output terminal of JK5 is set to 1, and the signals output by the output terminals of JK4-JKJ0 are all set to 0.
Further, with the flip-flops D7 to D0 set, when the output terminal Q of D0 changes from low to high, that is, the output terminal Q of D9 changes from low to high, that is, the clock input terminal CK of D10 also changes from low to high, the data input terminal D of D10 is grounded, and therefore, the output terminal Q of D10 is 0, so that the clock signal CLK output by the output terminal of A8 is constantly 0, at which time the correction ends.
The clock signal CLK plays an indispensable role in setting and clearing the flip-flop. As can be seen from fig. 3, the clock generating circuit mainly comprises a second D flip-flop and logic circuits such as an exclusive or gate. Since the two input signals of the exclusive or gate XR0 are obtained by delaying the same signal, the XR0 output is 0 under the condition of no signal change, one input of the second and gate A8 is at a high level after passing through the inverter INV1, and CLK is changed from low to high when START makes the other input of the second and gate A8 also at a high level.
Because the clock signal CLK is used as the clock signal connected to the trigger D11, when the rising edge of CLK arrives, the output end QN of D11 is changed from low level to high level, the output end QN is divided into two paths, one path is connected to the data input end D of D11 and one input end of the exclusive or gate XR0 after passing through the delay unit DEL1, the other path of the output end QN is directly connected to the other input end of XR0, and under the action of the delay unit DEL1, the high-low level appears at the input end of XR0, so that the output of XR0 has a change from low level to high level.
The output of the exclusive or gate XR0 passes through the inverter INV1 and the second and gate circuit A8, and generates the clock signal CLK as the clock control signal of the logic control circuit.
From the above analysis, the frequency of the clock generating circuit is determined by the delay unit DEL1, and the delay time is set according to the comparison speed of the comparator COMP1 in the voltage comparing unit and the settling time of the loop oscillating unit.
The structure and operation principle of the current adjusting unit will be described.
The current adjustment unit 303 includes an initial current generation circuit and a plurality of parallel current branches. Wherein the initial current generation circuit includes: the second operational amplifier, the second NMOS tube, the second resistor, the third PMOS tube and the fourth PMOS tube.
As shown in fig. 2, the positive input terminal of the second operational amplifier AMP2 is used for inputting the third reference voltage, the negative input terminal of the second operational amplifier AMP2 is connected to the source of the second NMOS transistor N2 and the first terminal of the second resistor R2, and the output terminal of the second operational amplifier AMP2 is connected to the gate of the second NMOS transistor N2. The source electrode of the second NMOS tube N2 is connected with the first end of the second resistor R2, and the second end of the second resistor R2 is grounded. The second operational amplifier AMP2, the second NMOS transistor N2, and the second resistor R2 form a negative feedback amplifying circuit. V is known from the short-circuit characteristics of the input terminal of the amplifier ref3 ＝V fb2 The current flowing through N2 is I C ＝V ref3 /R 2 As a reference current for the loop oscillator. Wherein V is ref3 Characterizing a third reference voltage, R 2 The resistance of the second resistor R2 is characterized.
As shown in fig. 2, the current adjusting unit 303 may further include a third capacitor C3, where a first end of the third capacitor C3 is connected to the negative input end of the comparator AMP2, and a second end of the third capacitor C3 is grounded for filtering to obtain a relatively accurate reference current.
In addition, the drain electrode of the second NMOS transistor N2 is connected to the gate electrode and the drain electrode of the third PMOS transistor P3 and the gate electrode and the drain electrode of the fourth PMOS transistor P4, the gate electrode of the third PMOS transistor P3 is connected to the gate electrode of the fourth PMOS transistor P4, and the drain electrode of the fourth PMOS transistor P4 is connected to the loop oscillation unit 20. As shown in FIG. 2, the third PMOS transistor P3 and the fourth PMOS transistor P4 form a current mirror, assuming that the current of the fourth PMOS transistor P4 is I B When the current of the fourth PMOS tube P4 is input into the loop oscillation unit 20, the loop oscillation unit 20 forms an initial frequency f B 。
The multiple parallel current branches comprise M current branches, each current branch comprises a PMOS tube and a switch, the grid electrode of each PMOS tube is connected with the grid electrode of the third PMOS tube, the drain electrode of each PMOS tube is connected with the loop oscillating unit 20 through the switch in the current branch, and the switch in the jth current branch is connected with the output end Q of the jth JK trigger and is used for being controlled by the signal output by the output end Q of the jth JK trigger to be closed and disconnected.
For example, assuming that M is 8, the current adjustment unit 303 in fig. 2 includes 8 parallel current branches, and in each current branch, when the switch in the current branch is in a closed state, the PMOS transistor and the third PMOS transistor P3 in the current branch form a current mirror. For example, a first current branch comprises P5 and switch S0 in series, a second current branch comprises P6 and switch S1 in series, a third current branch comprises P7 and switch S2 in series, a fourth current branch comprises P8 and switch S3 in series, a fifth current branch comprises P9 and switch S4 in series, a sixth current branch comprises P10 and switch S5 in series, a seventh current branch comprises P11 and switch S6 in series, and an eighth current branch comprises P12 and switch S7 in series.
The switches in each current branch are controlled by signals output by the output end Q of the JK trigger in the logic control circuit. For example, the signal DS0 output by the JK0 output Q is used to control the switch S0 in the first current branch, the signal DS1 output by the JK1 output Q is used to control the switch S1 in the second current branch, the signal DS2 output by the JK2 output Q is used to control the switch S2 in the third current branch, … …, and the signal DS7 output by the JK7 output Q is used to control the switch S7 in the eighth current branch. Wherein, for each current branch, the switch in the branch is closed when the signal controlling the switch in the branch is high, and the switch in the branch is opened when the signal controlling the switch in the branch is low.
In fig. 2, the image currents generated by P5 to P12 for adjusting the oscillation frequency of the loop oscillation unit 20 are expressed in the form of the second power, that is, the branch current of the current branch where P5 is located is expressed as 2 0 I 1 The branch current of the current branch where P6 is located is denoted as 2 1 I 1 … … the branch current of the current branch in which P12 is located is denoted as 2 7 I 1 . The values illustrate that the branch currents of the two adjacent current branches are 2 times as much as each other by designing the current mirror proportion of the current mirror.
In FIG. 2, the branch currents due to the plurality of parallel current branches are 2 respectively 0 I 1 To 2 7 I 1 Thus, the current input to the loop oscillation unit 20, i.e., the supply current of the loop oscillation unit 20, is increased or decreased by one I 1 The oscillation frequency of the loop oscillation unit 20 is increased or decreased by Δf, so that the current adjusting unit shown in fig. 2 can adjust Δf at a minimum and 256×Δf at a maximum, i.e., in the circuit shown in fig. 2, the oscillation frequency of the loop oscillation unit 20 is at the initial frequency f B The adjustment range is delta f-256 x delta f. Wherein the power supply current of the loop oscillation unit can be calculated by adopting the prior art to change by one I 1 The value of the change Δf in the oscillation frequency.
It should be noted that in practical applications, a greater or lesser number of current branches may be provided, and accordingly, the adjustment range of the oscillation frequency of the loop oscillation unit 20 may be greater or smaller. Secondly, it should be noted that, in the present disclosure, in order to improve adjustment accuracy, the branch currents of two adjacent current branches are set to be 2 times of the relationship, and in practical application, the branch currents of two adjacent current branches may also be set to be 3 times of the relationship, 5 times of the relationship, and so on.
In a complete process of adjusting the oscillation frequency, the frequency correction control signal STRAT is first a high pulse level signal, when the rising edge of STRAT arrives, the output terminal of JK7 outputs a high level signal, i.e. JK7 is set to 1, the output terminals of JK6-JK0 all output low level signals, i.e. JK6-JK0 are set, so that the switch S7 in the eighth current branch is closed, the switches in the other current branches are all open, and the supply current of the loop oscillation unit 20 is increased by 2 7 I 1 That is, the oscillation frequency of the loop oscillation unit 20 is at the original oscillation frequency f B On the basis of (a) 128 x af is increased.
Then, the loop oscillation unit 20 sets the oscillation frequency (f B +128×Δf), frequency detection unit 10 based on current oscillation frequency f=f B +128 Δf, generating a voltage control signal V control ComparatorCOMP1 vs. voltage control signal V control Comparing with the first reference voltage and outputting a comparison result V comp If V comp To be high, the current oscillation frequency characterizing the loop oscillation unit 20 is greater than the desired oscillation frequency, requiring a reduction in the oscillation frequency. In the logic control circuit, JK7 is set to 0, while JK6 is set to 1, and JK5-JK0 is set to 0. If V is comp At a low level, the current oscillation frequency characterizing the loop oscillation unit 20 is smaller than the desired oscillation frequency, requiring an increase in the oscillation frequency. In the logic control circuit, JK7 is kept unchanged at 1, while JK6 is set to 1 and JK5-JK0 is set to 0. Wherein the first reference voltage is set based on a preset desired oscillation frequency, e.g. according to formula V 0 ＝V ref2 *f 0 *C*R 1 Calculate and expect the oscillation frequency f 0 Corresponding voltage V 0 The first reference voltage may be slightly greater than V 0 Is a voltage value of (a).
In the present disclosure, under the action of an internal self-built clock signal, JK6-JK0 is set 1 or cleared according to the above manner, so as to implement automatic correction of oscillation frequency.
From the overall frequency adjustment process, the oscillation frequency of the final output is determined by the three reference voltages, and in the present disclosure, devices of different oscillation frequencies are realized by setting different reference voltages. For example, the reference voltage selection unit employed in the present disclosure may include a plurality of voltage branches, each including a reference voltage and a switch. Illustratively, fig. 4 is a schematic diagram of a reference voltage selection unit, according to an exemplary embodiment. As shown in fig. 4, assuming that the reference voltage selecting unit includes 8 voltage branches, each of which includes a reference voltage and a switch, the reference voltage V can be selected by closing the switch on the corresponding branch ref For example, the voltage V is selected when the switch S8 is closed 1 As reference voltage V ref Select voltage V when switch S9 is closed 2 As reference voltage V ref … …, selecting the voltage V when closing switch S9 8 As reference voltage V ref 。
FirstThe values are illustrative of the reference voltages on each voltage leg being the same or different, and the disclosure is not limited in this regard. It is further worth noting that the reference voltage V ref May refer to one or more of the first, second and third reference voltages described above. In addition, the second reference voltage and the third reference voltage may be the same, that is, the same reference voltage selecting unit may be employed.
By adopting the technical scheme and adopting M-bit correction precision, the maximum 2 of minimum one time can be realized M The precision of the frequency of the adjustment is adjusted, and the design mode of adding a phase-locked loop after the traditional manual adjustment or external crystal oscillator is adopted, so that the loop oscillator circuit provided by the disclosure is low in cost, small in chip area, low in power consumption, convenient to use and high in precision.
The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, but the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solutions of the present disclosure within the scope of the technical concept of the present disclosure, and all the simple modifications belong to the protection scope of the present disclosure.
In addition, the specific features described in the above embodiments may be combined in any suitable manner without contradiction. The various possible combinations are not described further in this disclosure in order to avoid unnecessary repetition.
Moreover, any combination between the various embodiments of the present disclosure is possible as long as it does not depart from the spirit of the present disclosure, which should also be construed as the disclosure of the present disclosure.

Claims (10)

1. A loop oscillator circuit, the circuit comprising:
the frequency detection unit (10) is connected with the loop oscillation unit (20) and is used for collecting the current oscillation frequency of the loop oscillation unit (20) and converting the current oscillation frequency into a voltage signal to be used as a voltage control signal for current calibration, wherein the current oscillation frequency is the oscillation frequency of the loop oscillation unit (20) corrected last time;
the correction unit (30) is respectively connected with the frequency detection unit (10) and the loop oscillation unit (20), the correction unit (30) comprises a plurality of parallel current branches which are connected with the loop oscillation unit (20) in an on-off mode, and the correction unit (30) is used for determining a target current branch which is communicated with the loop oscillation unit (20) in the plurality of parallel current branches according to the magnitude relation between the voltage control signal and the first reference voltage, and controlling the conduction of the target current branch so as to enable the target branch current in the target current branch to be input into the loop oscillation unit (20);
The loop oscillation unit (20) is used for generating the oscillation frequency calibrated at this time according to the input target branch current.
2. The loop oscillator circuit according to claim 1, characterized in that the frequency detection unit (10) comprises: the switching capacitor comprises an equivalent resistance circuit of a switching capacitor, a first operational amplifier, a first MOS tube and a voltage generating circuit;
the equivalent resistance circuit of the switch capacitor comprises a pair of complementary switches (CK, CKB) and a first capacitor, wherein the loop oscillation unit (20) is connected with the complementary switches (CK, CKB) so as to control the closing of the complementary switches (CK, CKB) according to the current oscillation frequency of the loop oscillation unit (20) to obtain the equivalent resistance value of the first capacitor;
the positive input end of the first operational amplifier is used for inputting a second reference voltage, the negative input end of the first operational amplifier is connected with the first end of the first MOS tube and the first end of the equivalent resistance circuit of the switch capacitor, the output end of the first operational amplifier is connected with the second end of the first MOS tube, and the second end of the equivalent resistance circuit of the switch capacitor is grounded;
the third end of the first MOS tube is connected with the voltage generation circuit and is used for inputting an equivalent current value of an equivalent resistance circuit of the switch capacitor into the voltage generation circuit;
The voltage generation circuit is used for generating a voltage control signal calibrated at this time according to the equivalent current value.
3. The loop oscillator circuit of claim 2, wherein the first MOS transistor is a first NMOS transistor; the voltage generation circuit comprises a first PMOS tube, a second PMOS tube and a first resistor;
the drain electrode of the first PMOS tube is connected with the grid electrode and is respectively connected with the drain electrode of the first NMOS tube, the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with a power supply, and the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube;
the drain electrode of the second PMOS tube is connected with the grid electrode and is respectively connected with the first end of the first resistor and the drain electrode of the first NMOS tube, and the second end of the first resistor is grounded;
the correction unit (30) is connected to a first end of the first resistor.
4. A loop oscillator circuit according to claim 3, characterized in that the loop oscillator circuit is an on-chip loop oscillator circuit;
the first resistor is an off-chip resistor and/or the first capacitor is an off-chip capacitor.
5. The loop oscillator circuit according to claim 2, characterized in that the frequency detection unit (10) further comprises: and the second reference voltage selection unit is connected with the positive input end of the first operational amplifier and is used for inputting the second reference voltage to the positive input end of the first operational amplifier.
6. The loop oscillator circuit according to any one of claims 1 to 5, characterized in that the correction unit (30) comprises a voltage comparison unit (301), a logic control unit (302) and a current adjustment unit (303);
the voltage comparison unit (301) is connected with the frequency detection unit (10) and is used for comparing the magnitude relation between the voltage control signal and the first reference voltage and outputting a comparison result;
the current regulation unit (303) comprises an initial current generation circuit and a plurality of parallel current branches, wherein the initial current generation circuit is connected with the plurality of parallel current branches in parallel;
the logic control unit (302) is respectively connected with the voltage comparison unit (301) and a plurality of parallel current branches, and is used for determining a target current branch communicated with the loop oscillation unit (20) in the plurality of parallel current branches according to the comparison result output by the voltage comparison unit (301), and generating a conduction control signal, wherein the conduction control signal is used for controlling the conduction of the target current branch.
7. The loop oscillator circuit of claim 6, characterized in that the logic control unit (302) comprises a logic control circuit (3021) and a clock generation circuit (3022);
The logic control circuit (3021) comprises a JK trigger array, first AND gates and a D trigger array, wherein the JK trigger array comprises M JK triggers, the D trigger array comprises M+3 first D triggers, the number of the first AND gates is M, and M is an integer larger than 1;
the output end Q of the ith first D trigger is connected with the data input end D of the ith-1 first D trigger, i is an integer which sequentially takes values between M+1 and 1, the data input ends D of the Mth+1 first D trigger and the Mth+3 first D trigger are grounded, the data input end D of the Mth+2 first D trigger is connected with the output end Q of the first D trigger, the output end Q of the Mth+2 first D trigger is connected with the clock input end CK of the Mth+3 first D trigger, the clock input ends CK of the first D trigger to the Mth+2 first D trigger are used for inputting clock signals generated by the clock generating circuit (3022), the reset ends of the first D trigger to the Mth first D trigger and the Mth+2 first D trigger are used for inputting frequency correction control signals, and the clock input ends CK of the Mth+1 first D trigger and the Mth+2 first D trigger are used for generating clock signals (the clock input ends CK of the Mth+2) and the Mth+1 first D trigger are connected with the clock input ends Q of the Mth+2 trigger;
The first input end of the jth first AND gate circuit is connected with the output end of the voltage comparison unit (301), the second input end of the jth first AND gate circuit is connected with the output end Q of the jth first D trigger, the output end of the jth first AND gate circuit is connected with the K end of the jth JK trigger, and the J end of the jth JK trigger is connected with the data input end D of the jth first D trigger, wherein the value range of J is [1, M ];
the reset terminal of each JK trigger is used for inputting a frequency correction control signal, the clock input terminal CK of each JK trigger is used for inputting a clock signal generated by the clock generating circuit (3022), and the conduction control signal comprises a signal output by the output terminal Q of each JK trigger.
8. The loop oscillator circuit of claim 7, wherein the clock generation circuit (3022) comprises a second and circuit, a second D flip-flop, a delay unit, an exclusive-or circuit, and an inverter;
the first input end of the second AND gate circuit is connected with the output end Q of the M+3th first D trigger, the second input end of the second AND gate circuit is connected with the output end of the inverter, the output end of the second AND gate circuit is used for outputting a clock signal, and the output end of the second AND gate circuit is connected with the clock input end CK of the second D trigger;
The output end QN of the second D trigger is connected with the input end of the delay unit and the second input end of the exclusive-or circuit, the output end of the delay unit is respectively connected with the first input end of the exclusive-or circuit and the data input end D of the second D trigger, and the setting end of the second D trigger is used for inputting the frequency correction control signal;
the output end of the exclusive-or circuit is connected with the input end of the inverter.
9. The loop oscillator circuit of claim 7, wherein the initial current generation circuit comprises: the second operational amplifier, the second NMOS tube, the second resistor, the third PMOS tube and the fourth PMOS tube;
the positive input end of the second operational amplifier is used for inputting a third reference voltage, the negative input end of the second operational amplifier is connected with the source electrode of the second NMOS tube and the first end of the second resistor, and the output end of the second operational amplifier is connected with the grid electrode of the second NMOS tube;
the source electrode of the second NMOS tube is connected with the first end of the second resistor, the second end of the second resistor is grounded, the drain electrode of the second NMOS tube is connected with the grid electrode and the drain electrode of the third PMOS tube and the grid electrode and the drain electrode of the fourth PMOS tube, the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the loop oscillation unit (20);
The current branches in parallel connection comprise M current branches, each current branch comprises a PMOS tube and a switch, the grid electrode of the PMOS in each current branch is connected with the grid electrode of the third PMOS tube, and the drain electrode of the PMOS tube in each current branch is connected with the loop oscillation unit (20) through the switch in the current branch;
the switch in the jth current branch is connected with the output end Q of the jth JK trigger and is used for being controlled to be closed and opened by a signal output by the output end Q of the jth JK trigger.
10. The loop oscillator circuit of claim 6, characterized in that the voltage comparison unit (301) comprises a comparator and a first reference voltage selection unit;
the positive input end of the comparator is used for inputting a voltage control signal, the negative input end of the comparator is connected with the first reference voltage selection unit and used for inputting a first reference voltage, and the output end of the comparator is connected with the logic control unit (302) and used for outputting a comparison result to the logic control unit (302).
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