CN117096038B - Double-sided photoelectric interconnection packaging structure and preparation method thereof - Google Patents
Double-sided photoelectric interconnection packaging structure and preparation method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- G—PHYSICS
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- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
- G02B6/4236—Fixing or mounting methods of the aligned elements
- G02B6/424—Mounting of the optical light guide
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4274—Electrical aspects
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4274—Electrical aspects
- G02B6/428—Electrical aspects containing printed circuit boards [PCB]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Optical Integrated Circuits (AREA)
Abstract
The invention provides a double-sided photoelectric interconnection packaging structure and a preparation method thereof, wherein a double-sided composite functional chip is prepared, so that a composite optical waveguide wiring layer is arranged in the double-sided composite functional chip to be combined with an optical chip for optical transmission, and circuit areas on the upper side and the lower side of the composite optical waveguide wiring layer of the double-sided composite functional chip are combined with a metal connecting piece to be electrically transmitted with the optical chip and a circuit substrate, thereby realizing photoelectric interconnection integration, reducing packaging size, reducing power consumption and improving reliability.
Description
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and relates to a double-sided photoelectric interconnection packaging structure and a preparation method thereof.
Background
With the continued development of big data, artificial intelligence, telemedicine, internet of things, electronic commerce, 5G communications, global data traffic has exploded, lower cost, more reliable, faster and higher density circuits are the goal of integrated circuit packaging pursuits.
In a semiconductor package structure, functional chips such as ASIC (Application Specific Integrated Circuit ) chips and HBM (High Bandwidth Memory, high bandwidth memory) chips are typically disposed on RDL (Re-distribution Layer, redistribution layer) and electrically connected and signal communicated with each other through the RDL, but the electrical connection and signal communication between the functional chips are performed through the RDL, which may cause distortion of transmission signals due to the length, distribution of transmission paths, and the like.
Because light has excellent performances such as small signal attenuation, low energy consumption, high bandwidth, compatibility with CMOS and the like, the industry generally considers that the light technology is introduced into the semiconductor manufacturing process, so that the chip size, the cost and the power consumption can be reduced, and the reliability can be improved. Therefore, the functional chips can be optically coupled through optical fibers in an end-face coupling (edge coupling) mode, but with the reduction of the chip spacing, the application mode of optical fiber coupling is limited.
Therefore, it is necessary to provide a double-sided photoelectric interconnection packaging structure and a preparation method thereof.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a double-sided optoelectronic interconnect package structure and a method for fabricating the same, which are used for solving the signal transmission problem between functional chips in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing a double-sided optoelectronic interconnect package structure, comprising the steps of:
providing a first wafer-level electric chip and a second wafer-level electric chip, wherein the first wafer-level electric chip comprises a first circuit area positioned at the top and a first substrate area positioned at the bottom, and the second wafer-level electric chip comprises a second circuit area positioned at the top and a second substrate area positioned at the bottom;
patterning the first wafer level electrical chip to form a first recess in the first substrate region and patterning the second wafer level electrical chip to form a second recess in the second substrate region;
forming a first optical waveguide wiring layer in the first groove, and forming a second optical waveguide wiring layer in the second groove;
bonding the first wafer-level electrical chip and the second wafer-level electrical chip, and connecting the first optical waveguide wiring layer and the second optical waveguide wiring layer to form a composite optical waveguide wiring layer;
patterning from the top of the first wafer level electrical chip to form a first waveguide optical port exposing the composite optical waveguide wiring layer, and patterning from the top of the second wafer level electrical chip to form a second waveguide optical port exposing the composite optical waveguide wiring layer;
forming a first metal connecting piece on the surface of the first circuit area, wherein the first metal connecting piece is electrically connected with the first circuit area, and forming a second metal connecting piece on the surface of the second circuit area, wherein the second metal connecting piece is electrically connected with the second circuit area;
cutting to form a double-sided composite functional chip;
providing a circuit substrate, wherein a first optical chip is arranged in the circuit substrate;
forming a metal wiring layer on the circuit substrate, wherein the metal wiring layer is electrically connected with the first optical chip and the circuit substrate, and the metal wiring layer exposes a first photosensitive area of the first optical chip;
bonding the double-sided composite functional chip on the circuit substrate, wherein the first metal connecting piece is electrically connected with the metal wiring layer, and the first waveguide optical port is correspondingly arranged with the first photosensitive area;
and providing a second optical chip, bonding the second optical chip on the circuit substrate, wherein the second optical chip is electrically connected with the metal wiring layer and the second metal connecting piece, and a second photosensitive area of the second optical chip is arranged corresponding to the second waveguide optical port.
Optionally, the composite optical waveguide wiring layer is in an axisymmetric pattern along the bonding surface or in an asymmetric pattern along the bonding surface.
Optionally, the method further comprises the step of forming a first shading protection layer covering the bottom and the side wall of the first groove; and/or further comprising the step of forming a second light-shielding protection layer covering the bottom and the side wall of the second groove.
Optionally, the method for forming the first light-shielding protection layer comprises a semiconductor exposure development method, and the formed first light-shielding protection layer comprises a metal first light-shielding protection layer or an organic-inorganic composite first light-shielding protection layer; the method for forming the second light-shielding protective layer comprises a semiconductor exposure development method, and the formed second light-shielding protective layer comprises a metal second light-shielding protective layer or an organic-inorganic composite second light-shielding protective layer.
Optionally, the method for forming the first optical waveguide wiring layer includes a semiconductor exposure developing method, and the formed first optical waveguide wiring layer includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer; the method of forming the second optical waveguide wiring layer includes a semiconductor exposure developing method, and the formed second optical waveguide wiring layer includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer.
Optionally, the method for cutting to form the double-sided composite functional chip includes a mechanical cutting method or a laser cutting method.
Optionally, the method further comprises the step of forming a third metal connection to the circuit substrate.
The invention also provides a double-sided photoelectric interconnection packaging structure, which comprises:
a circuit substrate in which a first optical chip is disposed;
the metal wiring layer is positioned on the circuit substrate, is electrically connected with the first optical chip and the circuit substrate, and exposes the first photosensitive area of the first optical chip;
the double-sided composite functional chip is bonded on the circuit substrate and comprises a composite optical waveguide wiring layer, a first circuit area, a first metal connecting piece and a first waveguide light port, wherein the first circuit area is positioned below the composite optical waveguide wiring layer, the first metal connecting piece is electrically connected with the first circuit area, the first waveguide light port is exposed out of the composite optical waveguide wiring layer, the second circuit area is positioned above the composite optical waveguide wiring layer, the second metal connecting piece is electrically connected with the second circuit area, the second waveguide light port is exposed out of the composite optical waveguide wiring layer, and the first waveguide light port and the first photosensitive area of the first optical chip are correspondingly arranged;
the second optical chip is bonded on the circuit substrate and electrically connected with the metal wiring layer and the second metal connecting piece, and a second photosensitive area of the second optical chip is arranged corresponding to the second waveguide optical port.
Optionally, the optical waveguide circuit further comprises a light shielding protective layer coating the composite optical waveguide wiring layer.
Alternatively, the composite optical waveguide wiring layer includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer.
As described above, the double-sided photoelectric interconnection packaging structure and the preparation method thereof enable the double-sided composite functional chip to be internally provided with the composite optical waveguide wiring layer for optical transmission by combining with the optical chip, and the circuit areas on the upper side and the lower side of the composite optical waveguide wiring layer of the double-sided composite functional chip are combined with the metal connecting piece for electric transmission with the optical chip and the circuit substrate, thereby realizing photoelectric interconnection integration, reducing packaging size, reducing power consumption and improving reliability, being applicable to high-density integrated packaging and being capable of realizing good photoelectric signal transmission.
Drawings
Fig. 1 is a schematic process flow diagram of a dual-sided optoelectronic interconnect package structure in accordance with an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a first wafer level chip according to an embodiment of the invention.
Fig. 3 is a schematic structural view of the first groove formed in the embodiment of the invention.
Fig. 4 is a schematic diagram showing a structure after forming the first optical waveguide wiring layer in the embodiment of the present invention.
Fig. 5 is a schematic top view of fig. 4.
Fig. 6 is a schematic structural view showing a second wafer level electrical chip having a second optical waveguide wiring layer in an embodiment of the present invention.
Fig. 7 is a schematic diagram of a structure of a bonded first wafer level chip and a bonded second wafer level chip according to an embodiment of the invention.
Fig. 8 is a schematic structural diagram of a dual-sided composite functional chip formed by dicing according to an embodiment of the present invention.
Fig. 9 is a schematic diagram of a structure after forming a metal wiring layer on a circuit substrate according to an embodiment of the invention.
Fig. 10 is a schematic structural diagram of a dual-sided composite functional chip bonded to a metal wiring layer according to an embodiment of the present invention.
Fig. 11 is a schematic structural diagram of bonding a second optical chip to a metal wiring layer according to an embodiment of the invention.
Fig. 12 is a schematic structural view of the third metal connector according to the embodiment of the present invention.
Description of element reference numerals
100-a double-sided composite functional chip; 101-a first wafer level electrical chip; 101 a-a first circuit region; 101 b-a first substrate region; 102-a first bonding pad; 103-a first groove; 104-a first optical waveguide wiring layer; 105-a first metal connector; 106-a first waveguide optical port; 201-a second wafer level electrical chip; 201 a-a second circuit region; 201 b-a second substrate region; 202-a second bonding pad; 204-a second optical waveguide wiring layer; 205-a second metal connection; 206-a second waveguide optical port; 301-a composite optical waveguide wiring layer; 200-a circuit substrate; 300-a first optical chip; 310-a first photosensitive region; 400-a metal wiring layer; 500-a second optical chip; 510-a second photosensitive region; 520-a metal connection layer; 600-third metal connector.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures, including embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact, and further, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
As shown in fig. 1, the present embodiment provides a method for manufacturing a double-sided photoelectric interconnection package structure, by manufacturing a double-sided composite functional chip, a composite optical waveguide wiring layer is provided inside the double-sided composite functional chip to perform optical transmission in combination with an optical chip, and circuit areas on upper and lower sides of the composite optical waveguide wiring layer in the double-sided composite functional chip are combined with metal connectors to perform electric transmission with the optical chip and a circuit substrate, so as to implement photoelectric interconnection integration, reduce package size, reduce power consumption, improve reliability, and be suitable for high-density integrated package, and can implement good photoelectric signal transmission.
The following is a further description of the preparation of the double-sided optoelectronic interconnect package structure with reference to fig. 2 to 12, which specifically includes:
first, referring to fig. 1, 2 and 6, step S1 is performed to provide a first wafer level chip 101 and a second wafer level chip 201, where the first wafer level chip 101 includes a first circuit region 101a at the top and a first substrate region 101b at the bottom, and the second wafer level chip 201 includes a second circuit region 201a at the top and a second substrate region 201b at the bottom.
Specifically, the dimensions of the first wafer level chip 101 and the second wafer level chip 201 may include, for example, 4 inches, 6 inches, 8 inches, 12 inches, etc., and the dimensions of the first wafer level chip 101 and the second wafer level chip 201 are not limited thereto and may be selected as required.
The specific types of the first wafer level electrical chip 101 and the second wafer level electrical chip 201 may be selected according to needs, the first circuit area 101a is disposed at the top of the first wafer level electrical chip 101 for performing electrical signal transmission, the first substrate area 101b of the first wafer level electrical chip 101 may provide space for subsequently preparing the first optical waveguide wiring layer 104, and similarly, the second circuit area 201a is disposed at the top of the second wafer level electrical chip 201 for performing electrical signal transmission, and the second substrate area 201b of the second wafer level electrical chip 201 may provide space for subsequently preparing the second optical waveguide wiring layer 204.
In fig. 2 and fig. 6, only the first bonding pad 102 for electrical extraction in the first circuit region 101a and the second bonding pad 202 for electrical extraction in the second circuit region 201a are illustrated, and the arrangement of the metal wiring layers in the first circuit region 101a and the second circuit region 201a is not illustrated.
Next, referring to fig. 1, 3 and 6, step S2 is performed to pattern the first wafer level chip 101 to form a first recess 103 in the first substrate region 101b, and pattern the second wafer level chip 201 to form a second recess (not shown) in the second substrate region 201b.
Specifically, the bottom non-circuit area of the first wafer level electrical chip 101 may be patterned by using a semiconductor photolithography technique to form a reserved channel for the preparation of the first optical waveguide wiring layer 104, that is, the first groove 103, and similarly, the bottom non-circuit area of the second wafer level electrical chip 201 may be patterned by using a semiconductor photolithography technique to form a reserved channel for the preparation of the second optical waveguide wiring layer 204, that is, the second groove, and the shapes of the first groove 103 and the second groove may be selected according to need, which is not limited herein.
Next, referring to fig. 1, 4 and 6, step S3 is performed to form a first optical waveguide wiring layer 104 in the first groove 103 and a second optical waveguide wiring layer 204 in the second groove.
As an example, a method of forming the first optical waveguide wiring layer 104 may include a semiconductor exposure developing method, the first optical waveguide wiring layer 104 formed may include an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, a lithium borate optical waveguide wiring layer, or the like, and a material of the organic polymer optical waveguide wiring layer may be polymethyl methacrylate (PMMA), polystyrene (PS), polycarbonate (PC) epoxy, fluorine-containing polyimide, or the like; the method of forming the second optical waveguide wiring layer 204 may include a semiconductor exposure developing method, and the second optical waveguide wiring layer 204 may include an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, a lithium borate optical waveguide wiring layer, or the like, and a material of the organic polymer optical waveguide wiring layer may be polymethyl methacrylate (PMMA), polystyrene (PS), polycarbonate (PC) epoxy, fluorine-containing polyimide, or the like.
Fig. 5 is a schematic plan view of the structure of fig. 4, and the material, distribution, and preparation of the first optical waveguide wiring layer 104 and the second optical waveguide wiring layer 204 are not limited thereto.
Further, the method may further include a step of forming a first light shielding layer (not shown) covering the bottom and the sidewall of the first recess 103; and/or may further include a step of forming a second light shielding layer (not shown) covering the bottom and sidewalls of the second groove to protect the formed corresponding optical waveguide wiring layer by the first light shielding layer and/or the second light shielding layer, so as to reduce light loss.
The method for forming the first light-shielding protection layer may include a semiconductor exposure developing method, and the formed first light-shielding protection layer may include a metal first light-shielding protection layer, such as copper, gold, aluminum, silver, platinum, titanium, or the like, or the formed first light-shielding protection layer may be an organic-inorganic composite first light-shielding protection layer, or the like, so as to cover the first optical waveguide wiring layer 104 through the first light-shielding protection layer, so as to reduce light loss.
Similarly, the method of forming the second light-shielding layer may include a semiconductor exposure developing method, and the formed second light-shielding layer may include a metal second light-shielding layer, such as copper, gold, aluminum, silver, platinum, titanium, or the like, or the formed second light-shielding layer may be an organic-inorganic composite second light-shielding layer or the like, so as to cover the second optical waveguide wiring layer 204 with the second light-shielding layer, thereby reducing light loss.
Next, referring to fig. 1 and 7, step S4 is performed to bond the first wafer level electrical chip 101 and the second wafer level electrical chip 201, and the first optical waveguide wiring layer 104 and the second optical waveguide wiring layer 204 are connected to each other to form a composite optical waveguide wiring layer 301.
As an example, the composite optical waveguide wiring layer 301 may be axisymmetric along the bonding surface or asymmetric along the bonding surface.
Specifically, referring to fig. 7, in this embodiment, the first wafer level electrical chip 101 and the second wafer level electrical chip 201 before bonding preferably have the same structure, so that after bonding, the composite optical waveguide wiring layer 301 may have an axisymmetric pattern along the bonding surface, but is not limited thereto, and in another embodiment, the first wafer level electrical chip 101 and the second wafer level electrical chip 201 may have different shapes according to the requirements of the process and the like, so that after bonding, the composite optical waveguide wiring layer 301 may have an asymmetric pattern along the bonding surface, which is not excessively limited herein.
Next, referring to fig. 1 and 8, step S5 is performed to pattern from the top of the first wafer level electrical chip 101 to form a first waveguide optical port 106 exposing the composite optical waveguide wiring layer 301, and to pattern from the top of the second wafer level electrical chip 201 to form a second waveguide optical port 206 exposing the composite optical waveguide wiring layer 301.
As an example, the method of patterning the first wafer level electrical chip 101 and the second wafer level electrical chip 201 may include a laser etching method to form the first waveguide optical port 106 and the second waveguide optical port 206 exposing the composite optical waveguide wiring layer 301 so that light is transmitted along the first waveguide optical port 106 and the second waveguide optical port 206. No undue limitations are made herein with respect to the morphology and size of the first waveguide port 106 and the second waveguide port 206.
Next, referring to fig. 1 and 8, step S6 is performed to form a first metal connection 105 on the surface of the first circuit area 101a, wherein the first metal connection 105 is electrically connected to the first circuit area 101a, and a second metal connection 205 is formed on the surface of the second circuit area 201a, and the second metal connection 205 is electrically connected to the second circuit area 201 a.
Specifically, referring to fig. 8, in the present embodiment, the first metal connection member 105 and the second metal connection member 205 are both made of a composite structure of metal posts and metal bumps, so as to facilitate subsequent electrical connection and testing, the first metal connection member 105 is electrically connected to the first bonding pad 102, the second metal connection member 205 is electrically connected to the second bonding pad 202, and the types of the first metal connection member 105 and the second metal connection member 205 are not limited thereto, and may be metal bumps or metal posts, etc., which are not excessively limited herein, and may be selected according to requirements.
Next, referring to fig. 1 and 8, step S7 is performed to perform dicing to form the dual-sided composite functional chip 100.
As an example, the method of performing dicing to form the dual-sided composite functional chip 100 may include a mechanical dicing method or a laser dicing method, and may be specifically selected as needed.
Next, referring to fig. 1 and 9, step S8 is performed to provide a circuit substrate 200, in which the first optical chip 300 is disposed in the circuit substrate 200.
Specifically, the first optical chip 300 has an electrical lead-out terminal and a first photosensitive region 310, and the electrical lead-out terminal and the first photosensitive region 310 are exposed from the circuit substrate 200. The type and size of the circuit board 200, and the type and size of the first optical chip 300 are not excessively limited.
Next, referring to fig. 1 and 9, step S9 is performed to form a metal wiring layer 400 on the circuit substrate 200, wherein the metal wiring layer 400 is electrically connected to both the first optical chip 300 and the circuit substrate 200, and the metal wiring layer 400 exposes the first photosensitive region 310 of the first optical chip 300.
Specifically, as shown in fig. 9, the patterned metal wiring layer 400 is electrically connected to the electrical outlet of the first optical chip 300, and the metal wiring layer 400 is electrically connected to the circuit substrate 200, so that the first optical chip 300 can be electrically connected to the circuit substrate 200. The method, material, distribution, etc. for preparing the metal wiring layer 400 are not limited herein.
Next, referring to fig. 1, 8 and 10, step S10 is performed to bond the dual-sided composite functional chip 100 to the circuit substrate 200, and the first metal connection member 105 is electrically connected to the metal wiring layer 400, and the first waveguide optical port 106 is disposed corresponding to the first photosensitive region 310 for optical transmission, wherein the dual-sided composite functional chip 100 may be directly bonded to the metal wiring layer 400, but is not limited thereto.
Next, referring to fig. 1, 8 and 11, step S11 is performed to provide a second optical chip 500, and the second optical chip 500 is bonded to the circuit substrate 200, and the second optical chip 500 is electrically connected to the metal wiring layer 400 and the second metal connector 205, and the second photosensitive region 510 of the second optical chip 500 is disposed corresponding to the second waveguide optical port 206 for optical transmission, where the second optical chip 500 may be directly bonded to the metal wiring layer 400, but is not limited thereto.
Specifically, the second optical chip 500 has an electrical lead-out end, a second photosensitive region 510, and a metal connection layer 520 connecting the electrical lead-out end and the second photosensitive region 510, where the electrical lead-out end of the second optical chip 500 may be electrically connected to the metal wiring layer 400 through a metal bump, a metal pillar, or the like. The kind and size of the second optical chip 500 are not excessively limited herein.
Further, as shown in fig. 12, a step of forming a third metal connector 600 electrically connected to the circuit substrate 200 may be further included, and the third metal connector 600 may include a metal bump, a metal post, etc., which is not limited herein.
It will be appreciated that, to increase the yield, the double-sided optoelectric interconnection package structure in fig. 12 may be regarded as a single structure formed after the dicing process, and that the double-sided optoelectric interconnection package structure in fig. 12 may be a single structure obtained by direct fabrication, as needed, without being excessively limited thereto.
Referring to fig. 2 to 12, the present embodiment further provides a double-sided photoelectric interconnection packaging structure, which may be directly manufactured by the above manufacturing process, so that the materials, manufacturing processes, etc. of the double-sided photoelectric interconnection packaging structure may be referred to above, and of course, the double-sided photoelectric interconnection packaging structure may also be manufactured by other manufacturing processes as required.
Specifically, in this embodiment, the double-sided optoelectronic interconnection packaging structure includes: the circuit board 200, the metal wiring layer 400, the double-sided composite functional chip 100, and the second optical chip 500.
Wherein, the circuit substrate 200 is provided with a first optical chip 300; the metal wiring layer 400 is located on the circuit substrate 200 and electrically connected to the first optical chip 300 and the circuit substrate 200, and the metal wiring layer 400 exposes the first photosensitive region 310 of the first optical chip 300; the double-sided composite functional chip 100 is bonded on the circuit substrate 200, and includes a composite optical waveguide wiring layer 301, a first circuit region 101a located below the composite optical waveguide wiring layer 301, a first metal connector 105 electrically connected to the first circuit region 101a, and a first waveguide optical port 106 exposing the composite optical waveguide wiring layer 301, a second circuit region 201a located above the composite optical waveguide wiring layer 301, a second metal connector 205 electrically connected to the second circuit region 201a, and a second waveguide optical port 206 exposing the composite optical waveguide wiring layer 301, where the first waveguide optical port 106 is disposed corresponding to a first photosensitive region 310 of the first optical chip 300 for optical transmission; the second optical chip 500 is bonded to the circuit substrate 200 and electrically connected to the metal wiring layer 400 and the second metal connector 205, and the second photosensitive region 510 of the second optical chip 500 is disposed corresponding to the second waveguide optical port 206 for optical transmission.
As an example, a light shielding layer (not shown) covering the composite optical waveguide wiring layer 301 may be further included.
The light-shielding protection layer may include a metal light-shielding protection layer, for example, a metal light-shielding protection layer made of copper, gold, aluminum, silver, platinum, titanium, or the like, or the composite light-shielding protection layer may be an organic-inorganic composite light-shielding protection layer, so as to protect the composite optical waveguide wiring layer 301 through the light-shielding protection layer, thereby reducing light loss.
As an example, the composite optical waveguide wiring layer may include an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer.
As an example, a third metal connector 600 electrically connected to the circuit substrate 200 may be further included, and the third metal connector 600 may include a metal bump, a metal post, etc., which is not limited herein.
In summary, according to the double-sided photoelectric interconnection packaging structure and the preparation method thereof, the double-sided composite functional chip is prepared, so that the composite optical waveguide wiring layer is arranged inside the double-sided composite functional chip to be combined with the optical chip for optical transmission, and the circuit areas on the upper side and the lower side of the composite optical waveguide wiring layer of the double-sided composite functional chip are combined with the metal connecting pieces to be electrically transmitted with the optical chip and the circuit substrate, so that photoelectric interconnection integration is realized, the packaging size is reduced, the power consumption is reduced, the reliability is improved, and the double-sided photoelectric interconnection packaging structure is suitable for high-density integrated packaging, and good photoelectric signal transmission can be realized.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. The preparation method of the double-sided photoelectric interconnection packaging structure is characterized by comprising the following steps of:
providing a first wafer-level electric chip and a second wafer-level electric chip, wherein the first wafer-level electric chip comprises a first circuit area positioned at the top and a first substrate area positioned at the bottom, and the second wafer-level electric chip comprises a second circuit area positioned at the top and a second substrate area positioned at the bottom;
patterning the first wafer level electrical chip to form a first recess in the first substrate region and patterning the second wafer level electrical chip to form a second recess in the second substrate region;
forming a first optical waveguide wiring layer in the first groove, and forming a second optical waveguide wiring layer in the second groove;
bonding the first wafer-level electrical chip and the second wafer-level electrical chip, and connecting the first optical waveguide wiring layer and the second optical waveguide wiring layer to form a composite optical waveguide wiring layer;
patterning from the top of the first wafer level electrical chip to form a first waveguide optical port exposing the composite optical waveguide wiring layer, and patterning from the top of the second wafer level electrical chip to form a second waveguide optical port exposing the composite optical waveguide wiring layer;
forming a first metal connecting piece on the surface of the first circuit area, wherein the first metal connecting piece is electrically connected with the first circuit area, and forming a second metal connecting piece on the surface of the second circuit area, wherein the second metal connecting piece is electrically connected with the second circuit area;
cutting to form a double-sided composite functional chip;
providing a circuit substrate, wherein a first optical chip is arranged in the circuit substrate;
forming a metal wiring layer on the circuit substrate, wherein the metal wiring layer is electrically connected with the first optical chip and the circuit substrate, and the metal wiring layer exposes a first photosensitive area of the first optical chip;
bonding the double-sided composite functional chip on the circuit substrate, wherein the first metal connecting piece is electrically connected with the metal wiring layer, and the first waveguide optical port is correspondingly arranged with the first photosensitive area;
and providing a second optical chip, bonding the second optical chip on the circuit substrate, wherein the second optical chip is electrically connected with the metal wiring layer and the second metal connecting piece, and a second photosensitive area of the second optical chip is arranged corresponding to the second waveguide optical port.
2. The method for manufacturing the double-sided photoelectric interconnection packaging structure according to claim 1, wherein the method comprises the following steps: the composite optical waveguide wiring layer is in axisymmetric graph along the bonding surface or in asymmetric graph along the bonding surface.
3. The method for manufacturing the double-sided photoelectric interconnection packaging structure according to claim 1, wherein the method comprises the following steps: the method further comprises the step of forming a first shading protection layer covering the bottom and the side wall of the first groove; and/or further comprising the step of forming a second light-shielding protection layer covering the bottom and the side wall of the second groove.
4. The method for manufacturing a double-sided optoelectronic interconnect package structure as set forth in claim 3, wherein: the method for forming the first light-shielding protective layer comprises a semiconductor exposure development method, wherein the formed first light-shielding protective layer comprises a metal first light-shielding protective layer or an organic-inorganic composite first light-shielding protective layer; the method for forming the second light-shielding protective layer comprises a semiconductor exposure development method, and the formed second light-shielding protective layer comprises a metal second light-shielding protective layer or an organic-inorganic composite second light-shielding protective layer.
5. The method for manufacturing the double-sided photoelectric interconnection packaging structure according to claim 1, wherein the method comprises the following steps: the method for forming the first optical waveguide wiring layer comprises a semiconductor exposure and development method, wherein the formed first optical waveguide wiring layer comprises an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer or a lithium borate optical waveguide wiring layer; the method of forming the second optical waveguide wiring layer includes a semiconductor exposure developing method, and the formed second optical waveguide wiring layer includes an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer, or a lithium borate optical waveguide wiring layer.
6. The method for manufacturing the double-sided photoelectric interconnection packaging structure according to claim 1, wherein the method comprises the following steps: the method for cutting to form the double-sided composite functional chip comprises a mechanical cutting method or a laser cutting method.
7. The method for manufacturing the double-sided photoelectric interconnection packaging structure according to claim 1, wherein the method comprises the following steps: and forming a third metal connector electrically connected with the circuit substrate.
8. A double-sided optoelectronic interconnect assembly formed by the method of any one of claims 1-7, wherein the double-sided optoelectronic interconnect assembly comprises:
a circuit substrate in which a first optical chip is disposed;
the metal wiring layer is positioned on the circuit substrate, is electrically connected with the first optical chip and the circuit substrate, and exposes the first photosensitive area of the first optical chip;
the double-sided composite functional chip is bonded on the circuit substrate and comprises a composite optical waveguide wiring layer, a first circuit area, a first metal connecting piece and a first waveguide light port, wherein the first circuit area is positioned below the composite optical waveguide wiring layer, the first metal connecting piece is electrically connected with the first circuit area, the first waveguide light port is exposed out of the composite optical waveguide wiring layer, the second circuit area is positioned above the composite optical waveguide wiring layer, the second metal connecting piece is electrically connected with the second circuit area, the second waveguide light port is exposed out of the composite optical waveguide wiring layer, and the first waveguide light port and the first photosensitive area of the first optical chip are correspondingly arranged;
the second optical chip is bonded on the circuit substrate and electrically connected with the metal wiring layer and the second metal connecting piece, and a second photosensitive area of the second optical chip is arranged corresponding to the second waveguide optical port.
9. The dual sided optoelectronic interconnect assembly of claim 8, wherein: the light shielding protective layer is used for covering the composite optical waveguide wiring layer.
10. The dual sided optoelectronic interconnect assembly of claim 8, wherein: the composite optical waveguide wiring layer comprises an organic polymer optical waveguide wiring layer, a silicon-based optical waveguide wiring layer, a lithium niobate optical waveguide wiring layer or a lithium borate optical waveguide wiring layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311360935.6A CN117096038B (en) | 2023-10-20 | 2023-10-20 | Double-sided photoelectric interconnection packaging structure and preparation method thereof |
| PCT/CN2024/078004 WO2025081694A1 (en) | 2023-10-20 | 2024-02-22 | Double-sided optoelectronic interconnection packaging structure and preparation method therefor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311360935.6A CN117096038B (en) | 2023-10-20 | 2023-10-20 | Double-sided photoelectric interconnection packaging structure and preparation method thereof |
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| JP2012013819A (en) * | 2010-06-30 | 2012-01-19 | Kyocera Corp | Optical transmission substrate and light-receiving module |
| CN103293127A (en) * | 2013-05-16 | 2013-09-11 | 电子科技大学 | SOI (silicon-on-insulator)-based multi-slit optical waveguide grating FP (Fabry-Perot) cavity optical biochemical sensor chip |
| CN203385668U (en) * | 2013-05-16 | 2014-01-08 | 成都谱视科技有限公司 | Slit waveguide series grating FP (Fabry-Perot) cavity optical biochemical sensor chip |
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| JP4825739B2 (en) * | 2007-06-22 | 2011-11-30 | 株式会社日立製作所 | Structure of opto-electric hybrid board and opto-electric package |
| US8211732B2 (en) * | 2008-09-11 | 2012-07-03 | Omnivision Technologies, Inc. | Image sensor with raised photosensitive elements |
| JP5493744B2 (en) * | 2009-11-12 | 2014-05-14 | 富士通株式会社 | Opto-electric hybrid board and method for manufacturing opto-electric hybrid board |
| CN110389121A (en) * | 2019-07-24 | 2019-10-29 | 中国科学院半导体研究所 | Fluorescence imaging system with multi-focus structured light illumination |
| CN218938553U (en) * | 2022-10-19 | 2023-04-28 | 深南电路股份有限公司 | Photoelectric co-packaging structure |
| CN115588618B (en) * | 2022-12-06 | 2023-03-10 | 盛合晶微半导体(江阴)有限公司 | Three-dimensional stacked photoelectric packaging structure and preparation method |
| CN116449506A (en) * | 2023-02-22 | 2023-07-18 | 深南电路股份有限公司 | Photoelectric hybrid integrated device based on glass substrate and manufacturing method thereof |
| CN117096038B (en) * | 2023-10-20 | 2024-01-30 | 盛合晶微半导体(江阴)有限公司 | Double-sided photoelectric interconnection packaging structure and preparation method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012013819A (en) * | 2010-06-30 | 2012-01-19 | Kyocera Corp | Optical transmission substrate and light-receiving module |
| CN103293127A (en) * | 2013-05-16 | 2013-09-11 | 电子科技大学 | SOI (silicon-on-insulator)-based multi-slit optical waveguide grating FP (Fabry-Perot) cavity optical biochemical sensor chip |
| CN203385668U (en) * | 2013-05-16 | 2014-01-08 | 成都谱视科技有限公司 | Slit waveguide series grating FP (Fabry-Perot) cavity optical biochemical sensor chip |
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| WO2025081694A1 (en) | 2025-04-24 |
| CN117096038A (en) | 2023-11-21 |
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