CN117080247A - Gallium nitride heterojunction field effect transistor, manufacturing method and electronic device - Google Patents

Abstract

Embodiments of the present application provide a gallium nitride heterojunction field effect transistor, a manufacturing method and electronic equipment, and relate to the field of semiconductor technology. Gallium nitride heterojunction field effect transistors solve the problem of incompatibility between appropriate threshold voltage and low on-resistance, as well as the problem of large gate leakage current. The gallium nitride heterojunction field effect transistor includes: a channel layer and a barrier layer. The barrier layer is disposed on one side of the channel layer. The barrier layer includes a groove, and a first part and a barrier layer respectively disposed on both sides of the groove. In the second part, a two-dimensional electron gas is formed on the interface between the channel layer and the first part and the second part respectively. The first drain electrode is disposed on a side of the first part away from the channel layer. The second drain electrode is disposed on a side of the second part away from the channel layer. The first dielectric layer is at least disposed on the inner surface of the groove. The gate electrode is arranged in the groove.

Description

Gallium nitride heterojunction field effect transistor, manufacturing method and electronic device

Technical field

The present application relates to the field of semiconductor technology, and in particular to a gallium nitride heterojunction field effect transistor, a manufacturing method and electronic equipment.

Background technique

With the development of technology, portable mobile terminals are constantly progressing in the direction of miniaturization and thinness. For portable mobile terminals with both wired charging and wireless charging functions, a two-way on-off module should be installed on the wired charging input end and wireless charging input end of the circuit board respectively. In order to save the circuit board of the portable mobile terminal Space, a transistor with two drains can be used as a bidirectional on-off module.

When the above-mentioned transistors need to be turned on, a voltage value above the threshold voltage needs to be applied between the gate and the drain, thereby establishing a conductive channel in the barrier layer and the channel layer, and conducting the circuit where the transistor is located through the conductive channel. Transistors in the related art often have the problem of not having both a suitable threshold voltage and low on-resistance, as well as the problem of large gate leakage current. The above problems need to be solved urgently.

Contents of the invention

In order to solve the above technical problems, this application provides a gallium nitride heterojunction field effect transistor, a manufacturing method and an electronic device, which can solve the problem of incompatibility of appropriate threshold voltage and low on-resistance, as well as the relatively low gate leakage current. Big question.

In a first aspect, this application provides a gallium nitride heterojunction field effect transistor, including: a channel layer, the material of the channel layer is gallium nitride; a barrier layer, the barrier layer is disposed on one side of the channel layer , the barrier layer includes a groove, and a first part and a second part respectively provided on both sides of the groove, the groove at least includes a first opening, the opening direction of the first opening is away from the direction of the channel layer, and the channel layer is respectively connected with A two-dimensional electron gas is formed on the interface between the first part and the second part; a first drain electrode, the first drain electrode is arranged on the side of the first part away from the channel layer, and the material of the first drain electrode is a conductive material; the second drain electrode pole, the second drain electrode is disposed on the side of the second part away from the channel layer, and the material of the second drain electrode is a conductive material; the first dielectric layer is disposed at least on the inner surface of the groove, and the first dielectric layer The material of the gate electrode is an insulating material; the gate electrode is arranged in the groove, and the material of the gate electrode is a conductive material.

The barrier layer of the transistor is provided with grooves, which intercept the two-dimensional electron gas in the first and second parts of the barrier layer, so that the conductive channel will not be easily established and the threshold voltage will be maintained at a high level. Therefore, even if the channel layer is kept thick, it will not cause an excessive drop in the threshold voltage. And because the barrier layer is thicker, the concentration of the two-dimensional electron gas will be higher and the on-resistance will be smaller. This setting not only ensures the concentration of the two-dimensional electron gas in the barrier layer, making the on-resistance of the transistor low, but also ensures that the threshold voltage will not be too low. Moreover, since an insulating first dielectric layer is provided between the gate electrode and the semiconductor material, the first dielectric layer can block the current between the metal gate electrode and the semiconductor material layer, thus greatly reducing the gate leakage current.

In some possible implementations, the material of the barrier layer is Al _y Ga _1-y N, where Al is aluminum, Ga is gallium, N is nitrogen, and the value range of y is 0<y≤1. The material of the barrier layer can be flexibly determined according to actual needs, making it easy to adjust the electrical properties of the transistor through material adjustment.

In some possible implementations, the material of the first dielectric layer includes silicon nitride, aluminum oxide, aluminum nitride, silicon dioxide or hafnium dioxide. The material of the first dielectric layer can be flexibly determined according to actual needs.

In some possible implementations, the depth of the groove is the same as the thickness of the barrier layer. The barrier layer at the groove can be completely dug out, thereby better blocking the two-dimensional electron gas between the barrier layer and the channel layer.

In some possible implementations, a first gate field plate is also included. The first gate field plate is connected to the gate, and both sides of the first gate field plate are respectively facing the direction of the first drain and the second drain. Extending in the direction, a first dielectric layer is provided between the first gate field plate and the barrier layer. The first gate field plate can adjust the electric field distribution between the gate electrode, the first drain electrode and the second drain electrode, and reduce the intensity of the electric field in local parts of the gate electrode, thereby preventing the local electric field from being too dense and causing a gap between the gate electrode and the drain electrode. breakdown. This makes the electric field evenly distributed and increases the voltage resistance of the transistor.

In some possible implementation methods, a second dielectric layer and a second gate field plate are also included. The second gate field plate is arranged relative to the first gate field plate, and the second gate field plate is connected to the first drain electrode and the first gate field plate respectively. A second dielectric layer is provided between the second drain electrode and the first gate field plate, and the second gate field plate, the first gate field plate and the gate electrode are all electrically connected. Adding a second gate field plate to the first gate field plate can make the electric field distribution between the gate and the drain more uniform, further increasing the voltage resistance of the transistor.

In some possible implementations, the material of the second dielectric layer includes silicon nitride, aluminum oxide, aluminum nitride, silicon dioxide or hafnium dioxide. The material of the second dielectric layer can be flexibly determined according to actual needs.

In some possible implementations, a transition layer is also included, and the transition layer is disposed on a side of the channel layer away from the barrier layer. By setting up a transition layer, the inter-crystal stress caused by the difference between the substrate crystal material and the channel layer crystal material can be released, and the distance between the gate and the substrate can be increased to avoid breakdown of the transistor.

In some possible implementations, the transition layer includes a transition layer body and a nucleation layer. The transition layer body is disposed on a side of the channel layer away from the barrier layer. The nucleation layer is disposed on a side of the transition layer body away from the channel layer. . By setting the nucleation layer, it is more conducive to the growth of the transition layer.

In some possible implementations, the material of the transition layer body includes aluminum gallium nitride with graded aluminum composition, N-type gallium nitride, homogeneous aluminum gallium nitride or superlattice aluminum gallium nitride; the material of the nucleation layer includes nitride Gallium or aluminum nitride. The material of the transition layer can be flexibly determined according to actual needs, making it easy to adjust the electrical properties of the transistor through material adjustment.

In some possible implementations, a substrate is further included, and the substrate is disposed on a side of the transition layer away from the channel layer. By arranging the substrate, it is more conducive to the formation of transistors.

In a second aspect, a method for manufacturing a gallium nitride heterojunction field effect transistor is provided, which is used to manufacture any of the above-mentioned gallium nitride heterojunction field effect transistors, including: preparing a channel layer; Barrier layer; a groove is provided on the side of the barrier layer away from the channel layer at a position corresponding to the gate; a first dielectric layer is formed on the inner surface of the groove and the side of the barrier layer away from the channel layer; Remove the first dielectric layer at positions corresponding to the first drain electrode and the second drain electrode; form the first drain electrode and the second drain electrode to form a gate electrode. The above-mentioned manufacturing method adopts the method of forming a film layer first and then removing unnecessary parts. It can reduce manufacturing costs and improve production efficiency during the manufacturing process of each film layer.

In some possible implementations, after forming the gate, the method further includes forming a first gate field plate on the side with the gate. The formation of the gate electrode and the formation of the first gate field plate can be completed in two steps, thereby improving the quality of the first gate field plate.

In some possible implementations, forming the first gate field plate on the side with the gate electrode includes forming a photoresist on the side with the gate electrode, and exposing the area where the first gate field plate is to be prepared, and then The area where the first gate field plate is prepared uses a sputtering or evaporation process to form the first gate field plate. By occupying the photoresist, the first gate field plate can be shaped into a desired shape.

In some possible implementation methods, it also includes forming a second dielectric layer on a side of the first gate field plate away from the gate, and forming a second gate on a side of the second dielectric layer away from the first gate field plate. Field board.

In some possible implementations, forming the second gate field plate on a side of the second dielectric layer away from the first gate field plate includes forming photolithography on a side of the second dielectric layer away from the first gate field plate. glue, and expose the area where the second gate field plate is to be prepared, and use a sputtering or evaporation process to form the second gate field plate in the area where the second gate field plate is to be prepared. By occupying the photoresist and the second dielectric layer, the second gate field plate can be shaped into a desired shape.

In some possible implementation methods, creating the groove includes forming a photoresist on the side of the barrier layer away from the channel layer, and exposing the part where the groove is to be formed, and forming a photoresist on the side of the barrier layer away from the channel layer. Etch to form grooves. Through the etching process, the grooves of the barrier layer can be formed into the required shape, and there is no need to mold the barrier layer at one time, thus reducing production costs.

In some possible implementations, removing the first dielectric layer at positions corresponding to the first drain electrode and the second drain electrode includes forming a photoresist on a side of the first dielectric layer away from the channel layer, and exposing the exposed area to be Forming portions of the first drain electrode and the second drain electrode. Through the etching process, the first dielectric layer can be formed into a desired shape without the need to shape the first dielectric layer at one time, thereby reducing production costs.

In some possible implementation methods, before preparing the channel layer, it also includes: obtaining a substrate; forming a nucleation layer on the surface of the substrate through vapor phase epitaxial growth technology; and growing the transition layer body on the side of the nucleation layer away from the substrate. . Vapor phase epitaxial growth technology is more conducive to the formation of crystal lattice, not only improving the crystal quality of the nucleation layer, but also improving the bulk crystal quality of the transition layer grown on the nucleation layer.

A third aspect provides an electronic device using any of the above-mentioned gallium nitride heterojunction field effect transistors. Because the transistor is smaller, it can reduce the area occupied on the PCB of the electronic device and improve the integration of the electronic device while ensuring its electrical performance.

Description of the drawings

Figure 1 is a schematic front structural view of an electronic device provided by an embodiment of the present application;

Figure 2 is a schematic structural diagram of the reverse side of the electronic device provided by the embodiment of the present application;

Figure 3 is a schematic structural diagram of a charging circuit provided by related technologies;

Figure 4 is a schematic structural diagram of a high electron mobility transistor provided by related technologies;

Figure 5 is a schematic diagram of the process of preparing the transition layer provided by the embodiment of the present application;

Figure 6 is a schematic diagram of the process of preparing a channel layer according to an embodiment of the present application;

Figure 7 is a schematic diagram of the process of preparing a barrier layer according to an embodiment of the present application;

Figure 8 is a schematic diagram of the process of forming grooves provided by an embodiment of the present application;

Figure 9 is a schematic diagram of the process of preparing the first dielectric layer according to the embodiment of the present application;

Figure 10 is a schematic diagram of the process of removing part of the first dielectric layer according to an embodiment of the present application;

Figure 11 is a schematic diagram of the process of preparing the first drain electrode and the second drain electrode according to the embodiment of the present application;

Figure 12 is a schematic diagram of the process of preparing a gate electrode according to an embodiment of the present application;

Figure 13 is a schematic diagram of the process of preparing a first gate field plate according to an embodiment of the present application;

Figure 14 is a schematic diagram of the process of preparing a second gate field plate and a second dielectric layer according to an embodiment of the present application;

Figure 15 is a schematic diagram of the device in the first scenario provided by the embodiment of the present application;

Figure 16 is a schematic structural diagram of the charging circuit in the second scenario provided by the embodiment of the present application.

Reference signs:

001-display; 002-battery cover; 003-middle frame;

USB_IN-wired charging interface; RX_IN-wireless charging interface;

1-Driver device; 2-First transistor; 3-Second transistor;

601-Existing substrate; 602-Existing nucleation layer; 603-Existing buffer layer; 604-Existing channel layer; 605-Existing barrier layer; 606-First semiconductor layer; 607-First insulation Dielectric layer; 608-first field plate; 609-first field plate extension metal; 610-first drain electrode; 611-second drain electrode;

11-Substrate; 12-Transition layer; 1201-Nucleation layer; 1202-Transition layer body; 13-Channel layer; 14-Barrier layer; 1401-First part; 1402-Second part; 15-First medium layer; 16-first drain; 17-second drain; 18-gate; 19-first gate field plate; 20-second dielectric layer; 21-second gate field plate;

G-gate pin; D1-first drain pin; D2-second drain pin.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

The term "and/or" in this article is just an association relationship that describes related objects, indicating that three relationships can exist. For example, A and/or B can mean: A exists alone, A and B exist simultaneously, and they exist alone. B these three situations.

The terms “first” and “second” in the description and claims of the embodiments of this application are used to distinguish different objects, rather than to describe a specific order of objects. For example, the first target object, the second target object, etc. are used to distinguish different target objects, rather than to describe a specific order of the target objects.

In the embodiments of this application, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "such as" in the embodiments of the present application is not to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the words "exemplary" or "such as" is intended to present the concept in a concrete manner.

In the description of the embodiments of this application, unless otherwise specified, the meaning of “plurality” refers to two or more. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

Embodiments of the present application provide an electronic device. The electronic device may be a mobile phone, a computer, a tablet, a personal digital assistant (PDA), a vehicle-mounted computer, a television, a smart wearable device, a smart home device, etc. Electronic equipment. Taking the electronic device as a mobile phone as an example, the structure of the electronic device is introduced below.

Referring to Figures 1 and 2, an exemplary electronic device may be a mobile phone with a wireless charging function, including a display screen 001, a battery cover 002 and a middle frame 003, which form a receiving cavity, and may be provided with a A battery (not shown in the figure), a wireless charging coil (not shown in the figure) and a printed circuit board (PCB) (not shown in the figure). The PCB is provided with circuits for controlling charging of electronic devices. Refer to Figure 3, taking a mobile phone as an example. For a mobile phone charging channel with both wired and wireless charging, in order to control the charging channel on and off and avoid wired charging and wireless charging currents flowing into each other, it is necessary to connect the line where the wired charging interface USB_IN is located and the wireless charging channel. The lines where the interface RX_IN is located are respectively equipped with devices that can achieve bidirectional conduction or shutdown, and the conduction or shutdown of the two-phase conduction or shutdown device is controlled by driving device 1. The more common MOS tube can be used as the turn-on or turn-off device. However, due to the existence of parasitic diodes in MOS tubes, a single MOS tube cannot achieve bidirectional conduction or shutdown. Therefore, two N-shaped MOS tubes can be set up in a circuit that needs to be turned on or off in two directions. The sources of the two MOS tubes are connected to each other. The gates of the two MOS tubes are connected to one end of the driving device 1. The driving device 1. Turn on or off two MOS tubes at the same time. In this way, the line where the wired charging interface USB_IN is located and the line where the wireless charging interface RX_IN is located can be turned on or off in two directions respectively.

However, with the development of technology, electronic equipment is becoming more and more integrated, and the area on the motherboard where devices can be placed is becoming increasingly tight. The solution of setting up two MOS tubes takes up too much motherboard area, and some electronic equipment cannot be allocated on the motherboard. Make space for two MOS tubes. Referring to Figure 4, based on the above problems, a high electron mobility transistor is provided in the related art. This transistor can include from bottom to top: an existing substrate 601, and an existing nucleation epitaxial epitaxial structure on the existing substrate 601. Layer 602, existing buffer layer 603 epitaxially over existing nucleation layer 602, existing channel layer 604 epitaxially over existing buffer layer 603, and existing barrier epitaxially over existing channel layer 604 Layer 605. The gate structure layer may include: a first semiconductor layer 606 and a first insulating dielectric layer 607. The thickness of the first insulating dielectric layer 607 is smaller than the thickness of the first semiconductor layer 606. The field plate layer may include: a first field plate 608 and a first field plate extension metal 609. The first field plate 608 and the first field plate extension metal 609 may form an inverted U-shaped grid extending from the first field plate 608 to both sides. Field plate structure. It also includes a first drain electrode 610 and a second drain electrode 611 symmetrically distributed on both sides of the gate structure layer. It is easy to find from the above structure that the channel two-dimensional electron gas concentration is positively related to the structural thickness of the existing barrier layer 605. However, if the existing barrier layer 605 is too thick, the conductive channel will be easily established and the threshold voltage will decrease. In order to maintain a reasonable threshold voltage, the existing barrier layer 605 needs to be appropriately thinned, so that the concentration of the two-dimensional electron gas in the channel decreases and the impedance per unit area increases. Furthermore, since the first field plate 608 and the first semiconductor layer 606 are in direct contact, the leakage current of the gate is large and the gate withstand voltage is poor. It can be seen that the structural features in related technologies have led to several technical problems, including the problem that the ideal threshold voltage and the ideal device on-resistance cannot be achieved at the same time; and the gate leakage current is large and the gate withstand voltage is poor. question.

Referring to Figure 5, in view of this, an embodiment of the present invention provides a gallium nitride (GaN) heterojunction field effect transistor (HFET) (hereinafter referred to as a transistor). The transistor may include a substrate 11, which may be made of silicon, carbon A substrate 11 made of silicon, sapphire or gallium nitride, etc., and then a transition layer 12 is formed on the surface of the substrate 11. When forming the transition layer 12, a new vapor phase epitaxial growth technology (MOCVD) can be used to deposit nucleation on the substrate 11 Layer 1201, thereby forming a film layer having a lattice structure corresponding to the nucleation layer material. The nucleation layer material can be gallium nitride (GaN) or aluminum nitride (AlN). However, since the crystal structure of the substrate 11 and the nucleation layer 1201 are different, their lattice constants, that is, the physical dimensions of the unit cells, are different. This will cause a lattice mismatch in the lattice structure of the crystal grown on the substrate 11 . The stress between the crystals grown in this way is relatively large. In order to grow crystals with a relaxed stress state, it is necessary to continue to grow the transition layer body 1202 on the basis of the nucleation layer 1201. The growth methods and materials of the transition layer body 1202 can be diverse. For example, an aluminum gallium nitride (AlGaN) transition layer body 1202 of graded aluminum composition can be grown on the side of the nucleation layer 1201 away from the substrate 11 . It can be set that the aluminum component is the highest on the side close to the nucleation layer 1201, until it transitions to the surface of the transition layer body 1202 away from the nucleation layer 1201, and the aluminum component is zero. Alternatively, N-type gallium nitride material formed by doping carbon (C) or iron (Fe) can also be grown on the side of the nucleation layer 1201 away from the substrate 11 . Alternatively, a homogeneous aluminum gallium nitride material with a proportion of aluminum and gallium selected according to actual needs can also be grown on the side of the nucleation layer 1201 away from the substrate 11 . Alternatively, the superlattice aluminum gallium nitride material can also be grown on the side of the nucleation layer 1201 away from the substrate 11 , that is, two materials can be alternately formed on the nucleation layer 1201 . For example, 20 nanometers of gallium nitride and 20 nanometers of aluminum gallium nitride can be alternately formed on the nucleation layer 1201 . Of course, the above examples only give some materials and growth methods of the transition layer 12 , and the transition layer 12 can also be made of other materials and produced by other growth methods. It can also be obtained by a combination of the above methods. For example, the superlattice structure can be prepared during the process of growing the aluminum gallium nitride transition layer body 1202 of graded aluminum composition on the side of the nucleation layer 1201 away from the substrate 11 . The embodiments of the present invention are not limited to the specific materials and preparation methods of the transition layer 12 . During the growth process of the transition layer body 1202, the stress between newly grown crystals gradually decreases, the unit cells gradually become regular and consistent, and the lattice mismatch gradually disappears. This can reduce the stress between crystals and relax the lattice. Due to the existence of the transition layer body 1202, the dislocations of the nucleation layer 1201 are shielded and the stress caused by the lattice mismatch is released. At the same time, it also provides high resistance in the height direction of the transistor.

Referring to FIG. 6 , after the transition layer 12 is produced, the channel layer 13 can be epitaxially grown on the side of the transition layer 12 away from the substrate 11 . The material of the channel layer 13 can be pure gallium nitride (iGaN). During epitaxy, the gallium nitride material is not doped in any way and maintains lattice relaxation and maintains high material quality. The thickness of the channel layer 13 can be determined according to actual needs.

Referring to FIG. 7 , after the channel layer 13 is formed, a barrier layer 14 can be epitaxially grown on the side of the channel layer 13 away from the transition layer 12 . A two-dimensional electron gas is formed at the interface between the barrier layer 14 and the channel layer 13 . The electrons in the two-dimensional electron gas can move planarly along the interface between the barrier layer 14 and the channel layer 13 . Among them, the movement of the electron group in one direction is limited to a small range, and the system that can move freely on a plane perpendicular to this direction is called a two-dimensional electron system. If the electron density in the system is low, it is called a two-dimensional electron gas. For example, the material of the barrier layer 14 may be Al _y Ga _1-y N, where the value range of y is 0<y≤1. In other words, the material of the barrier layer 14 can be aluminum nitride or aluminum gallium nitride, and the ratio of aluminum and gallium can be determined according to actual needs. Since the material of the barrier layer 14 is different from the material of the channel layer 13, there is a lattice mismatch phenomenon in the barrier layer 14. The advantage of this is that the barrier layer 14 can maintain the stress state without relaxing to form a piezoelectric polarization. Taking the material of the barrier layer 14 as aluminum gallium nitride as an example, since the lattice constant of the aluminum gallium nitride material is between aluminum nitride and gallium nitride, when aluminum gallium nitride is grown on the gallium nitride material, the aluminum gallium nitride The material will be subjected to tensile stress in the transverse direction, and the aluminum gallium nitride material will be compressed in the longitudinal direction. This further increases the distance between the non-overlapping positive and negative centers of the material itself, resulting in a piezoelectric polarization effect. Such an arrangement can form a two-dimensional electron gas at the interface between the barrier layer 14 and the channel layer 13, thereby obtaining a conductive channel with high electron mobility.

Referring to Figure 8, after the barrier layer 14 is formed, a groove needs to be etched in the barrier layer 14 at the position where the gate 18 needs to be accommodated. The groove divides the barrier layer 14 into a first part 1401 and a second part on both sides of the groove. Part 1402. The process of forming the groove can be any etching process, such as chemical etching process, etc. The etching depth of the groove can be determined according to actual needs. The barrier layer 14 can be entirely etched away in the area where the groove is located, or a certain thickness can be retained. Providing the groove can cut off the two-dimensional electron gas in the channel layer 13, allowing the transistor to remain in an off state without external voltage being applied.

Referring to FIG. 9 , after forming the groove, a first dielectric layer 15 may be formed on the surface of the barrier layer 14 and the surface of the groove. The first dielectric layer 15 can be formed in any manner. For example, the first dielectric layer 15 can be formed by plasma enhanced chemical vapor deposition (PECVD). Specifically, this method is a method of depositing a semiconductor thin film material by performing a chemical reaction on the surface of the barrier layer 14 and the surface of the groove after forming ionization using glow discharge in a deposition chamber. Plasma-enhanced chemical vapor deposition is a method of epitaxy in chemical vapor deposition that excites gas to generate low-temperature plasma and enhance the chemical activity of reactive substances. This method can form solid films at lower temperatures. For example, in a reaction chamber, the matrix material is placed on the cathode, the reaction gas is introduced to a lower pressure (1~600Pa), the matrix is maintained at a certain temperature, and a glow discharge is generated in a certain way. The gas near the surface of the matrix is ionized, and the reaction gas is obtained Activation, while cathode sputtering occurs on the surface of the substrate, thereby improving surface activity. Not only common thermochemical reactions occur on the surface, but also complex plasma chemical reactions occur. The deposited film is formed under the combined action of these two chemical reactions. In addition to the above method, the first dielectric layer 15 can also be formed using a low pressure chemical vapor deposition (LPCVD) method. When using low-pressure chemical vapor deposition, one or more gaseous precursors (chemical gases) need to be introduced into the reaction chamber. This step is performed at a lower pressure, usually below atmospheric pressure. This helps increase reaction speed and uniformity, as well as improve film quality. Gas flow and pressure are often precisely regulated by dedicated controllers and valves. The choice of gas determines the properties of the resulting film. The gas precursor molecules are adsorbed on the surface of the barrier layer 14 and the groove surface. Adsorption is the process by which precursor molecules settle on and interact with the substrate surface. Specifically, molecules transfer from the gas phase to the solid phase without actually integrating into the solid phase. Adsorption includes physical adsorption and chemical adsorption. Then, at a set temperature, the precursor adsorbed on the surface of the barrier layer 14 and the surface of the groove undergoes a chemical reaction to form a thin film deposited on the surface. These reactions can be decomposition reactions, displacement reactions, reduction reactions, etc. The specific reaction types depend on the type of gas and reaction conditions. The substance generated by the reaction forms a thin film and is uniformly deposited on the surface of the barrier layer 14 and the surface of the groove. The first dielectric layer 15 may also be formed by atomic layer deposition (ALD). This is a method in which substances are deposited layer by layer on the surface of a substrate in the form of a single-atom film. Atomic layer deposition has similarities to ordinary chemical deposition. But in the atomic layer deposition process, the chemical reaction of the new layer of atomic film is directly related to the previous layer. This way, only one layer of atoms is deposited in each reaction. The material of the first dielectric layer 15 may be insulating silicon nitride (SiN _x ), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), silicon dioxide (SiO ₂ ) or hafnium dioxide (HfO ₂ ). Material. Various formation processes of the first dielectric layer 15 and materials of the first dielectric layer 15 are given above. The above processes and materials are only examples. The embodiments of the present invention are not specific to the formation process of the first dielectric layer 15 and the first dielectric layer. 15 materials are limited.

Referring to FIG. 10 , after the first dielectric layer 15 is formed, part of the first dielectric layer 15 needs to be removed to form the first drain electrode 16 and the second drain electrode 17 . The first drain electrode is electrically connected to the first portion 1401 of the barrier layer 14 , and the second drain electrode is electrically connected to the second portion 1402 of the barrier layer 14 . There are various ways to remove the regions of the first dielectric layer 15 corresponding to the first drain electrode 16 and the second drain electrode 17 . In the production process of transistors, multiple transistors are often gathered on a wafer. After production is complete, the wafers need to be diced into individual transistors. For example, photoresist may be formed on the surface of the first dielectric layer 15 away from the barrier layer 14 , and the photoresist may be disposed on the other first media except the areas corresponding to the first drain electrode 16 and the second drain electrode 17 On level 15. The formation of the photoresist may include the following steps: coating a photoresist film on the surface of the first dielectric layer 15, and then attaching a mask with a preset hollow pattern to the first dielectric layer 15, using ultraviolet light to The mask is illuminated for exposure. Ultraviolet light shines on the photoresist film through the hollow area of the eye template. At this time, a photoreaction occurs, resulting in a difference in solubility between the illuminated part and the non-illuminated part. The exposed wafer is then immersed in the developer. At this time, the exposed area of the positive glue and the non-exposed area of the negative glue will be dissolved during development. This presents a three-dimensional graphic. The developed wafer requires a high-temperature treatment process, which is called a hard film, and its main function is to further enhance the adhesion of the photoresist to the substrate 11 . Then, the wafer needs to be etched to remove the first dielectric layer 15 in the areas corresponding to the first drain electrode 16 and the second drain electrode 17 that are not protected by the photoresist. The etching operation can be liquid wet etching or gaseous dry etching. For wet etching, strong acid solutions are often used for etching; while dry etching often uses plasma or high-energy ion beams to cause damage to the material surface and cause etching. After the etching is completed, the photoresist still needs to be removed, all etching steps are completed, and the removal of the first dielectric layer 15 in the areas corresponding to the first drain electrode 16 and the second drain electrode 17 is completed.

Referring to Figure 11, after the first dielectric layer 15 in the corresponding areas of the first drain electrode 16 and the second drain electrode 17 is removed and the barrier layer 14 in the corresponding area is exposed, it is necessary to remove the first drain electrode 16 and the second drain electrode 17. Preparation of 17. Any process can be used to form the metal material in the regions corresponding to the first drain electrode 16 and the second drain electrode 17 of the barrier layer 14 respectively. For example, an ohmic junction may be formed through an ohmic contact process, thereby obtaining the first drain electrode 16 and the second drain electrode 17 made of metal. The ohmic contact process can be roughly divided into ion implantation process and epitaxial process. The ion implantation process generates positively charged impurity ions from raw materials. These impurity ions are accelerated by an electric field to obtain sufficient energy. In this way, the impurity ions can enter the target lattice, and then undergo a thermal annealing process to activate these impurities. ions, thereby achieving impurity doping of the base material. Since ion implantation can accurately control the concentration and depth of implanted impurities, it is more suitable for Moore's Law of increasingly smaller device sizes. Therefore, ion implantation plays an irreplaceable role in the process. However, ion implantation also has some disadvantages. One of them is that high-energy impurity ions bombard the substrate 11, which will still cause lattice damage despite annealing repairs. In addition, the high-precision control of impurity ions by ion implantation will inevitably lead to Comes with the complexity of the ion implanter. Epitaxy technology is to grow a single crystal layer on the substrate 11. According to the method of transporting atoms to the substrate 11, it can be basically divided into three methods: solid phase epitaxy (SolidPhase Exitaxy, SPE), vapor phase epitaxy (Vapor Phase Exitaxy, VPE) ) and liquid phase epitaxy (Liquid Phase Exitaxy, LPE). Different from ion implantation, according to different epitaxy methods, different instruments or methods can be selected for epitaxy. For example, for VPE method, different gas phase reactors or some chemical vapor deposition instruments can be used, while for LPE method, In other words, we can use liquid phase reactors or alloys, etc. Therefore, compared with the ion implantation method, epitaxy equipment is relatively simple and causes much less damage to the substrate 11 . It can be seen from the above that there are various implementation methods of the ohmic contact process, and specific processes can be selected for production and manufacturing according to actual needs.

Referring to FIG. 12 , after the step of forming the first dielectric layer 15 , the gate electrode 18 of the transistor still needs to be prepared. The gate 18 can be made of metal. The grid 18 can be prepared by sputtering or evaporation. Sputtering utilizes the characteristic of charged ions having a certain kinetic energy after being accelerated in an electric field to guide the ions to the target electrode to be sputtered. When the ion energy meets certain conditions, the incident ions will sputter out the target atoms from the surface during the collision with the target atoms. The sputtered atoms have a certain kinetic energy and will emit in a certain direction. To the area where the gate electrode 18 needs to be formed, the gate electrode 18 is formed in the groove. Evaporation is a process that uses a certain heating and evaporation method to evaporate the coating material (or film material) and vaporize it, and the particles fly to the groove surface of the wafer to condense. It has the advantages of simple film formation method, high film purity and density, and unique film structure and performance.

In order to ensure that the electrical characteristics when the current flows from the first drain electrode 16 through the second drain electrode 17 are consistent with the electrical characteristics when the second drain electrode 17 flows through the first drain electrode 16, the symmetry of the transistor structure should be ensured. That is, the transistors on both sides of the groove should be symmetrical to each other. If the structures of the transistors are symmetrical to each other, the electrical properties of both ends of the transistor can be guaranteed to be consistent.

The barrier layer 14 of the embodiment of the present invention is provided with grooves. The grooves intercept the two-dimensional electron gas in the first part 1401 and the second part 1402 of the barrier layer 14 so that the conductive channel will not be easily established and the threshold voltage will be maintained. at a higher level. Therefore, even if the channel layer 13 is kept thick, the threshold voltage will not decrease excessively. In addition, the thicker the barrier layer 14 is, the higher the concentration of the two-dimensional electron gas will be and the smaller the on-resistance will be. Such an arrangement not only ensures the concentration of the two-dimensional electron gas in the barrier layer 14, making the on-resistance of the transistor low, but also ensures that the threshold voltage will not be too low. Moreover, since the insulating first dielectric layer 15 is disposed between the gate electrode 18 and the semiconductor material, the first dielectric layer 15 can block the current between the metal gate electrode 18 and the semiconductor material layer, thus greatly reducing the leakage of the gate electrode 18. current.

Referring to FIG. 13 , in other embodiments, a first gate field plate 19 may be added, and the first gate field plate 19 is electrically connected to the gate 18 . When preparing the first gate field plate 19, it may be formed together with the preparation of the above-mentioned gate electrode 18. It is also possible to cover the area where the first gate field plate 19 is not required to be formed with photoresist after completing the preparation of the gate electrode 18 , and then form the first gate field plate 19 by sputtering or evaporation. The first gate field plate 19 extends in the direction of the first drain electrode 16 and the second drain electrode 17 respectively, and does not contact the first drain electrode 16 and the second drain electrode 17. The shape of the first gate field plate 19 and size can be determined according to actual needs. Due to the existence of the first gate field plate 19, the electric field distribution state of the gate 18 is changed, and the gate electric field is evenly distributed. The electric field spikes caused by the overly dense electric field between the edge of the gate electrode 18 and the first drain electrode 16 and the edge of the gate electrode 18 and the second drain electrode 17 are alleviated to a great extent. The electric field is evenly distributed, and the balanced electric field increases the voltage resistance of the transistor and improves the current collapse effect. Among them, the current collapse effect refers to the effect that when the first drain or second drain voltage of a transistor exceeds a certain value, as the drain voltage increases, the current begins to decrease and cannot reach the ideal value. In addition, because the structure itself has a stronger voltage resistance, a smaller chip size can be achieved at the same voltage level, thereby further reducing device cost and area.

In other embodiments, the number of gate field plates may be two or more layers, and all gate field plates are connected to the gate 18 . Referring to FIG. 14 , for example, two layers of gate field plates can be provided. The method of setting them can be to prepare a second dielectric layer 20 on the side of the wafer with the gate field plate after forming the gate field plate in the above embodiment. , and the second gate field plate 21 disposed in the second dielectric layer 20 . The material and preparation method of the second dielectric layer 20 can be the same as the first dielectric layer 15 ; the material and preparation method of the second gate field plate 21 can be the same as the first gate field plate 19 . For example, the second dielectric layer 20 can be formed on the side of the first gate field plate 19 away from the gate electrode 18 , and the cured photoresist can be formed on the side of the second dielectric layer 20 away from the first gate field plate 19 , this layer of cured photoresist only covers the area outside the second gate field plate 21 and can expose the area where the second gate field plate 21 is to be prepared. The second gate field plate 21 is formed using a sputtering or evaporation process in the area where the second gate field plate 21 is to be prepared.

The coverage area of the second gate field plate 21 may be larger than that of the first gate field plate 19 . The shape of the second gate field plate 21 may be set such that the height of both side edges of the second gate field plate 21 is slightly lower than the main body portion of the second gate field plate 21 . The advantage of this arrangement is that it can make the electric field optimization capability of the second gate field plate 21 stronger and further improve the voltage withstand capability of the transistor.

The gallium nitride heterojunction field effect transistor mentioned above is suitable for several scenarios. This article will introduce two of the application scenarios as examples.

scene one

The transistor provided by the embodiment of the present invention can be applied to any scenario that requires bidirectional turn-on and turn-off. Referring to FIG. 15 , the transistor provided by the embodiment of the present invention with two sides symmetrical along the grooves can be disposed on a line that requires bidirectional conduction and turn-off, and the transistor can be packaged as a patch type or pin type device. The device at least includes a gate pin G connected to the gate electrode 18 of the transistor, a first drain pin D1 connected to the first drain electrode 16 of the transistor, and a second drain pin D2 connected to the second drain electrode 17 of the transistor. The drive circuit needs to be connected to the gate pin G, and the device is connected to the circuit that requires bidirectional on and off control through the first drain pin D1 and the second drain pin D2. When the transistor needs to be turned on, a voltage needs to be applied to its gate 18 so that the gate voltage is higher than the voltage of the first drain 16 and the voltage difference between the gate 18 and the first drain 16 is greater than the first threshold. voltage; or, make the gate voltage higher than the voltage of the second drain electrode 17, and the voltage difference between the gate electrode 18 and the second drain electrode 17 is greater than the second threshold voltage. Since both sides of the transistor are symmetrical along the groove, the electrical properties of the first drain side and the second drain side of the transistor are also the same, and the first threshold voltage is equal to the second threshold voltage. The threshold voltage is related to the transistor parameters and can be known by measuring the transistor. After the gate voltage reaches the above range, carriers, that is, induced electrons, are generated in the channel layer 13 . The induced electrons are connected with the two-dimensional electron gas cut off by the grooves in the barrier layer 14 to form a conductive channel, thereby achieving conduction between the first drain electrode 16 and the second drain electrode 17 . When the gate voltage does not reach the above range, the induced electrons in the channel layer 13 decrease, and the induced electrons are not enough to connect the first part 1401 and the second part 1402 of the barrier layer 14, and the conductive channel is disconnected. Disconnection between the first drain 16 and the second drain 17 is achieved.

Scene 2

The transistor of the embodiment of the present invention can be applied to a mobile phone PCB that has both wired charging function and wireless charging function. Referring to Figure 16, in order to control the charging path on and off and avoid mutual flooding of wired charging and wireless charging currents, it is necessary to set the first transistor 2 provided by the embodiment of the present invention on the line where the wired charging interface USB_IN is located, and to set it on the line where the wireless charging interface RX_IN is located. The second transistor 3 provided by the embodiment of the present invention. The first transistor 2 and the second transistor 3 are respectively controlled to be turned on or off by two pins of the driving device 1 . For example, during wired charging, the first transistor 2 can be controlled to be turned on and the second transistor 3 to be turned off through the driving device 1 . During wireless charging, the driving device 1 can be used to control the second transistor 3 to be turned on and the first transistor 2 to be turned off, thereby preventing current backflow.

The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above-mentioned specific implementations. The above-mentioned specific implementations are only illustrative and not restrictive. Those of ordinary skill in the art will Inspired by this application, many forms can be made without departing from the purpose of this application and the scope protected by the claims, all of which fall within the protection of this application.

Claims (20)

1. A gallium nitride heterojunction field effect transistor, characterized in that it includes: A channel layer, the material of the channel layer is gallium nitride; A barrier layer, the barrier layer is provided on one side of the channel layer, the barrier layer includes a groove, and a first part and a second part respectively provided on both sides of the groove, the groove is at least It includes a first opening, the opening direction of the first opening is away from the direction of the channel layer, and a two-dimensional electron gas is formed on the interface between the channel layer and the first part and the second part respectively; A first drain electrode, the first drain electrode is disposed on the side of the first part away from the channel layer, and the material of the first drain electrode is a conductive material; a second drain electrode, the second drain electrode is disposed on the side of the second part away from the channel layer, and the material of the second drain electrode is a conductive material; A first dielectric layer, the first dielectric layer is provided at least on the inner surface of the groove, and the material of the first dielectric layer is an insulating material; A gate electrode is provided in the groove, and the material of the gate electrode is a conductive material. 2. The gallium nitride heterojunction field effect transistor according to claim 1, characterized in that the material of the barrier layer is Al _y Ga _1-y N, where Al is aluminum, Ga is gallium, and N is nitrogen, and the value range of y is 0<y≤1. 3. The gallium nitride heterojunction field effect transistor according to claim 1, wherein the material of the first dielectric layer includes silicon nitride, aluminum oxide, aluminum nitride, silicon dioxide or hafnium dioxide. . 4. The gallium nitride heterojunction field effect transistor according to claim 1, wherein the depth of the groove is the same as the thickness of the barrier layer. 5. The gallium nitride heterojunction field effect transistor according to claim 1, further comprising a first gate field plate, the first gate field plate being connected to the gate, and the third gate field plate being connected to the gate. Both sides of a gate field plate extend toward the direction of the first drain electrode and the direction of the second drain electrode respectively, and the third gate field plate is disposed between the first gate field plate and the barrier layer. A medium layer. 6. The gallium nitride heterojunction field effect transistor according to claim 5, further comprising a second dielectric layer and a second gate field plate, the second gate field plate being opposite to the first A gate field plate is provided, and the second dielectric layer is provided between the second gate field plate and the first drain electrode, the second drain electrode and the first gate field plate respectively, so The second gate field plate, the first gate field plate and the gate are all electrically connected. 7. The gallium nitride heterojunction field effect transistor according to claim 6, wherein the material of the second dielectric layer includes silicon nitride, aluminum oxide, aluminum nitride, silicon dioxide or hafnium dioxide. . 8. The gallium nitride heterojunction field effect transistor according to claim 1, further comprising a transition layer, the transition layer being disposed on a side of the channel layer away from the barrier layer. 9. The gallium nitride heterojunction field effect transistor according to claim 8, wherein the transition layer includes a transition layer body and a nucleation layer, and the transition layer body is disposed away from the channel layer. On one side of the barrier layer, the nucleation layer is disposed on a side of the transition layer body away from the channel layer. 10. The gallium nitride heterojunction field effect transistor according to claim 9, characterized in that the material of the transition layer body includes aluminum gallium nitride with graded aluminum composition, N-type gallium nitride, and homogeneous aluminum gallium. Nitrogen or superlattice aluminum gallium nitride; the material of the nucleation layer includes gallium nitride or aluminum nitride. 11. The gallium nitride heterojunction field effect transistor according to claim 8, further comprising a substrate, the substrate being disposed on a side of the transition layer away from the channel layer. 12. A method for manufacturing a gallium nitride heterojunction field effect transistor, characterized in that it is used to manufacture the gallium nitride heterojunction field effect transistor according to any one of claims 1 to 11, including: Preparing the channel layer; preparing the barrier layer on the channel layer; On the side of the barrier layer away from the channel layer, the groove is opened at a position corresponding to the gate; The first dielectric layer is formed on the inner surface of the groove and the side of the barrier layer away from the channel layer; Remove the first dielectric layer at positions corresponding to the first drain electrode and the second drain electrode; The first drain electrode and the second drain electrode are formed, and the gate electrode is formed. 13. The method for manufacturing a gallium nitride heterojunction field effect transistor according to claim 12, wherein after forming the gate electrode, it further includes forming a first gate field on the side with the gate electrode. plate. 14. The method of manufacturing a gallium nitride heterojunction field effect transistor according to claim 13, wherein forming the first gate field plate on the side with the gate electrode includes: A photoresist is formed on one side of the electrode and exposes the area where the first gate field plate is to be prepared. The first gate is formed using a sputtering or evaporation process in the area where the first gate field plate is to be prepared. Polar field plate. 15. The method for manufacturing a gallium nitride heterojunction field effect transistor according to claim 12, further comprising forming a second dielectric on a side of the first gate field plate away from the gate electrode. layer, and the second gate field plate is formed on a side of the second dielectric layer away from the first gate field plate. 16. The method for manufacturing a gallium nitride heterojunction field effect transistor according to claim 15, wherein the second dielectric layer is formed on a side of the second dielectric layer away from the first gate field plate. The gate field plate includes forming a photoresist on a side of the second dielectric layer away from the first gate field plate and exposing an area where the second gate field plate is to be prepared. The area of the second gate field plate is formed using a sputtering or evaporation process. 17. The method of manufacturing a gallium nitride heterojunction field effect transistor according to claim 12, wherein opening the groove includes forming a light beam on a side of the barrier layer away from the channel layer. The resist is used to expose the portion where the groove is to be formed, and the side of the barrier layer away from the channel layer is etched to form a groove. 18. The method for manufacturing a gallium nitride heterojunction field effect transistor according to claim 12, wherein the first dielectric at a position corresponding to the first drain electrode and the second drain electrode is removed. The layer includes forming a photoresist on a side of the first dielectric layer away from the channel layer and exposing the portion where the first drain electrode and the second drain electrode are to be formed. 19. The method for manufacturing a gallium nitride heterojunction field effect transistor according to claim 12, wherein before preparing the channel layer, the method further includes: Get the substrate; Form a nucleation layer on the surface of the substrate through vapor phase epitaxial growth technology; A transition layer body is grown on a side of the nucleation layer away from the substrate. 20. An electronic device, characterized by using the gallium nitride heterojunction field effect transistor according to any one of claims 1 to 11.