CN117079697A

CN117079697A - System for realizing memory bit-by-bit repair and memory read-write method

Info

Publication number: CN117079697A
Application number: CN202210507379.XA
Authority: CN
Inventors: 熊保玉; 沈岙
Original assignee: Hikstor Technology Co Ltd
Current assignee: Hikstor Technology Co Ltd
Priority date: 2022-05-10
Filing date: 2022-05-10
Publication date: 2023-11-17

Abstract

The application provides a system for realizing memory bit-by-bit repair and a memory read-write method, wherein the system comprises: a memory array with redundant columns, each row of array cells including a first number of data storage cells and a second number of repair cells; the write-destroy operation circuit is used for carrying out write-destroy operation on the failure units detected in each row of array units of the storage array; the reading circuit is used for reading the respective state identification of each row of array units of the storage array and the data stored in the state identification; the logic circuit is used for outputting a control signal and a selection signal according to the read state identification of each row of array units; a data selection circuit for selecting input or output data according to the control signal and the selection signal; and the write circuit is used for writing the data selected and input by the data selection circuit into a normal data storage unit or a normal repair unit.

Description

System for realizing memory bit-by-bit repair and memory read-write method

Technical Field

The application relates to the technical field of integrated circuit design, in particular to a system for realizing memory bit-by-bit repair and a memory read-write method.

Background

Under the condition that the existing MRAM manufacturing process is not mature enough, the array can be manufactured to form a plurality of problematic cells, some cells at the edge of the array are difficult to turn over, the characteristics of the MRAM are lost, and some cells are damaged in the normal reading and writing process, so that the array cannot be used. These problematic cells (hereinafter referred to as failed cells in the present application) seriously affect the yield of the array, and must be handled or replaced with cells that can be read and written normally in order to use the problematic array. Many repair methods are produced, and the common methods are: repair is performed using redundant cells of a row and column, or algorithmically using ECC (Error Correcting Code, error correction code).

In the current array structure, redundant repair is adopted, and only the whole row or the whole column can be replaced at a time, and because only a few units possibly need to be repaired, the whole row and one thousand or more units need to be replaced, so that the repair is wasteful. If the 1-bit ECC is used for repairing, the repairing capability is insufficient, and if the two-bit ECC is used for repairing, a large area is occupied, so that the cost is increased and other problems are caused.

Therefore, a circuit is needed to solve the problem of repairing individual failure units in an array, and the repair capability is required to meet the chip requirement without occupying too much area.

Disclosure of Invention

In order to solve the problems, the application provides a system for realizing the bit-by-bit repair of a memory and a memory read-write method, which can realize the function of repairing a failure unit in an array by bit.

In one aspect, the present application provides a system for implementing memory bitwise repair, comprising:

a memory array with redundant columns, each row of array cells including a first number of data storage cells and a second number of repair cells;

the write-destroy operation circuit is used for carrying out write-destroy operation on the failure units detected in each row of array units of the storage array;

the reading circuit is used for reading the respective state identification of each row of array units of the storage array and the data stored in the state identification;

the logic circuit is used for outputting a control signal and a selection signal according to the read state identification of each row of array units;

a data selection circuit for selecting input or output data according to the control signal and the selection signal;

and the write circuit is used for writing the data selected and input by the data selection circuit into a normal data storage unit or a normal repair unit.

Optionally, the write destruct operation circuit and the write circuit are implemented by a multiplexed write destruct operation/write circuit, the write destruct operation/write circuit specifically including:

a first NOT gate, the input end of which inputs a write enable signal;

a second NOT gate, the input end of which is connected to the output end of the first NOT gate;

a first NAND gate, two input ends of which input a write enable signal and a write destruction operation enable signal;

the second NAND gate, one input end is connected with the output end of the first NAND gate, another input end is connected with the output end of the second NAND gate;

the input end of the third NAND gate is connected with the output end of the second NAND gate;

the first NMOS tube is connected in series to the bit line, the grid electrode is connected to the output end of the third NOT gate, and the drain electrode is connected with the array unit on the bit line;

the second NMOS tube is connected in series to the source line, the grid electrode is connected to the output end of the second NOT gate, and the drain electrode is connected with the array unit on the source line;

the drain electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube, and the source electrode of the third NMOS tube is grounded;

the drain electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the fourth NMOS tube is grounded, the grid electrode of the fourth NMOS tube and the grid electrode of the third NMOS tube are connected at one point, and the fourth NMOS tube and the grid electrode of the third NMOS tube are connected to the output end of the first NOT gate together;

and the grid electrode of the first PMOS tube is connected with the output end of the first NAND gate, the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is connected with the array unit on the bit line.

Optionally, the read circuit includes:

the current mirror structure is used for outputting array current, array reference current and state identification reference current, wherein the array current flows into an array unit to be read;

a first reference resistor through which the array reference current flows;

a second reference resistor through which the state identification reference current flows;

the first voltage type sensitive amplifier is connected with a branch where the array current is and a branch where the array reference current is;

the second voltage type sensitive amplifier is connected with a branch where the array current is and a branch where the state identification reference current is;

and an inverter connected to the output end of the second voltage type sensitive amplifier.

Optionally, the resistance value of the first reference resistor is between the anti-parallel state resistance value and the parallel state resistance value of the magnetic tunnel junction in the array unit;

the resistance value of the second reference resistor is between the parallel state resistance value and the breakdown state resistance value of the magnetic tunnel junction in the array unit.

Optionally, the state identifier is used for distinguishing a normal unit from a failed unit that has been broken down, the state identifier is 0, which indicates that the unit is a normal unit, and the state identifier is 1, which indicates that the unit is a failed unit that has been broken down.

Optionally, if the state of the data storage unit is identified as 0, the control signal is at a low level, and if the state of the data storage unit is identified as 1, the control signal is at a high level;

the selection signal is used for selecting the positions of the repair units, the positions of the repair units are sequentially increased along with the increase of the number of the failed data storage units, and if the state identification of the repair units is 1, the selection signal skips the repair units at the current positions.

Optionally, the data selection circuit comprises an input unit and an output unit,

the input unit includes N single input-multiple output data selectors for selecting channels for data input according to the control signals and selection signals, selectively inputting the input data to the write circuit;

the output unit comprises N multi-input-single-output data selectors, which are used for selecting a data output channel according to the control signals and the selection signals and selectively outputting data from the data read by the read circuit;

where N is the number of data storage units on a row of the memory array.

In another aspect, the present application provides a method of writing data to a memory, the method comprising:

selecting a row of the memory array;

in a test mode, the write-down operation circuit carries out write-down operation on the failure unit detected in the array unit of the row;

reading the respective state identifiers of the array units of the row by a reading circuit;

the logic circuit outputs a control signal and a selection signal according to the state identification;

the data selection circuit selects a data input channel according to the control signal and the selection signal, and selectively inputs the input data to the write circuit;

the write circuit writes the data selected and input by the data selection circuit into a normal data storage unit or a normal repair unit.

In another aspect, the present application provides a method of reading data from a memory, the method comprising:

selecting a row of the memory array;

reading the respective state identifiers of the array units of the rows and the stored data by a reading circuit;

the data selecting circuit selects a channel for outputting data according to the control signal and the selection signal, and selectively outputs data from the data read by the reading circuit.

The system and the method for realizing the bit-by-bit repair of the memory can repair the failed data storage unit by bits, and greatly improve the repair efficiency. And the memory array only needs to have a plurality of redundant columns, the use area is small, and the effects of reducing the chip cost and improving the chip yield can be achieved.

Drawings

FIG. 1 is a block diagram of a system for implementing memory bit-wise repair in accordance with one embodiment of the present application;

FIG. 2 is a schematic diagram of a memory array with redundant columns according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a write destruct/write circuit according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a read circuit according to an embodiment of the application;

FIG. 5 is a schematic diagram illustrating a logic circuit according to an embodiment of the present application;

FIG. 6 is a schematic diagram of an input unit according to an embodiment of the application;

FIG. 7 is a schematic diagram of an output unit according to an embodiment of the application;

FIG. 8 is a schematic diagram of a bit-wise repair of a write operation according to an embodiment of the application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In the present application, the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate an azimuth or a positional relationship based on that shown in the drawings. These terms are only used to better describe the present application and its embodiments and are not intended to limit the scope of the indicated devices, elements or components to the particular orientations or to configure and operate in the particular orientations.

Also, some of the terms described above may be used to indicate other meanings in addition to orientation or positional relationships, for example, the term "upper" may also be used to indicate some sort of attachment or connection in some cases. The specific meaning of these terms in the present application will be understood by those of ordinary skill in the art according to the specific circumstances.

Furthermore, the terms "mounted," "configured," "provided," "connected," "coupled," and "sleeved" are to be construed broadly. For example, it may be a fixed connection, a removable connection, or a unitary construction; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements, or components. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.

Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.

An embodiment of the present application provides a system for implementing bit-wise repair of a memory, as shown in fig. 1, the system includes:

a memory array 101 with redundant columns, each row of array cells including a first number of data storage cells and a second number of repair cells;

a write destruct operation/write circuit 102, configured to perform a write destruct operation on a failure unit detected in each row of array units of the storage array;

a reading circuit 103, configured to read the respective status identifier of each row of array units of the memory array and the data stored in the status identifier;

a logic circuit 104, configured to output a control signal and a selection signal according to the read state identifier of each row of array units;

a data selection circuit 105 for selecting input or output data according to the control signal and the selection signal;

the write destruct operation/write circuit 102 is further configured to write the data selected and input by the data selection circuit into a normal data storage unit or a normal repair unit.

In the above system, a schematic diagram of a storage array structure with redundant columns is shown in fig. 2, and each row of array units is functionally divided into a data storage unit and a repair unit from the whole storage array perspective, and is functionally divided into a normal unit and a failure unit from the state identification perspective. Assuming that the total array unit bit number of a row is M, the row comprises a data storage unit for storing N bits and a repair unit for repairing K bits, wherein m=n+k, and the relationship between N and K can be adjusted according to the current process requirement. It should be noted that the positions of the repair units can be adjusted arbitrarily in the array according to the needs, and the repair units can be in discontinuous columns, and the number of the repair units can be adjusted at any time.

As an implementation manner, the write-destruction operation/writing circuit 102 in this embodiment realizes multiplexing of two functional circuits, namely, a write-destruction operation circuit and a writing circuit, and is designed as a whole circuit, but the actual design is not limited thereto. Fig. 3 shows one possible circuit configuration of the write destroy operation/write circuit 102. Referring to fig. 3, the write destroy operation/write circuit may include: 3 inverters, 2 NAND gates, 4 NMOS tubes and1 PMOS tube.

Specifically, the write destruct operation/write circuit includes:

a first NOT gate NOT1, the input end inputs a write enable signal write EN;

a second NOT2, the input end of which is connected to the output end of the first NOT;

a first NAND gate NAND1 having two input terminals to which a write enable signal write EN and a write disable operation enable signal break down_en are input;

the second NAND gate NAND2, one input end is connected with the output end of the first NAND gate, and the other input end is connected with the output end of the second NAND gate;

the input end of the third NOT3 is connected with the output end of the second NOT;

the first NMOS tube M1 is connected in series to the bit line, the grid electrode is connected to the output end of the third NOT gate, and the drain electrode is connected with the array unit on the bit line;

the second NMOS tube M2 is connected in series to the source line, the grid electrode is connected to the output end of the second NOT gate, and the drain electrode is connected with the array unit on the source line;

the drain electrode of the third NMOS tube M4 is connected with the drain electrode of the first NMOS tube, and the source electrode of the third NMOS tube M4 is grounded;

the drain electrode of the fourth NMOS tube M5 is connected with the drain electrode of the second NMOS tube, the source electrode of the fourth NMOS tube M5 is grounded, the grid electrode of the fourth NMOS tube M4 and the grid electrode of the third NMOS tube M4 are connected at one point and are commonly connected to the output end of the first NOT gate;

and the grid electrode of the first PMOS tube M3 is connected with the output end of the first NAND gate, the source electrode of the first PMOS tube M is connected with a power supply, and the drain electrode of the first PMOS tube M is connected with the array unit on the bit line.

The write destruct operation/write circuit controls the normal write operation of the array unit through the write enable signal write EN, and can realize the failed write destruct operation of the array unit through the combined action of the write destruct operation enable signal BreakDown_EN and the write enable signal write EN in the test mode.

The specific implementation method is as follows:

1. when the write EN and break down EN signals are both low, no operation is performed at this point and the array cell is not selected. M1 is closed, M2 is closed, and M3 is closed.

2. When the write EN signal is high and the break down EN signal is low, then the array cell normal write operation is performed, with M1 on, M2 on, and M3 off.

3. When the write EN signal is high and the break down EN signal is also high, then the array cell write down operation is performed, M1 is off, M2 is on, and M3 is on. The voltage loaded at the two ends of the array unit MTJ in the mode can break down the MTJ in a short time, so that the write-down function is realized.

It should be noted that, the circuit structure shown in fig. 3 is exemplified by any one bit line and a corresponding source line, and if there are M bit array cells in a row for the whole memory array, a total of M write destruct operation/write circuits are required. Different rows may multiplex the write destruct/write circuits described above.

As an embodiment, fig. 4 shows a possible circuit configuration of the read circuit. Referring to fig. 4, the read circuit may include:

the current mirror structure is used for outputting an array current Iarray, an array reference current Iref and a state identification reference current Iflag, wherein the array current Iarray flows into an array unit to be read;

a first reference resistor Rref1 through which an array reference current Iref flows;

a second reference resistor Rref2 through which a state identification reference current Iflag flows;

the first voltage type sense amplifier SA1 is connected into a branch circuit where the array current is and a branch circuit where the array reference current is;

the second voltage type sensitive amplifier SA2 is connected into a branch circuit where the array current is and a branch circuit where the state identification reference current is;

and an inverter INV connected to the output end of the second voltage type sense amplifier SA 2.

The reading circuit adopts two voltage-type sensitive amplifiers and a current mirror structure, and array current Iarray, array reference current Iref and state identification reference current Iflag are separated through the current mirror structure, and three currents are almost the same at the moment due to the action of the current mirror. The branch circuit where the Iarray is located and the branch circuit where the Iref is located are connected into a voltage type sensitive amplifier SA1, the branch circuit where the Iref is located is connected with a first reference resistor Rref1 with a resistance value between the resistance value of an anti-parallel state (RAP state) and the resistance value of a parallel state (RP state) of the array unit MTJ, and the branch circuit where the Iflag is located is connected with a second reference resistor Rref2 with a resistance value between the resistance value of a breakdown state of the array unit MTJ and the resistance value of the MTJ RP state. The resistance relationship is that the MTJ RAP state > the MTJ RP state > the MTJ breakdown state.

Because the resistances of the access points of the branches are different, the voltages of the access points are also different, the voltage of the two points can be compared through the voltage type sense amplifier, when the voltage VREAD of the access point of the branch where the Iarray is located is higher than the voltage VREF_ARRAY of the access point of the branch where the Iref is located, the resistance of an ARRAY unit (which can be a data storage unit or a repair unit) of the branch where the Iarray is located is larger than the first reference resistance, and the ARRAY unit is in the RAP state, so that the read data is 1. When the branch access point voltage VREAD of the iary is lower than the branch access point voltage vref_array of the Iref, it is indicated that the resistance of the ARRAY unit of the branch of the iary is lower than the first reference resistance, and the ARRAY unit is in RP state, so the readout data is 0.

Similarly, SA2 may output a comparison result between the array unit resistance and the second reference resistance, and if the array unit resistance is greater than the second reference resistance, it indicates that the array unit is a normal unit, the output is 1, and the state flag=0 is obtained through the inverter. If the resistance of the array unit is smaller than the second reference resistance, the array unit is in a breakdown state, the output is 0, and the state identification flag=1 is obtained through an inverter.

The read circuit adopts two voltage-type sense amplifiers, and has the advantages of being capable of simultaneously comparing the state identification and stored data of each row of data storage units and repair units of the storage array. When s1=1, s2=1 (i.e., flag=0), the array unit is in a RAP state, when s1=0, s2=1 (i.e., flag=0), the array unit is in an RP state, and when s1=0, s2=0 (i.e., flag=1), the array unit is in a breakdown state. There is no case where s1=1, sa2=0.

It should be noted that, the circuit structure shown in fig. 4 is a read circuit of one array unit, and for one row of the memory array, a total of M read circuits are required assuming the number of bits M of the array unit. Different rows may multiplex the read circuits described above. The read circuit may output M-bit data and an M-bit state identification (also referred to as a flag value) at a time.

Further, after transmitting the status flag (flag value) read by the read circuit to the logic circuit, the logic circuit outputs a control signal tm_REPAIR_EN and a selection signal tm_REPAIR_SEL <1:0> according to the flag values of the data storage unit and the REPAIR unit. The control signal is used to control whether the repair unit needs to be enabled or not, and the selection signal is used to allocate the repair unit positions, i.e. to select which repair unit to use for repair. In this embodiment, the control signal tm_repair_en is 1bit, and has a value of 0 or 1, and since the number of selectable REPAIR units is 4, the selection signal tm_repair_sel <1:0> is 2 bits, and has a value of 00,01,10,11, and different REPAIR units are selected respectively.

The specific logical correspondence of the logic circuit is as follows:

when the data storage unit flag value is equal to 1, it is indicated that the data storage unit is failed, the control signal tm_repair_en=1 is output, and which REPAIR unit is used for REPAIR is selected in order. As shown in FIG. 5 (a), there are 4 failures of the data storage unit, and the select signal TM_REPAIR_SEL <1:0> is incremented, and the 4 REPAIR units are used in turn for REPAIR. As shown in fig. 5 (b), there are 5 failures of the data storage units, the first 4 are repaired by using 4 repair units in turn, and the 5 th failure unit is out of repair range and is not operated.

When the flag value of the REPAIR unit is equal to 1, it indicates that the REPAIR unit is also failed, at this time, the selection signal tm_repair_sel <1:0> will automatically skip the failed REPAIR unit, and REPAIR is performed by using the next normal REPAIR unit, as shown in (c) in fig. 5, the 2 nd REPAIR unit fails, the selection signal tm_repair_sel <1:0> skips 01, and 00, 10,11 are sequentially output, and REPAIR is performed by using the 1 st REPAIR unit, the 3 rd REPAIR unit, and the 4 th REPAIR unit. And (5) beyond the repair range, and performing no operation.

The control signal tm_request_en and the selection signal tm_request_sel <1:0> outputted from the logic circuit are transferred to the data selection circuit, and the data inputted or outputted is selected by the data selection circuit.

The data selection circuit consists of two parts, including an input unit and an output unit,

the input unit is used for inputting data, comprises N single-input-multiple-output data selectors, selects a data input channel according to a control signal TM_REPAIR_EN and a selection signal TM_REPAIR_SEL, and selectively inputs the input data to the write circuit. FIG. 6 shows the circuit configuration of the input unit according to the embodiment of the present application, when TM_REPAIR_EN is low, it is indicated that the input bit is not disabled and is directly written. When tm_repair_en is high, which REPAIR cell to use for a write replacement of data is selected by the select signal tm_repair_sel. The remaining unselected inputs are invalid content.

The output unit is used for selecting the data finally output, and the data of the failure unit is also read out by the read operation, so that the corresponding REPAIR unit is required to realize replacement when outputting the data, and the control signal TM_REPAIR_EN and the selection signal TM_REPAIR_SEL are also used for selection. FIG. 7 shows a circuit configuration of the output unit according to the embodiment of the present application, when TM_REPAIR_EN is low, it indicates that the output bit is not disabled and is directly output. When tm_repair_en is high, which REPAIR cell to use for read replacement of data is selected by the select signal tm_repair_sel. The remaining unselected outputs are invalid content.

The system for realizing the bit-by-bit repair of the memory can repair the failed data storage unit by bit, and greatly improves the repair efficiency. And the memory array only needs to have a plurality of redundant columns, the use area is small, and the effects of reducing the chip cost and improving the chip yield can be achieved.

In another aspect, another embodiment of the present application provides a method for writing data into a memory, implemented by using the above system for implementing bit-wise repair of a memory, where the method includes:

selecting a row of the memory array;

the reading circuit reads the respective state identification of the array units of the row;

the logic circuit outputs a control signal and a selection signal according to the read state identification;

In another aspect, another embodiment of the present application provides a method for reading data from a memory, implemented by using the above system for implementing bit-wise repair of a memory, where the method includes:

selecting a row of the memory array;

the reading circuit reads the respective state identification of the array units of the row and the stored data;

The process of writing and reading is described in detail below with respect to a row of array cells.

Referring to fig. 8 (a), a memory array with redundant columns is set to have 12 array cells per row, 8 data storage cells for storing data, and 4 repair cells for repairing by bit, which may be defined as arbitrary bits, and this embodiment is merely exemplary. The data storage units DQ2, DQ5, DQ6 and the repair unit DQ8 were found to be failure units through testing. It is necessary to write destroy operations to these failed cells in sequence.

Firstly, entering a test mode, pulling high breakdown_EN to perform writing destruction operation, selecting DQ2 through external DQ <2> high level, and when breakdown_EN and corresponding DQ <2> are high, corresponding TM_BREAK_EN <2> is high level, and selecting DQ2 needing writing destruction. The remaining unselected DQ are low and the corresponding TM_BREAK_EN is low, using DATAMASK override, and no write operation is performed.

At this time, by using the write destroy operation/write circuit, the drive M1 of the selected failure unit is turned off, M2 is turned on, M3 is turned on, a path is formed, and the voltage applied to the MTJ is too high, resulting in the MTJ being destroyed by writing. The remaining unselected cells are not written. After the failure unit is destroyed by writing, the failure unit is broken down, and the resistance value of the failure unit is reduced from thousands of ohms to hundreds of ohms, which is far smaller than that of a normal MTJ. And sequentially performing write-destroy operation on the failure units. And ending the test mode, and performing normal read-write operation.

When writing, the operation of reading the state identifier of the array unit is performed first, the FLAG value read out by the data storage unit should be 00100110, the FLAG value read out by the repair unit should be 1000, and the high order is the failed unit that is destroyed by writing. The FLAG value is then provided to a logic circuit, which outputs a control signal tm_repair_en and a select signal tm_repair_sel according to the location and number of failed cells for determining the location of the REPAIR cells. TM_REPAIR_EN and TM_REPAIR_SEL are transmitted to the data selection circuit.

When the first bit data memory cell DQ0 receives write data, since the first bit data memory cell is a normal cell and flag=0, tm_repair_en is low, and write is performed normally, and the input MUX selects array in <0>, and data is written into DQ0 from array in < 0>. The rest of the cells are covered by DATAMASK and no write operation is performed.

Similarly, when the second bit data storage unit DQ1 receives write data, since the second bit data storage unit is a normal unit, flag=0, tm_repair_en is low, and write is performed normally, and the input MUX selects array in <1>, and data is written into DQ1 from array in <1 >. The rest of the cells are covered by DATAMASK and no write operation is performed.

When the third bit data storage unit DQ2 inputs the write data, since the third bit data storage unit has been written and flag=1, tm_repair_en is pulled high, REPAIR writing is performed on this bit data, and data is written into the REPAIR unit. However, since the first bit REPAIR cell DQ8 is also disabled and FLAG is 1, the REPAIR is performed using the first normal REPAIR cell DQ9 later, where tm_repair_en=1, tm_repair_sel <1:0> =01, the DQ9 cell is selected for REPAIR, MUX select REPAIR IN1 is input, and data is written into DQ9 (corresponding to DQ9 instead of DQ 2). The remaining cells are covered by DATAMASK and are not written.

The rest of the failed cells are subjected to write replacement operation in the same way. Fig. 8 (b) shows a schematic diagram of a write operation bit-wise repair.

When the reading operation is performed, different references are used for the reading operation at the same time, so that a group of 12-bit read array data and a group of 12-bit FLAG value can be obtained and respectively output from SA of the two different references.

When the first-bit read operation is performed, since the first-bit data memory cell is a normal cell and flag=0, tm_repeat_en is low, and the output MUX selects ARRAY out <0>, and outputs data read from DQ0.

Similarly, when the second bit read operation is performed, since the second bit data memory cell is a normal cell, flag=0, tm_repeat_en is low, and the output MUX selects ARRAY out <1>, which is output for the data read from DQ1.

When the third bit read operation is performed, since the third bit data memory cell is already written and flag=1, tm_repair_en is pulled high, the data of this bit is repaired, and the data is read out from the REPAIR cell. However, since the first bit REPAIR cell FLAG is also 1 and dq8 has been broken down, the data of the first normal REPAIR cell DQ9 is read backward, where tm_repair_en=1 and tm_repair_sel <1:0> =01, and the output MUX selects REPAIR OUT1 to output, and the data is read OUT by DQ 9.

And the rest failure units perform read replacement operation according to the same method.

The method for writing data into the memory and the method for reading data provided by the embodiment of the application are characterized in that firstly, a failure unit is identified and broken down by high voltage, and is changed into an irreversible breakdown state to distinguish 0 state and1 state of the unit, when the memory is subjected to reading or writing operation, the reading of a unit state identifier is firstly carried out, a control signal and a selection signal are output according to the state identifier, the output data or the input data are arranged in sequence, the failure unit with the high state identifier is eliminated, and after the replacement is carried out by a normal repairing unit, the normal reading and writing operation is carried out, so that the function of repairing according to bits is realized. The repair work can be carried out in each read-write process, when the MTJ unit fails due to durability problem in normal use, the repair unit can repair the failed data storage unit according to the bit, and the repair efficiency is greatly improved.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present application should be included in the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A system for implementing bit-wise repair of memory, the system comprising:

2. The system of claim 1, wherein the write destroy operation circuit and the write circuit are implemented by a multiplexed write destroy operation/write circuit, the write destroy operation/write circuit specifically comprising:

a first NOT gate, the input end of which inputs a write enable signal;

3. The system of claim 1, wherein the read circuit comprises:

a first reference resistor through which the array reference current flows;

4. The system of claim 3, wherein the first reference resistor has a resistance value between an anti-parallel state resistance value and a parallel state resistance value of the magnetic tunnel junction in the array unit;

5. The system of claim 1, wherein the status flag is used to distinguish between a normal cell and a failed cell that has been broken down, wherein the status flag is 0 indicating that the cell is a normal cell, and wherein the status flag is 1 indicating that the cell is a failed cell that has been broken down.

6. The system of claim 5, wherein the system further comprises a controller configured to control the controller,

if the state of the data storage unit is marked as 0, the control signal is in a low level, and if the state of the data storage unit is marked as 1, the control signal is in a high level;

7. The system of claim 1, wherein the data selection circuit comprises an input unit and an output unit,

where N is the number of data storage units on a row of the memory array.

8. A method of writing data to a memory, characterized in that it is implemented with a system for implementing bit-wise repair of a memory according to any of claims 1-7, said method comprising:

selecting a row of the memory array;

9. A method of memory reading data, characterized in that it is implemented with a system for implementing memory bitwise repair according to any of claims 1-7, said method comprising:

selecting a row of the memory array;

10. A method according to claim 8 or 9, wherein the status flag is used to distinguish between a normal cell and a failed cell that has been broken down, the status flag being 0 indicating that the cell is a normal cell, the status flag being 1 indicating that the cell is a failed cell that has been broken down.

11. The method of claim 10, wherein the step of determining the position of the first electrode is performed,