CN117075966B - Instruction processing method, device, equipment and readable storage medium - Google Patents
Instruction processing method, device, equipment and readable storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1657—Access to multiple memories
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
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- G06F13/1668—Details of memory controller
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The present disclosure relates to an instruction processing method, apparatus, device, and readable storage medium, the method comprising: when the database unloading engine is accessed, acquiring an instruction to be processed, wherein the instruction to be processed carries attribute information, and judging whether the instruction is hit or not according to the instruction type, the data source, the flag bit, whether the instruction is hit or not and whether the channel is a shared channel to be processed. Data can be read and written into the DDR through the array table instruction, and data consistency in the DDR and the cache can be further achieved, so that instruction processing can be carried out on the latest data, and the latest data can be obtained.
Description
Technical Field
The present disclosure relates to the field of data processing technologies, and in particular, to an instruction processing method, an apparatus, a device, and a readable storage medium.
Background
A database offload engine (Database Offload Engine, DOE) aimed at offloading database software processing onto hardware to achieve the capability of high-speed, even real-time processing. Typically, the array table and the hash table are stored separately.
During data storage, there are two types of ports to access the DOE, one is a single channel host (host) port and one is a 16 channel packet processing engine (packet processing engine, PPE) port. Wherein the host port accesses data in double rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR), the PPE port accesses data in cache and accesses data in DDR through cache.
Because the two ports are parallel, the situation that DDR and cache data are not synchronous can occur. When the PPE port accesses the DOE in parallel with the host port, the following occurs: 1) The PPE end is read only, and the host end is inserted, deleted, updated and inquired; when the host end is updated, the data in the DDR is up to date, the data is to be synchronized to the cache, and the DDR is required to perform consistency processing to the cache; 2) Reading and writing by the PPE terminal, inserting, deleting and inquiring by the host terminal; when the host queries, the data in the cache is up to date, the data needs to be synchronized to the DDR, and the cache needs to perform consistency processing to the DDR. Because DDR and cache data are not synchronous, when an instruction is executed, instruction processing cannot be performed on the latest data, and the latest data is difficult to acquire.
Disclosure of Invention
In order to solve the above technical problems, the present disclosure provides an instruction processing method, apparatus, device, and readable storage medium, so as to perform instruction processing on latest data, and obtain the latest data.
In a first aspect, an embodiment of the present disclosure provides an instruction processing method, including:
when accessing a database unloading engine, acquiring an instruction to be processed, wherein the instruction to be processed carries attribute information, and the attribute information comprises at least one of an instruction type, a data source, a flag bit, whether the instruction hits or not and whether a channel is a shared channel of the instruction to be processed;
When the instruction to be processed is an array table instruction, judging the instruction to be processed according to the instruction type, the data source, the flag bit, whether the instruction hits or not and whether the channel is a shared channel of the instruction to be processed, processing the instruction to be processed based on a judging result, and outputting a processing result.
In a second aspect, an embodiment of the present disclosure provides an instruction processing apparatus, including:
the acquisition module is used for acquiring an instruction to be processed when accessing the database unloading engine, wherein the instruction to be processed carries attribute information, and the attribute information comprises at least one of an instruction type, a data source, a flag bit, whether the instruction hits or not and whether a channel is a shared channel of the instruction to be processed;
The first processing module is used for judging the instruction to be processed according to the instruction type, the data source, the flag bit, whether the instruction hits or not and whether the channel is a shared channel of the instruction to be processed when the instruction to be processed is an array table instruction, processing the instruction to be processed based on a judging result, and outputting a processing result.
In a third aspect, an embodiment of the present disclosure provides an electronic device, including:
A memory;
A processor; and
A computer program;
wherein the computer program is stored in the memory and configured to be executed by the processor to implement the method according to the first aspect.
In a fourth aspect, embodiments of the present disclosure provide a computer-readable storage medium having stored thereon a computer program for execution by a processor to implement the method of the first aspect.
In a fifth aspect, the disclosed embodiments also provide a computer program product comprising a computer program or instructions which, when executed by a processor, implement an instruction processing method as described above.
According to the instruction processing method, the device, the equipment and the readable storage medium, when the database unloading engine is accessed, the instruction to be processed is obtained, the instruction to be processed carries attribute information, the attribute information comprises at least one of an instruction type, a data source, a flag bit, whether the instruction hits or not and whether the channel is a shared channel of the instruction to be processed, when the instruction to be processed is an array table instruction, the instruction to be processed is judged according to the instruction type, the data source, the flag bit, whether the instruction hits or not and whether the channel is the shared channel of the instruction to be processed, the instruction to be processed is processed based on a judging result, and a processing result is output. Data can be read and written into the DDR through the array table instruction, and data consistency in the DDR and the cache can be further achieved, so that instruction processing can be carried out on the latest data, and the latest data can be obtained.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments of the present disclosure or the solutions in the prior art, the drawings that are required for the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a flow chart of an instruction processing method provided in an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of processing logic of an array table instruction according to an embodiment of the disclosure;
FIG. 3 is a flowchart of a method for processing a query instruction according to an embodiment of the present disclosure;
FIG. 4 is a flowchart of a method for processing an insert instruction according to an embodiment of the present disclosure;
FIG. 5 is a flowchart of a method for processing a delete instruction according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of processing logic of a hash table instruction according to an embodiment of the disclosure;
fig. 7 is a schematic structural diagram of an instruction processing apparatus according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, a further description of aspects of the present disclosure will be provided below. It should be noted that, without conflict, the embodiments of the present disclosure and features in the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein; it will be apparent that the embodiments in the specification are only some, but not all, embodiments of the disclosure.
Embodiments of the present disclosure provide an instruction processing method, which is described below in connection with specific embodiments.
Fig. 1 is a flowchart of an instruction processing method according to an embodiment of the present disclosure. The execution subject of the method is an electronic device. The electronic equipment can be portable mobile equipment such as smart phones, tablet computers, notebook computers, vehicle navigation equipment, intelligent sports equipment and the like; the system can also be a fixed device such as a personal computer, an intelligent household appliance, a server and the like, wherein the server can be a single server, can be a server cluster, and can be a distributed cluster or a centralized cluster. The method can be applied to a scene of instruction processing, can process the latest data, and can acquire the latest data.
It can be appreciated that the instruction processing method provided by the embodiment of the present disclosure may also be applied in other scenarios.
In order to ensure that the PPE end and the host end access the latest data, the strategy adopted by the embodiment of the disclosure is to set a cache state bit on the data, wherein when the data of the host end is inserted into the DDR, the state bit is 0, when the cache reads the data in the DDR, the cache state bit in the DDR is rewritten to 1, which indicates that the data is already on the cache, and when the cache replaces the old data to the DDR, the state bit of the cache is rewritten to 0, which indicates that the data is not already on the cache. The consistency module is configured, and all the consistency module needs to do is to update the DDR or read the data on the cache according to the status bit of the cache.
According to the requirements, the caches are divided into two types of caches, one type of cache is called exclusive cache, and the other type of cache is called shared cache. The exclusive cache is 16 first-level caches (L1 caches), and the PPE of each channel can only access the data on the corresponding channel cache; the shared cache is 16L 1 caches and 1 second-level cache (L2 cache), and the PPEs of each channel can access the data on the 16L 1 caches. The structure of the single shared cache is the same as that of the L1cache of the shared cache; the L2 cache of the shared cache increases the status bit of the L1cache, and the capacity of the L2 cache is larger than that of all the L1 caches.
The consistency module is divided into a plurality of group consistency acons and hash consistency hcons.
The main functions of acons include: 1) The data reading and writing in the DDR are realized through an array table engine (Array Instruction Engine, AIE), and the consistency module respectively sends array table instructions, such as an insert instruction (store), a query instruction (load) and a delete instruction (read_clear), of the instruction interface unit (Instruction Interface Unit, IIU) to the AIE module; 2) The IIU is transmitted to the array table instruction of the consistency module for storage, and the instructions are numbered, so that the related information of the instructions can be obtained during subsequent processing; 3) Synchronizing DDR and cache data, analyzing results returned by the AIE and the cache, and sending instructions to the AIE and the cache; 4) And returning the obtained final result to the IIU according to different types of instructions.
As for the array table, there are tables of PPE read only, DDR read write, PPE read write and DDR read only. So the data in the array table exists on both the shared cache and the exclusive cache. There are 3 types of instructions passed from IIU to AIE: store, load, read _clear. Wherein the load and read_clear are processed in the coherency module in unison, the data type of inst is cmd, and the data type of res is cmd pointing to data. Whereas the inst of store is of the opposite data type to res.
Hcons are related to shared cache only, except that acons may be related to either exclusive or shared cache. Judging whether the result is directly transmitted to the L1cache or the L2cache according to the result returned to the acons by the AIE, and if the result is transmitted to the L1cache, directly transmitting the result back to the IIU; if the data is transmitted to the L2, judging whether the data is returned to the IIU or directly returned to the IIU after the data is transmitted to the L1 according to the returned result of the L2.
The execution results returned by the L2 cache can be divided into two categories: 1) The result is get and the data is only on L2, or the result is miss (no on L2, no on L1), which is considered to be unnecessary, and the result is output. 2) The result is get, and the data is also on L1, requiring updates to the data on L1. Since there may be multiple L1 caches for data on L2, a total of several instructions are issued.
The returned result is the processing at the MISS: when the exclusive cache returns to the miss, a request is sent to the AIE again; when the shared cache returns to the miss (L1 or L2), the data returned by the AIE before is directly sent to the IIU.
By the above-described flow and the module functions to be implemented, the doe _acons module may be divided into a plurality of sub-modules. The multiple sub-modules in doe _acons module and their corresponding functions are shown in table 1 below:
table 1 multiple sub-modules in doe_acons module and corresponding functions
The doe _ hcons module may be divided into a plurality of sub-modules. The various sub-modules in doe _ hcons module and their corresponding functions are shown in table 2 below:
Table 2 multiple sub-modules in doe_hcons module and corresponding functions
The instruction processing method shown in fig. 1 is described below, and the method includes the following specific steps:
S101, when a database unloading engine is accessed, acquiring an instruction to be processed, wherein the instruction to be processed carries attribute information, and the attribute information comprises at least one of an instruction type, a data source, a flag bit, whether the instruction hits or not and whether a channel is a shared channel of the instruction to be processed.
In this step, when the database uninstallation engine is accessed, the electronic device obtains a to-be-processed instruction, where some attribute information is carried in the to-be-processed instruction.
In some embodiments, the attribute information includes at least one of: the instruction type, the data source, the flag bit, whether the instruction hits or not and whether the channel is a shared channel or not of the instruction to be processed.
Optionally, the attribute information may be any one of an instruction type, a data source, a flag bit, whether the instruction hits, and whether the channel is a shared channel of the instruction to be processed, or any combination of several types of the instruction and the shared channel, and the attribute information may also be other information, which is not specifically limited.
In some embodiments, the instruction type of the instruction to be processed includes any one of an insert instruction, a query instruction, and a delete instruction.
S102, when the instruction to be processed is an array table instruction, judging the instruction to be processed according to the instruction type, the data source, the flag bit, whether the instruction hits or not and whether the channel is a shared channel of the instruction to be processed, processing the instruction to be processed based on a judging result, and outputting a processing result.
When the instruction to be processed is an array table instruction, the electronic equipment can process the instruction to be processed according to the attribute information. Specifically, the instruction to be processed is judged according to the instruction type, the data source, the flag bit, whether the instruction hits or not and whether the channel is a shared channel of the instruction to be processed, the instruction to be processed is processed based on the judging result, and the processing result is output. The judgment results are different, the processing modes of the instructions are different, and the output results are different.
Compared with the prior art, when the database unloading engine is accessed, the method and the device acquire the to-be-processed instruction, wherein the to-be-processed instruction carries attribute information, the attribute information comprises at least one of an instruction type, a data source, a flag bit, whether the instruction hits or not and whether the channel is a shared channel of the to-be-processed instruction, when the to-be-processed instruction is an array table instruction, the to-be-processed instruction is judged according to the instruction type, the data source, the flag bit, whether the instruction hits or not and whether the channel is the shared channel of the to-be-processed instruction, the to-be-processed instruction is processed based on a judging result, and a processing result is output. Data can be read and written into the DDR through the array table instruction, and data consistency in the DDR and the cache can be further achieved, so that instruction processing can be carried out on the latest data, and the latest data can be obtained.
Fig. 3 is a flowchart of a method for processing a query instruction according to an embodiment of the present disclosure, where, as shown in fig. 3, when an instruction type of the instruction to be processed is a query instruction, the method includes the following steps:
S301, if the data source is an array table instruction engine and the channel is a shared channel, outputting a processing result to an instruction interface unit for responding to the query instruction and the instruction interface unit for responding to the query data.
As shown in fig. 2, when the instruction type of the instruction to be processed is a query instruction, the determination path of the array_load is corresponding. When the DATA source is the array table instruction engine sourse _id= aie and the channel is the shared channel, the output processing results are iiu_res_load and iiu_res_data.
S302, if the data source is an array table instruction engine, the channel is a shared channel, and the flag bit is zero, the output processing result is that the instruction interface unit responds to the query instruction and the instruction interface unit responds to the query data.
As shown in fig. 2, when the DATA source is the array table instruction engine sourse _id= = aie, the channel is the exclusive channel or the exclusive_table, and the flag bit is zero or the cache_pos= =0, the output processing results are iiu_res_load and iiu_res_data.
S303, if the data source is an array table instruction engine, the channel is a shared channel, and the flag bit is the flag bit corresponding to the first-level cache, outputting the processing result to the first-level cache operation command line to execute the query instruction.
As shown in fig. 2, when the data source is the array table instruction engine sourse _id= = aie, the channel is the exclusive channel, and the flag bit is the flag bit corresponding to the first-level cache, namely, cache_pos= =l1, the output processing result is l1_cmd_load.
S304, if the data source is a first-level cache memory and the instruction hits, the output processing result is that the instruction interface unit responds to the query instruction and the instruction interface unit responds to the query data.
As shown in fig. 2, when the DATA source is a level one cache, sourse _id= =l1, and the instruction hits, l1_hit, the output processing results are iiu_res_load and iiu_res_data.
S305, if the data source is a first-level cache memory and the instruction is not hit, outputting the processing result to an array table instruction engine to run a command line to execute the query instruction.
As shown in fig. 2, when the data source is a first level cache, sourse _id= =l1, and the instruction misses, l1_miss, the output processing result is aie_cmd_load.
Compared with the prior art, when the instruction type of the to-be-processed instruction is a query instruction, the embodiment of the disclosure includes the following steps: if the data source is an array table instruction engine and the channel is a shared channel, outputting a processing result which is that the instruction interface unit responds to the query instruction and the instruction interface unit responds to the query data; if the data source is an array table instruction engine, the channel is a shared channel and the flag bit is zero, outputting a processing result which is that the instruction interface unit responds to the query instruction and the instruction interface unit responds to the query data; if the data source is an array table instruction engine, the channel is a shared channel, and the flag bit is the flag bit corresponding to the first-level cache, outputting a processing result to be an operation command line of the first-level cache to execute the query instruction; if the data source is a first-level cache memory and the instruction hits, outputting a processing result that the instruction interface unit responds to the query instruction and the instruction interface unit responds to the query data; if the data source is a first-level cache memory and the instruction is not hit, the output processing result is an array table instruction engine running command line executing query instruction. When the instruction type of the instruction to be processed is a query instruction, outputting a processing result according to different judging results, determining the latest data based on judging logic, and further performing query instruction processing on the latest data to acquire the latest data.
Fig. 4 is a flowchart of a processing method of an insert instruction according to an embodiment of the present disclosure, where when an instruction type of the instruction to be processed is an insert instruction, the method includes the following specific steps:
S401, if the data source is an array table instruction engine and the flag bit is zero, outputting a processing result to an instruction interface unit for responding to the insertion instruction.
As shown in fig. 2, when the instruction type of the instruction to be processed is an insert instruction, the judgment path of the corresponding array_store is determined. When the data source is the array table instruction engine sourse _id= = aie and the flag bit is zero, namely cache_pos= =0, the output processing result is iiu_res_store.
S402, if the data source is an array table instruction engine and the flag bit is the flag bit corresponding to the first-level cache, outputting the processing result to be the first-level cache operation command line execution insertion instruction and the first-level cache operation command line insertion data.
As shown in fig. 2, when the DATA source is the array table instruction engine sourse _id= = aie and the flag bit is the flag bit corresponding to the first-level cache, i.e. cache_pos= =l1, the output processing results are l1_cmd_store and l1_cmd_data.
S403, if the data source is an array table instruction engine and the flag bit is the flag bit corresponding to the second-level cache, outputting the processing result to be the second-level cache operation command line execution insertion instruction and the second-level cache operation command line insertion data.
As shown in fig. 2, when the DATA source is the array table instruction engine sourse _id= = aie and the flag bit is the flag bit corresponding to the second-level cache, namely, cache_pos= =l2, the output processing results are l2_cmd_store and l2_cmd_data.
S404, if the data source is the second-level cache memory and the instruction is not hit, the output processing result is that the instruction interface unit responds to the insert instruction.
As shown in fig. 2, when the data source is a second-level cache memory, sourse _id= =l2, and the instruction misses, l2_miss, the output processing result is iiu_res_store.
S405, if the data source is the second-level cache, the instruction hits, and the number of channels hitting the first-level cache is zero, the output processing result is the response of the instruction interface unit to the insert instruction.
As shown in fig. 2, when the data source is a second-level cache, i.e., sourse _id= L2, the instruction hits, i.e., l1_hit, and the number of channels hitting the first-level cache is zero, i.e., l1_pos= 0, the output processing result is iiu_res_store.
S406, if the data source is the second-level cache, the instruction hits, and the number of channels hitting the first-level cache is greater than zero, outputting the processing result as the first-level cache operation command line execution insertion instruction and the first-level cache operation command line insertion data.
As shown in fig. 2, when the DATA source is a second-level cache, i.e., sourse _id= L2, the instruction hits, i.e., l1_hit, and the number of channels hitting the first-level cache is greater than zero, i.e., l1_pos > 0, the output processing results are l1_cmd_store and l1_cmd_data.
S407, if the data source is a first-level cache memory, the channel is a shared channel, and the instruction hits, the output processing result is the response of the instruction interface unit to the insert instruction.
As shown in fig. 2, when the data source is a first-level cache, i.e., sourse _id= L1, the channel is an exclusive channel, i.e., an exclusive_table, and the instruction hits, i.e., l1_hit, the output processing result is iiu_res_store.
S408, if the data source is the first-level cache memory, the channel is the exclusive channel, and the instruction is not hit, the output processing result is the array table instruction engine operation command line execution insert instruction and the array table instruction engine operation command line insert data.
As shown in fig. 2, when the DATA source is a primary cache memory, i.e., sourse _id= L1, the channel is an exclusive channel, i.e., an exclusive_table, and the instruction misses, i.e., l1_miss, the output processing results are aie_cmd_store and aie_cmd_data.
S409, if the data source is the first-level cache, the channel is the shared channel, and the sum of the channel number hitting the first-level cache is equal to one, the output processing result is the response of the instruction interface unit to the insert instruction.
As shown in fig. 2, when the data source is a level one cache, i.e., sourse _id= L1, the channel is a shared channel, i.e., share_table, and the sum of the number of channels hitting the level one cache is equal to one, i.e., sum (l1_pos) = 1, the output processing result is iiu_res_store.
S410, if the data source is the first-level cache, the channels are shared channels, and the sum of the channel number hitting the first-level cache is greater than one, the processing is not performed.
As shown in fig. 2, when the data source is a level one cache, i.e., sourse _id= L1, the channel is a shared channel, i.e., share_table, and the sum of the number of channels hitting the level one cache is equal to one, i.e., sum (l1_pos) > 1, no processing is performed.
Compared with the prior art, the embodiment of the disclosure comprises the following steps when the instruction type of the to-be-processed instruction is an insert instruction: if the data source is an array table instruction engine and the flag bit is zero, outputting a processing result to an instruction interface unit for responding to the insertion instruction; if the data source is an array table instruction engine and the flag bit is the flag bit corresponding to the first-level cache memory, outputting a processing result to be a first-level cache memory operation command line execution insertion instruction and first-level cache memory operation command line insertion data; if the data source is an array table instruction engine and the flag bit is the flag bit corresponding to the second-level cache memory, outputting a processing result to be a second-level cache memory operation command line execution insertion instruction and second-level cache memory operation command line insertion data; if the data source is a second-level cache memory and the instruction is not hit, outputting a processing result that the instruction interface unit responds to the inserted instruction; if the data source is a second-level cache memory, the instruction hits, and the number of channels hitting the first-level cache memory is zero, outputting a processing result as a response of the instruction interface unit to the inserted instruction; if the data source is a second-level cache memory, the instruction hits, and the number of channels hitting the first-level cache memory is greater than zero, outputting a processing result to be a first-level cache memory operation command line execution insertion instruction and first-level cache memory operation command line insertion data; if the data source is a first-level cache memory, the channel is a shared channel and the instruction hits, the output processing result is that the instruction interface unit responds to the inserted instruction; if the data source is a first-level cache memory, the channel is a shared channel and the instruction is not hit, outputting a processing result which is an array table instruction engine operation command line execution insertion instruction and array table instruction engine operation command line insertion data; if the data source is a first-level cache memory, the channels are shared channels, and the sum of the channel numbers hitting the first-level cache memory is equal to one, outputting a processing result to an instruction interface unit to respond to the insertion instruction; if the data source is a primary cache memory, the channels are shared channels, and the sum of the number of channels hitting the primary cache memory is greater than one, no processing is performed. When the instruction type of the instruction to be processed is an inserting instruction, outputting a processing result according to different judging results, determining the latest data based on judging logic, and further carrying out inserting instruction processing on the latest data to obtain the latest data.
Fig. 5 is a flowchart of a method for processing a delete instruction according to an embodiment of the present disclosure, where, as shown in fig. 5, when an instruction type of the instruction to be processed is a delete instruction, the method includes the following steps:
s501, if the data source is an array table instruction engine and the flag bit is zero, outputting a processing result that the instruction interface unit responds to the deletion instruction and the instruction interface unit responds to the deletion data.
As shown in fig. 2, when the instruction type of the instruction to be processed is a delete instruction, the determination path of the corresponding array_clear is determined. When the DATA source is the array table instruction engine sourse _id= aie and the flag bit is zero, namely the cache_pos= 0, the output processing results are iiu_res_clear and iiu_res_data.
S502, if the data source is an array table instruction engine and the flag bit is the flag bit corresponding to the first-level cache, outputting a processing result to be the first-level cache operation command line to execute the deleting instruction.
As shown in fig. 2, when the data source is the array table instruction engine sourse _id= = aie and the flag bit is the flag bit corresponding to the first-level cache, i.e. cache_pos= =l1, the output processing result is l1_cmd_clear.
S503, if the data source is the first-level cache memory and the instruction hits, the output processing result is that the instruction interface unit responds to the delete instruction and the instruction interface unit responds to the delete data.
As shown in fig. 2, when the DATA source is a level one cache, or sourse _id= L1, and the instruction hits, or l1_hit, the output processing results are iiu_res_clear and iiu_res_data.
S504, if the data source is the first-level cache memory and the instruction is not hit, the output processing result is that the array table instruction engine runs the command line to execute the delete instruction.
As shown in fig. 2, when the data source is a first level cache, sourse _id= =l1, and the instruction misses, l1_miss, the output processing result is aie_cmd_clear.
Compared with the prior art, the embodiment of the disclosure comprises the following steps when the instruction type of the to-be-processed instruction is a delete instruction: if the data source is an array table instruction engine and the flag bit is zero, outputting a processing result that the instruction interface unit responds to the deleting instruction and the instruction interface unit responds to the deleting data; if the data source is an array table instruction engine and the flag bit is the flag bit corresponding to the first-level cache, outputting a processing result to be a first-level cache operation command line execution deleting instruction; if the data source is a first-level cache memory and the instruction hits, outputting a processing result that the instruction interface unit responds to the deleting instruction and the instruction interface unit responds to the deleting data; if the data source is a first-level cache memory and the instruction is not hit, the output processing result is that the array table instruction engine operates the command line to execute the deleting instruction. When the instruction type of the instruction to be processed is a deleting instruction, outputting a processing result according to different judging results, determining the latest data based on judging logic, and further deleting the instruction to the latest data, so that the latest data can be obtained.
In some embodiments, the method further comprises: when the instruction to be processed is a hash table instruction, judging the instruction to be processed according to the sum of the data source, the flag bit, whether the instruction hits or not and the channel number hitting the first-level cache memory of the instruction to be processed; and processing the instruction to be processed based on the judging result, and outputting a processing result.
Optionally, the processing the to-be-processed instruction based on the determination result, and outputting a processing result, including the following steps:
s601, if the data source is a hash table instruction engine and the instruction is not hit, outputting a processing result to be an instruction interface unit response;
As shown in fig. 6, when the instruction to be processed is a HASH table instruction, i.e., hash_delete, and the data source is a HASH table instruction engine, i.e., sourse _id= hie, and the instruction misses, i.e., hie _miss, the output processing result is iiu_res.
S602, if the data source is an array table instruction engine, an instruction hit and a flag bit is zero, outputting a processing result as an instruction interface unit response;
As shown in fig. 6, when the data source is a hash table instruction engine sourse _id= = hie, an instruction hit is hie _hit, and the flag bit is zero, namely cache_pos= =0, the output processing result is iiu_res.
S603, if the data source is an array table instruction engine, an instruction hit and the flag bit is not zero, outputting a processing result as a second-level cache memory operation command line;
As shown in fig. 6, when the data source is a hash table instruction engine sourse _id= hie, the instruction hit is hie _hit, and the flag bit is not zero, i.e. cache_pos is not equal to 0, the output processing result is l2_cmd.
S604, if the data source is a second-level cache memory and the sum of the channel numbers hitting the first-level cache memory is equal to one, outputting a processing result as an instruction interface unit response;
As shown in fig. 6, when the data source is a second-level cache memory, i.e., sourse _id= L2, and the sum of the channel numbers hitting the first-level cache memory is equal to one, i.e., sum (l1_pos) = 1, the output processing result is iiu_res.
S605, if the data source is a second-level cache memory and the sum of the channel numbers hitting the first-level cache memory is not equal to one, not processing;
As shown in fig. 6, when the data source is a second-level cache memory, that is, sourse _id= L2, and the sum of the channel numbers hitting the first-level cache memory is not equal to one, that is, sum (l1_pos) +.1, no processing is performed.
S606, if the data source is a first-level cache memory and the instruction is not hit, outputting a processing result as an instruction interface unit response;
as shown in fig. 6, when the data source is a level one cache, sourse _id= L1, and the instruction misses, l1_miss, the output processing result is iiu_res.
S607, if the data source is the first-level cache, the instruction hits, and the flag bit is the flag bit corresponding to the second-level cache, the output processing result is the response of the instruction interface unit;
as shown in fig. 6, when the data source is a first-level cache, i.e., sourse _id= L1, the instruction hits, i.e., l1_hit, and the flag bit is the flag bit corresponding to the second-level cache, i.e., cache_pos is only on L2, the output processing result is iiu_res.
S608, if the data source is the first-level cache, the instruction hits, and the flag bits are the flag bit corresponding to the first-level cache and the flag bit corresponding to the second-level cache, the output processing result is the first-level cache operation command line.
As shown in fig. 6, when the data source is a first-level cache, i.e., sourse _id= L1, the instruction hits, i.e., l1_hit, and the flag bit is a flag bit corresponding to the first-level cache and a flag bit corresponding to the second-level cache, i.e., cache_pos, are both on L1 and L2, the output processing result is l1_cmd.
According to the embodiment of the disclosure, when an instruction to be processed is a hash table instruction, the instruction to be processed is judged according to the sum of the data source, the flag bit, whether the instruction hits or not and the channel number hitting a first-level cache memory of the instruction to be processed; and processing the instruction to be processed based on the judging result, and outputting a processing result. Through the hash table instruction, data consistency in DDR and cache can be realized, so that instruction processing can be performed on the latest data, and the latest data can be obtained.
Fig. 7 is a schematic structural diagram of an instruction processing apparatus according to an embodiment of the present disclosure. The instruction processing apparatus may be an electronic device as described in the above embodiments, or the instruction processing apparatus may be a part or component in the electronic device. The instruction processing apparatus provided in the embodiment of the present disclosure may execute the processing flow provided in the embodiment of the instruction processing method, as shown in fig. 7, the instruction processing apparatus 70 includes: an acquisition module 71, a first processing module 72; the obtaining module 71 is configured to obtain, when accessing the database offload engine, an instruction to be processed, where the instruction to be processed carries attribute information, and the attribute information includes at least one of an instruction type, a data source, a flag bit, whether the instruction hits, and whether a channel is a shared channel of the instruction to be processed; the first processing module 72 is configured to determine, when the instruction to be processed is an array table instruction, whether the instruction to be processed is a shared channel according to an instruction type, a data source, a flag bit, whether the instruction hits, and whether the channel is a shared channel of the instruction to be processed, process the instruction to be processed based on a determination result, and output a processing result.
Optionally, the instruction type of the instruction to be processed includes any one of an insert instruction, a query instruction and a delete instruction.
Optionally, the first processing module 72 processes the to-be-processed instruction based on the determination result, and when outputting the processing result, the processing module is specifically configured to: when the instruction type of the to-be-processed instruction is a query instruction, the method comprises the following steps: if the data source is an array table instruction engine and the channel is a shared channel, outputting a processing result which is that the instruction interface unit responds to the query instruction and the instruction interface unit responds to the query data; if the data source is an array table instruction engine, the channel is a shared channel and the flag bit is zero, outputting a processing result which is that the instruction interface unit responds to the query instruction and the instruction interface unit responds to the query data; if the data source is an array table instruction engine, the channel is a shared channel, and the flag bit is the flag bit corresponding to the first-level cache, outputting a processing result to be an operation command line of the first-level cache to execute the query instruction; if the data source is a first-level cache memory and the instruction hits, outputting a processing result that the instruction interface unit responds to the query instruction and the instruction interface unit responds to the query data; if the data source is a first-level cache memory and the instruction is not hit, the output processing result is an array table instruction engine running command line executing query instruction.
Optionally, the first processing module 72 processes the to-be-processed instruction based on the determination result, and when outputting the processing result, the processing module is specifically configured to: when the instruction type of the instruction to be processed is an insert instruction, the method comprises the following steps: if the data source is an array table instruction engine and the flag bit is zero, outputting a processing result to an instruction interface unit for responding to the insertion instruction; if the data source is an array table instruction engine and the flag bit is the flag bit corresponding to the first-level cache memory, outputting a processing result to be a first-level cache memory operation command line execution insertion instruction and first-level cache memory operation command line insertion data; if the data source is an array table instruction engine and the flag bit is the flag bit corresponding to the second-level cache memory, outputting a processing result to be a second-level cache memory operation command line execution insertion instruction and second-level cache memory operation command line insertion data; if the data source is a second-level cache memory and the instruction is not hit, outputting a processing result that the instruction interface unit responds to the inserted instruction; if the data source is a second-level cache memory, the instruction hits, and the number of channels hitting the first-level cache memory is zero, outputting a processing result as a response of the instruction interface unit to the inserted instruction; if the data source is a second-level cache memory, the instruction hits, and the number of channels hitting the first-level cache memory is greater than zero, outputting a processing result to be a first-level cache memory operation command line execution insertion instruction and first-level cache memory operation command line insertion data; if the data source is a first-level cache memory, the channel is a shared channel and the instruction hits, the output processing result is that the instruction interface unit responds to the inserted instruction; if the data source is a first-level cache memory, the channel is a shared channel and the instruction is not hit, outputting a processing result which is an array table instruction engine operation command line execution insertion instruction and array table instruction engine operation command line insertion data; if the data source is a first-level cache memory, the channels are shared channels, and the sum of the channel numbers hitting the first-level cache memory is equal to one, outputting a processing result to an instruction interface unit to respond to the insertion instruction; if the data source is a primary cache memory, the channels are shared channels, and the sum of the number of channels hitting the primary cache memory is greater than one, no processing is performed.
Optionally, the first processing module 72 processes the to-be-processed instruction based on the determination result, and when outputting the processing result, the processing module is specifically configured to: when the instruction type of the to-be-processed instruction is a delete instruction, the method comprises the following steps: if the data source is an array table instruction engine and the flag bit is zero, outputting a processing result that the instruction interface unit responds to the deleting instruction and the instruction interface unit responds to the deleting data; if the data source is an array table instruction engine and the flag bit is the flag bit corresponding to the first-level cache, outputting a processing result to be a first-level cache operation command line execution deleting instruction; if the data source is a first-level cache memory and the instruction hits, outputting a processing result that the instruction interface unit responds to the deleting instruction and the instruction interface unit responds to the deleting data; if the data source is a first-level cache memory and the instruction is not hit, the output processing result is that the array table instruction engine operates the command line to execute the deleting instruction.
Optionally, the instruction processing apparatus 70 further includes: a judgment module 73 and a second processing module 74; the judging module 73 is configured to judge, when the instruction to be processed is a hash table instruction, the instruction to be processed according to a data source of the instruction to be processed, a flag bit, whether the instruction hits, and a sum of channel numbers hitting a first-level cache; the second processing module 74 is configured to process the instruction to be processed based on the determination result, and output a processing result.
Optionally, the second processing module 74 processes the to-be-processed instruction based on the determination result, and when outputting the processing result, the processing module is specifically configured to: if the data source is a hash table instruction engine and the instruction is not hit, outputting a processing result to be an instruction interface unit response; if the data source is an array table instruction engine, the instruction hits and the flag bit is zero, outputting a processing result as an instruction interface unit response; if the data source is an array table instruction engine, the instruction hits and the flag bit is not zero, outputting a processing result to be a second-level cache memory operation command line; if the data source is a second-level cache memory and the sum of the channel numbers hitting the first-level cache memory is equal to one, outputting a processing result as an instruction interface unit response; if the data source is a second-level cache memory and the sum of the channel numbers hitting the first-level cache memory is not equal to one, not processing; if the data source is a first-level cache memory and the instruction is not hit, outputting a processing result as an instruction interface unit response; if the data source is a first-level cache memory, the instruction hits, and the flag bit is the flag bit corresponding to the second-level cache memory, outputting a processing result as an instruction interface unit response; if the data source is a first-level cache memory, the instruction hits, and the flag bit is the flag bit corresponding to the first-level cache memory and the flag bit corresponding to the second-level cache memory, the output processing result is the first-level cache memory operation command line.
The instruction processing apparatus of the embodiment shown in fig. 7 may be used to implement the technical solution of the above method embodiment, and its implementation principle and technical effects are similar, and are not described herein again.
Fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure. The electronic device may be a device running an instruction processing system as described in the above embodiments. The electronic device provided in the embodiment of the present disclosure may execute the processing flow provided in the embodiment of the instruction processing method, as shown in fig. 8, where the electronic device 80 includes: memory 81, processor 82, computer programs and communication interface 83; wherein the computer program is stored in the memory 81 and configured to be executed by the processor 82 for the instruction processing method as described above.
In addition, the embodiment of the present disclosure also provides a computer-readable storage medium having stored thereon a computer program that is executed by a processor to implement the instruction processing method described in the above embodiment.
Furthermore, the disclosed embodiments also provide a computer program product comprising a computer program or instructions which, when executed by a processor, implement the instruction processing method as described above.
It should be noted that the computer readable medium described in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.
In some embodiments, the clients, servers may communicate using any currently known or future developed network protocol, such as HTTP (HyperTextTransferProtocol ), and may be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), the internet (e.g., the internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future developed networks.
The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.
The computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to:
when accessing a database unloading engine, acquiring an instruction to be processed, wherein the instruction to be processed carries attribute information, and the attribute information comprises at least one of an instruction type, a data source, a flag bit, whether the instruction hits or not and whether a channel is a shared channel of the instruction to be processed;
When the instruction to be processed is an array table instruction, judging the instruction to be processed according to the instruction type, the data source, the flag bit, whether the instruction hits or not and whether the channel is a shared channel of the instruction to be processed, processing the instruction to be processed based on a judging result, and outputting a processing result.
In addition, the electronic device may also perform other steps in the instruction processing method described above.
Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, including, but not limited to, an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units involved in the embodiments of the present disclosure may be implemented by means of software, or may be implemented by means of hardware. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.
The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a Complex Programmable Logic Device (CPLD), and the like.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is merely a specific embodiment of the disclosure to enable one skilled in the art to understand or practice the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown and described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A method of instruction processing, the method comprising:
when accessing a database unloading engine, acquiring an instruction to be processed, wherein the instruction to be processed carries attribute information, and the attribute information comprises at least one of an instruction type, a data source, a flag bit, whether the instruction hits or not and whether a channel is a shared channel of the instruction to be processed;
When the instruction to be processed is an array table instruction, judging the instruction to be processed according to the instruction type, the data source, the flag bit, whether the instruction hits or not and whether the channel is a shared channel of the instruction to be processed, processing the instruction to be processed based on a judging result, and outputting a processing result;
The instruction to be processed is processed based on the judging result, and the output processing result comprises:
when the instruction type of the to-be-processed instruction is a query instruction, the method comprises the following steps:
if the data source is an array table instruction engine and the channel is a shared channel, outputting a processing result which is that the instruction interface unit responds to the query instruction and the instruction interface unit responds to the query data;
if the data source is an array table instruction engine, the channel is a shared channel and the flag bit is zero, outputting a processing result which is that the instruction interface unit responds to the query instruction and the instruction interface unit responds to the query data;
if the data source is an array table instruction engine, the channel is a shared channel, and the flag bit is the flag bit corresponding to the first-level cache, outputting a processing result to be an operation command line of the first-level cache to execute the query instruction;
If the data source is a first-level cache memory and the instruction hits, outputting a processing result that the instruction interface unit responds to the query instruction and the instruction interface unit responds to the query data;
If the data source is a first-level cache memory and the instruction is not hit, the output processing result is an array table instruction engine running command line executing query instruction.
2. The method of claim 1, wherein the instruction type of the instruction to be processed comprises any one of an insert instruction, a query instruction, and a delete instruction.
3. The method according to claim 2, wherein the processing the instruction to be processed based on the determination result, and outputting the processing result includes:
When the instruction type of the instruction to be processed is an insert instruction, the method comprises the following steps:
if the data source is an array table instruction engine and the flag bit is zero, outputting a processing result to an instruction interface unit for responding to the insertion instruction;
if the data source is an array table instruction engine and the flag bit is the flag bit corresponding to the first-level cache memory, outputting a processing result to be a first-level cache memory operation command line execution insertion instruction and first-level cache memory operation command line insertion data;
If the data source is an array table instruction engine and the flag bit is the flag bit corresponding to the second-level cache memory, outputting a processing result to be a second-level cache memory operation command line execution insertion instruction and second-level cache memory operation command line insertion data;
if the data source is a second-level cache memory and the instruction is not hit, outputting a processing result that the instruction interface unit responds to the inserted instruction;
If the data source is a second-level cache memory, the instruction hits, and the number of channels hitting the first-level cache memory is zero, outputting a processing result as a response of the instruction interface unit to the inserted instruction;
if the data source is a second-level cache memory, the instruction hits, and the number of channels hitting the first-level cache memory is greater than zero, outputting a processing result to be a first-level cache memory operation command line execution insertion instruction and first-level cache memory operation command line insertion data;
if the data source is a first-level cache memory, the channel is a shared channel and the instruction hits, the output processing result is that the instruction interface unit responds to the inserted instruction;
If the data source is a first-level cache memory, the channel is a shared channel and the instruction is not hit, outputting a processing result which is an array table instruction engine operation command line execution insertion instruction and array table instruction engine operation command line insertion data;
if the data source is a first-level cache memory, the channels are shared channels, and the sum of the channel numbers hitting the first-level cache memory is equal to one, outputting a processing result to an instruction interface unit to respond to the insertion instruction;
if the data source is a primary cache memory, the channels are shared channels, and the sum of the number of channels hitting the primary cache memory is greater than one, no processing is performed.
4. The method according to claim 2, wherein the processing the instruction to be processed based on the determination result, and outputting the processing result includes:
When the instruction type of the to-be-processed instruction is a delete instruction, the method comprises the following steps:
If the data source is an array table instruction engine and the flag bit is zero, outputting a processing result that the instruction interface unit responds to the deleting instruction and the instruction interface unit responds to the deleting data;
If the data source is an array table instruction engine and the flag bit is the flag bit corresponding to the first-level cache, outputting a processing result to be a first-level cache operation command line execution deleting instruction;
If the data source is a first-level cache memory and the instruction hits, outputting a processing result that the instruction interface unit responds to the deleting instruction and the instruction interface unit responds to the deleting data;
if the data source is a first-level cache memory and the instruction is not hit, the output processing result is that the array table instruction engine operates the command line to execute the deleting instruction.
5. The method according to claim 1, wherein the method further comprises:
When the instruction to be processed is a hash table instruction, judging the instruction to be processed according to the sum of the data source, the flag bit, whether the instruction hits or not and the channel number hitting the first-level cache memory of the instruction to be processed;
and processing the instruction to be processed based on the judging result, and outputting a processing result.
6. The method of claim 5, wherein processing the instruction to be processed based on the determination result, outputting a processing result, comprises:
if the data source is a hash table instruction engine and the instruction is not hit, outputting a processing result to be an instruction interface unit response;
If the data source is an array table instruction engine, the instruction hits and the flag bit is zero, outputting a processing result as an instruction interface unit response;
if the data source is an array table instruction engine, the instruction hits and the flag bit is not zero, outputting a processing result to be a second-level cache memory operation command line;
if the data source is a second-level cache memory and the sum of the channel numbers hitting the first-level cache memory is equal to one, outputting a processing result as an instruction interface unit response;
If the data source is a second-level cache memory and the sum of the channel numbers hitting the first-level cache memory is not equal to one, not processing;
If the data source is a first-level cache memory and the instruction is not hit, outputting a processing result as an instruction interface unit response;
If the data source is a first-level cache memory, the instruction hits, and the flag bit is the flag bit corresponding to the second-level cache memory, outputting a processing result as an instruction interface unit response;
If the data source is a first-level cache memory, the instruction hits, and the flag bit is the flag bit corresponding to the first-level cache memory and the flag bit corresponding to the second-level cache memory, the output processing result is the first-level cache memory operation command line.
7. An instruction processing apparatus, comprising:
the acquisition module is used for acquiring an instruction to be processed when accessing the database unloading engine, wherein the instruction to be processed carries attribute information, and the attribute information comprises at least one of an instruction type, a data source, a flag bit, whether the instruction hits or not and whether a channel is a shared channel of the instruction to be processed;
The first processing module is used for judging the instruction to be processed according to the instruction type, the data source, the zone bit, whether the instruction hits or not and whether the channel is a shared channel of the instruction to be processed when the instruction to be processed is an array table instruction, processing the instruction to be processed based on a judging result, and outputting a processing result;
The first processing module processes the to-be-processed instruction based on the judging result, and is specifically used for:
when the instruction type of the to-be-processed instruction is a query instruction, the method comprises the following steps:
if the data source is an array table instruction engine and the channel is a shared channel, outputting a processing result which is that the instruction interface unit responds to the query instruction and the instruction interface unit responds to the query data;
if the data source is an array table instruction engine, the channel is a shared channel and the flag bit is zero, outputting a processing result which is that the instruction interface unit responds to the query instruction and the instruction interface unit responds to the query data;
if the data source is an array table instruction engine, the channel is a shared channel, and the flag bit is the flag bit corresponding to the first-level cache, outputting a processing result to be an operation command line of the first-level cache to execute the query instruction;
If the data source is a first-level cache memory and the instruction hits, outputting a processing result that the instruction interface unit responds to the query instruction and the instruction interface unit responds to the query data;
If the data source is a first-level cache memory and the instruction is not hit, the output processing result is an array table instruction engine running command line executing query instruction.
8. An electronic device, comprising:
A memory;
A processor; and
A computer program;
Wherein the computer program is stored in the memory and configured to be executed by the processor to implement the method of any one of claims 1-6.
9. A computer readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, implements the method according to any of claims 1-6.
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