CN117075836B - Anti-interference device for display signal, display and electronic equipment - Google Patents

Abstract

The application provides an anti-interference device for display signals, a display and electronic equipment, and relates to the technical field of display processing, wherein the anti-interference device is connected with an embedded display interface (EDP); the tamper resistant device is configured to: when the EDP signal is detected to have an interference signal, a low-level voltage is input to a hot plug detection HPD signal in the EDP signal, and when the EDP signal is detected to disappear, a zero voltage is input to the HPD signal, so that the HPD signal is changed from a low level to a high level, and a virtual hot plug action is generated. The anti-interference device has the advantages of no influence on EDP signals and good anti-interference effect on interference signals.

Description

An anti-interference device, display and electronic equipment for displaying signals

Technical field

The present application relates to the field of display processing technology, and in particular to an anti-interference device for display signals, a display and electronic equipment.

Background technique

In current notebook computers, the motherboard CPU and the timing controller (Tcon) chip of the display screen usually use the embedded display interface (Embedded Display PORT, EDP) signal to communicate, so the EDP screen is used between the motherboard and the display screen. wire connection. Due to the long signal wiring, it is easy to be interfered when the protection is insufficient. Especially when doing some anti-interference tests, the EDP signal is prone to be interfered, resulting in blurred screens, stuck and other phenomena.

A typical current interference test item is the CPI (Cell Phone Interfere) test, which is also the most frequently failed test item for display devices. It is an interference signal generated by an interference signal generator that is modulated, amplified, coupled to a customized antenna, and then interferes with the Equipment Under Test (EUT) through the antenna.

At present, the following two methods are usually used to achieve anti-interference:

The first method: add a small capacitor on the EDP screen line or add a common mode inductor filter on the differential signal line; however, the capacitor or inductor will damage the signal and is not suitable for scenarios with fast signal transmission rates;

The second method: EDP screen wires are wrapped with conductive cloth or differential lines using shielded coaxial cables; however, since thicker conductive cloth cannot be used and the overlap between circles is short, the shielding effect is not ideal, and the use Shielded coaxial cable is too expensive.

Contents of the invention

In view of this, this application proposes an anti-interference device, display and electronic equipment for display signals to solve the technical problems of existing display anti-interference technical solutions such as damage to the signal, unsatisfactory shielding effect and high price. .

In one possible implementation, the anti-interference device is connected to the embedded display interface EDP; the anti-interference device is configured to: when an interference signal is detected in the EDP signal, detect the HPD signal to the hot plug in the EDP signal. Input a low-level voltage. When the interference signal in the EDP signal is detected to disappear, zero voltage is input to the HPD signal, causing the HPD signal to change from low level to high level, resulting in a virtual hot plug action.

In one possible implementation, the embedded display interface EDP includes N pairs of differential signal terminals and one HPD pin;

The anti-interference device includes N first anti-interference circuits; the first anti-interference circuit includes: a differential amplifier circuit and a first voltage comparator; wherein, one differential amplifier circuit is connected to a pair of differential signal terminals; the differential The amplifier circuit outputs the voltage difference of the differential signal to the first voltage comparator; the first voltage comparator is connected to the HPD pin and inputs a low level voltage or zero voltage to the HPD pin.

In one possible implementation, the differential amplification circuit includes an operational amplifier, a first resistor, a second resistor, a third resistor and a fourth resistor; wherein the first resistor, the second resistor, the third resistor and the fourth resistor The resistances of Between the non-inverting input terminals of the operational amplifier, the other terminal of the third resistor is connected to the output terminal of the operational amplifier; one terminal of the second resistor is connected to the second signal terminal of the differential signal terminal, and the other terminal of the second resistor is connected to the operational amplifier. The inverting input end of the amplifier; one end of the fourth resistor is connected between the second resistor and the inverting input end of the operational amplifier, and the other end of the fourth resistor is grounded; the output end of the operational amplifier is connected to the inverting input end of the operational amplifier. The non-inverting input terminal of a voltage comparator is connected.

In one possible implementation, the input voltage of the non-inverting input terminal of the first voltage comparator is the voltage difference of the differential signal; the input voltage of the inverting input terminal of the first voltage comparator is the maximum that the EDP signal can withstand. voltage; when the input voltage of the non-inverting input terminal of the first voltage comparator is greater than or equal to the input voltage of the inverting input terminal, the output terminal of the first voltage comparator outputs the low-level voltage of the HPD signal to the HPD pin, otherwise, the The output terminal of the first voltage comparator outputs zero voltage to the HPD pin.

In one possible implementation, the embedded display interface EDP also includes a single-ended signal terminal;

The anti-interference device further includes a second anti-interference circuit; the second anti-interference circuit includes a second voltage comparator; wherein the input voltage of the non-inverting input terminal of the second voltage comparator is the voltage of the single-ended signal terminal; The input voltage of the reverse input terminal of the voltage comparator is the maximum voltage of the EDP signal; when the input voltage of the non-inverting input terminal of the voltage comparator is greater than or equal to the input voltage of the reverse input terminal, the output terminal of the first voltage comparator leads to the HPD. pin outputs the low-level voltage of the HPD signal; otherwise, the output terminal of the first voltage comparator outputs zero voltage to the hot HPD pin.

In one possible implementation, the interference signal is a periodic signal.

In a second aspect, an embodiment of the present application provides a display, including: a timing controller Tcon chip and an anti-interference device for display signals according to the embodiment of the present application; the timing controller Tcon chip includes an embedded display interface EDP; the embedded Type display interface EDP and anti-interference device connection.

In a third aspect, embodiments of the present application provide an electronic device, including a motherboard and a display according to an embodiment of the present application; the motherboard is connected to the embedded display interface EDP of the display through an EDP signal line; the EDP signal line includes a main channel Main -Link and hot plug detection HPD signal lines; the main channel Main-Link includes N differential signal line pairs.

In one possible implementation, the differential amplifier circuit of each first anti-interference circuit inputs the voltage difference of the differential signal to the non-inverting input terminal of the first voltage comparator; when the first voltage comparator of any first anti-interference circuit The input voltage of the non-inverting input terminal is greater than or equal to the input voltage of the inverting input terminal. The output terminal of the first voltage comparator outputs the low-level voltage of the HPD signal to the HPD pin. When the input voltage of the non-inverting input terminal of the first voltage comparator If the input voltage is less than the reverse input terminal, zero voltage is input to the HPD pin; when the HPD signal changes from low level to high level, the motherboard is triggered to re-send display data to the Tcon chip through the main channel Main-Link.

In one possible implementation, when the input voltage of the non-inverting input terminal of the second voltage comparator of any second anti-interference circuit is greater than or equal to the input voltage of the inverting input terminal, the output terminal of the second voltage comparator supplies the HPD The pin outputs the low-level voltage of the HPD signal. When the input voltage of the non-inverting input terminal of the second voltage comparator is less than the input voltage of the inverting input terminal, zero voltage is input to the HPD pin; when the HPD signal changes from low level to high level, ping, triggering the main chip to re-send display data to the Tcon chip through the main channel Main-Link.

The anti-interference device of the present application has the advantages of having no impact on EDP signals and good anti-interference effect on interference signals.

Description of drawings

Figure 1 is a schematic diagram of an EDP interface connector according to an embodiment of the present application;

Figure 2 is a schematic diagram of three states of HDP signals according to the embodiment of the present application;

Figure 3 is a schematic diagram showing a signal anti-interference design route according to an embodiment of the present application;

Figure 4 is a structural diagram of an anti-interference device for display signals according to an embodiment of the present application;

Figure 5 is a structural diagram of the first anti-interference circuit according to the embodiment of the present application;

Figure 6 is a structural diagram of the second anti-interference circuit according to the embodiment of the present application;

Figure 7 is a structural diagram of a display according to an embodiment of the present application;

Figure 8 is a structural diagram of an electronic device according to an embodiment of the present application.

Attached image identification:

R1: the first resistor; R2: the second resistor; R3: the third resistor; R4: the fourth resistor;

A: operational amplifier; B: first voltage comparator; C: second voltage comparator.

Detailed ways

Various aspects and features of the present application are described herein with reference to the accompanying drawings.

It will be understood that various modifications may be made to the embodiments claimed herein. Therefore, the above description should not be viewed as limiting, but merely as examples of embodiments. Other modifications within the scope and spirit of this application will occur to those skilled in the art.

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the application and, together with the general description of the application given above and the detailed description of the embodiments given below, serve to explain the application. principle.

These and other features of the present application will become apparent from the following description of preferred forms of embodiments given as non-limiting examples with reference to the accompanying drawings.

It will also be understood that, although the present application has been described with reference to a few specific examples, those skilled in the art will be able to undoubtedly implement many other equivalent forms of the present application.

The above and other aspects, features and advantages of the present application will become more apparent in view of the following detailed description when taken in conjunction with the accompanying drawings.

Hereinafter, specific embodiments of the present application will be described with reference to the accompanying drawings; however, it should be understood that the applied embodiments are merely examples of the present application, which can be implemented in various ways. Well-known and/or repeated functions and structures have not been described in detail to avoid obscuring the application with unnecessary or redundant detail. Therefore, specific structural and functional details claimed herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach one skilled in the art to variously utilize the present invention in substantially any suitable detailed structure. Apply.

This specification may use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in further embodiments," which may refer to the same thing in accordance with the present application. or one or more of the different embodiments.

First, the design ideas of the embodiments of the present application are briefly introduced.

In current laptops, EDP signals are usually used to communicate between the motherboard CPU and the Tcon chip of the display screen, so the motherboard and the display screen are connected using EDP screen cables. EDP is a fully digital interface based on the DisplayPort architecture and protocol. It can use simpler connectors and fewer pins to transmit high-resolution signals, as shown in Figure 1, and the data transmission rate is much higher than LVDS. (Low-Voltage Differential Signaling), this is an important reason why the EDP interface replaces the LVDS interface. The EDP interface signal mainly consists of three parts: Main-Link, AUX CH and HPD. Main Link represents the main channel, used to transmit various types of video data and audio data; AUX CH represents the auxiliary channel, used to transmit data with low bandwidth requirements, as well as link management and device control signals; HPD represents the hot plug detection channel.

Main-Link consists of 1 to 4 pairs of data lines, and each pair of data lines is a pair of differential lines. For an LCD screen, the number of Main-Link data lines depends on the screen's resolution and color bits. The signals transmitted in this channel include video pixel signals, video timing signals, video format signals, bit/pixel and color space signals and error correction signals of video signals, and the ANXI8B/10B encoding method is used to improve the accuracy of data transmission. Data transmission uses AC coupling technology, and the sending end and receiving end have different common mode voltages, so the interface can be made smaller. ANSI8B/10B encoding first divides a set of continuous 8-bit data into two sets of data, one set of 3-bit data and a set of 5-bit data, and then encoded to obtain a set of 4-bit and 6-bit binary data. AUX CH is a bidirectional half-duplex transmission channel. Its signal adopts AC coupling differential transmission method. The signal adopts Manchesterll encoding, with a transmission rate of 1Mbps and a transmission distance of 15m. The delay time of each transmission task is less than 500μs. HPD is a one-way channel used to connect and interrupt lines.

At present, the following two methods are usually used to achieve anti-interference of EDP signals:

The first method: add a small capacitor on the EDP screen line or add a common mode inductor filter on the differential signal line; however, the capacitor or inductor will damage the signal and is not suitable for scenarios with fast signal transmission rates;

The second method: EDP screen wires are wrapped with conductive cloth or differential lines using shielded coaxial cables; however, since thicker conductive cloth cannot be used and the overlap between circles is short, the shielding effect is not ideal, and the use Shielded coaxial cable is too expensive.

As shown in Figure 2, the HPD signal in the EDP signal has three states:

Under normal circumstances, HPD is a low-voltage pulse signal, and the time is less than HPD_Timeout;

In the unplugged state, HPD becomes low level and the time is greater than HPD_Timeout. At this time, the main chip waits for HPD to become high level. In this state, the main chip enters protection mode and detects the HPD signal status. A 100K pull-down resistor on the HPD to detect whether it is unplugged.

In the inserted state, the main chip detects that the HPD signal changes from low level to high level, and the main chip will restart transmitting display data.

In view of the above technical problems and the above three states of the HPD signal, the design idea of this application is: when the EDP signal is interfered with, a virtual hot plug action is created in which HPD changes from low level to high level, which can trigger the main chip ( CPU on the motherboard) retransmits the display data and restores normal display.

To this end, as shown in Figure 3, this application proposes the following technical solution: when an interference signal (such as a CPI test signal) is coupled to an EDP signal and generates a coupling voltage, the voltage on the EDP signal is greater than or equal to what it can withstand. When the maximum voltage Vt is reached, data transmission errors may occur, resulting in abnormal display. At this time, the designed anti-interference circuit gives a hot plug signal to the HPD signal in the EDP signal, making the main chip think that there is a hot plug action, so that the main chip resends the EDP signal data to achieve the purpose of restarting data transmission. Return the display to normal. And when there is no interference signal, the anti-interference circuit will not affect normal signal performance.

This solution can theoretically solve most interference problems, but it cannot theoretically solve the very special situation where the interference voltage is infinitely close to the threshold voltage but interference will occur. However, this situation rarely occurs. Since the CPI test signal energy is relatively high, it will basically exceed the threshold voltage without other anti-interference countermeasures such as shielding.

The anti-interference device of the present application has the advantages of no impact on EDP signals, low price, and good anti-interference effect on interference signals.

After introducing the application scenarios and design ideas of the embodiments of the present application, the technical solutions provided by the embodiments of the present application will be described below.

As shown in Figure 4, the embodiment of the present application provides an anti-interference device for display signals. The anti-interference device is connected to the embedded display interface EDP; the anti-interference device is configured to: when an interference signal is detected in the EDP signal , input a low level voltage to the hot plug detection HPD signal in the EDP signal. When the interference signal in the EDP signal is detected to disappear, zero voltage is input to the HPD signal, causing the HPD signal to change from low level to high level, resulting in A virtual hot plug action.

For example, the EDP signal contains 1-4 differential signal pairs for transmitting data, hot plug HPD signals and some other signals. During differential signal transmission, the signal receiving end compares the difference between the two voltages to determine the logic state sent by the transmitting end. When there is no interference signal in the differential signal or the interference signal is very weak, the voltage difference of the differential signal is less than the maximum voltage that the EDP signal can withstand. When the interference signal is very strong, the voltage difference of the differential signal will be greater than or equal to the EDP signal. The maximum voltage it can withstand.

In one embodiment of the present application, the embedded display interface EDP includes N pairs of differential signal terminals and one HPD pin;

The anti-interference device includes N first anti-interference circuits; the first anti-interference circuit includes: a differential amplifier circuit and a first voltage comparator; wherein, one differential amplifier circuit is connected to a pair of differential signal terminals; the differential The amplifier circuit outputs the voltage difference of the differential signal to the first voltage comparator; the first voltage comparator is connected to the HPD pin and inputs a low level voltage or zero voltage to the HPD pin.

Specifically, as shown in Figure 5, the differential amplification circuit includes an operational amplifier A, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; wherein, the first resistor R1, the second resistor R2, and the fourth resistor R4. The three resistors R3 and the fourth resistor R4 have the same resistance value; one end of the first resistor R1 is connected to the first signal end of the differential signal end, and the other end of the first resistor R1 is connected to the non-inverting input end of the operational amplifier A; One end of the third resistor R3 is connected between the first resistor R1 and the non-inverting input end of the operational amplifier A, the other end of the third resistor R3 is connected to the output end of the operational amplifier A; one end of the second resistor R2 is connected to the differential The second signal end of the signal end, the other end of the second resistor R2 is connected to the inverting input end of the operational amplifier A; one end of the fourth resistor R4 is connected to the second resistor R2 and the inverting input end of the operational amplifier A The other end of the fourth resistor R4 is connected to ground; the output end of the operational amplifier A is connected to the non-inverting input end of the first voltage comparator B.

Correspondingly, the input voltage of the non-inverting input terminal of the first voltage comparator B is the voltage difference of the differential signal; the input voltage of the inverting input terminal of the first voltage comparator B is the maximum voltage that the EDP signal can withstand; when The input voltage of the non-inverting input terminal of the first voltage comparator B is greater than or equal to the input voltage of the inverting input terminal, and the output terminal of the first voltage comparator B outputs the low-level voltage of the HPD signal to the HPD pin. Otherwise, the first voltage comparator B The output of a voltage comparator outputs zero voltage to the hot HPD pin.

For example, the two voltages of the differential signal are Vp and Vn respectively, Vp is input to the non-inverting input terminal (+) of the operational amplifier A, and Vn is input to the inverting input terminal (-) of the operational amplifier A; then the output terminal of the operational amplifier outputs a voltage Difference Vd=Vp-Vn; the voltage difference Vd is input to the non-inverting input terminal (+) of voltage comparator B, and the reverse input terminal (-) of voltage comparator B is the maximum voltage Vt that the EDP signal of the EDP signal can withstand. -VHPD is the low-level voltage of the HPD signal, and the Vout output is connected to the HPD pin.

When the differential signal is not interfered with or the interference is small, Vd is less than Vt, then the Vout output is Vout=0V, which does not affect the HPD signal at this time. When the differential signal is interfered so that the coupled voltage is greater than or equal to the maximum voltage it can withstand, that is, Vd is greater than or equal to Vt, the output of Vout is -VHPD; at this time, the HPD signal will become a continuous low level. When the interference signal disappears, the Vout output becomes 0V, causing the HPD to change from low level to high level. Then the main chip will detect a virtual hot plug action, and will resend the display data and restore Normal data transfer. What the user intuitively sees is that the display returns to its normal state from abnormal states such as stuck or blurred screens.

The input and output logic levels of the anti-interference circuit are as shown in Table 1:

Table 1

In addition, for some single-ended signals in the EDP signal, there is no need for operational amplifier A, only a voltage comparator is needed, and the single-ended signal is connected to the non-inverting input of the voltage comparator.

In one embodiment of the present application, the embedded display interface EDP also includes a single-ended signal terminal; the anti-interference device further includes a second anti-interference circuit; the second anti-interference circuit includes a second voltage comparator ; Wherein, the input voltage of the non-inverting input terminal of the second voltage comparator is the voltage of the single-ended signal terminal; the input voltage of the reverse input terminal of the voltage comparator is the maximum voltage that the EDP signal can withstand; when the voltage comparator The input voltage of the non-inverting input terminal is greater than or equal to the input voltage of the inverting input terminal. The output terminal of the first voltage comparator outputs the low-level voltage of the HPD signal to the HPD pin. Otherwise, the output terminal of the first voltage comparator outputs the low-level voltage of the HPD signal to the HPD pin. The hot HPD pin outputs zero voltage.

As shown in Figure 6, the second anti-interference circuit includes a second voltage comparator C. For example, the single-ended signal voltage Vp is input to the non-inverting input terminal (+) of the second voltage comparator C. The reverse input terminal (-) is the maximum voltage Vt that the EDP signal can withstand. -VHPD is the low-level voltage of the HPD signal, and the Vout output is connected to the HPD pin.

When the single-ended signal is not interfered with or the interference is small, and Vp is less than Vt, the Vout output is Vout=0V, which does not affect the HPD signal at this time. When the single-ended signal is interfered so that the coupled voltage is greater than or equal to the maximum voltage it can withstand, that is, Vp is greater than or equal to Vt, the output of Vout is -VHPD; at this time, the HPD signal will become a continuous low level. When the interference signal disappears, the Vout output becomes 0V, causing the HPD to change from low level to high level. Then the main chip will detect a virtual hot plug action, and will resend the display data and restore Normal data transfer. What the user intuitively sees is that the display returns to its normal state from abnormal states such as stuck or blurred screens.

From the actual test of the CPI test signal, it is found that the frequency point most likely to fail is near 900MHz, then its period T=1.1ns. The response time of a general voltage comparator is tens of ns, which cannot meet the requirements. There are currently some high-speed comparators whose response time is at the Ps level, which can meet the requirements. For example, the model is MAX40025A/MAX40025C/MAX40026 or the faster integrated chip HMC974LC3C. The performance requirements of general comparators can also be met by adding a delay circuit. For other interference signals such as ESD interference, the half-wavelength is tens of ns, and a general comparator can be used. There are other interference signals that may last longer. This embodiment controls the signal with the reset function through circuit design, and achieves the purpose of anti-interference by restarting data transmission.

It can be seen from the design of the above anti-interference circuit that each group of differential signals in the EDP signal requires an anti-interference circuit, which may be more expensive. However, the anti-interference circuit can reduce other anti-interference costs, such as the conductive cloth of the EDP shielding line. , the coaxial line used by EDP signal, etc. In order to reduce costs, anti-interference circuits can be added for signals that are prone to problems in EDP signals, or they can be integrated as much as possible and integrate multiple anti-interference circuits into one chip to further reduce space and cost.

Another point that needs to be explained is that the interference signal is a periodic signal. For example, the CPI interference signal is a periodic signal with a period of ns. When the interference signal is at a high level and is greater than or equal to Vt, Vout outputs a low voltage signal. When the interference voltage is at low level, its value is less than Vt, and the output is high level. In this way, the interference signal will cause the HPD to complete the action from low level to high level within one cycle. Or when the interference signal is relatively short and disappears suddenly, Vout will also output a high level, causing the HPD to complete the action from low level to high level. If the duration of the interference signal is too short, it can be matched by a delay circuit.

Based on the same inventive idea, an embodiment of the present application provides a display, including: a timing controller Tcon chip and an anti-interference device for display signals in the embodiment of the present application; the timing controller Tcon chip includes an embedded display interface EDP; The embedded display interface EDP is connected to the anti-interference device.

The display may be a vehicle-mounted display device or a television, or may be a display of a mobile phone, a tablet computer, a notebook computer, or a computer. The embodiments of this application do not specifically limit the display. It should be noted that the display receives display data through an EDP interface. The display of this embodiment has the same technical effect as the anti-interference device, that is, it has the advantages of having no impact on the EDP signal and good anti-interference effect on the interference signal.

Based on the same inventive idea, as shown in Figure 7, an embodiment of the present application provides an electronic device, including a motherboard and a display of an embodiment of the present application; the motherboard is connected to the embedded display interface EDP of the display through an EDP signal line; so The EDP signal line includes a main channel Main-Link and a hot plug detection HPD signal line; the main channel Main-Link includes N differential signal line pairs.

The differential amplifier circuit of each first anti-interference circuit inputs the voltage difference of the differential signal to the non-inverting input terminal of the first voltage comparator; when the input voltage of the non-inverting input terminal of the first voltage comparator of any first anti-interference circuit is greater than or equal to The input voltage of the reverse input terminal, the output terminal of the first voltage comparator outputs the low-level voltage of the HPD signal to the HPD pin, when the input voltage of the non-inverting input terminal of the first voltage comparator is less than the input voltage of the reverse input terminal, Input zero voltage to the HPD pin; when the HPD signal changes from low level to high level, the main chip is triggered to re-send display data to the Tcon chip through the main channel Main-Link.

When the input voltage of the non-inverting input terminal of the second voltage comparator of any second anti-interference circuit is greater than or equal to the input voltage of the inverting input terminal, the output terminal of the second voltage comparator outputs the low level of the HPD signal to the HPD pin. voltage, when the input voltage of the non-inverting input terminal of the second voltage comparator is less than the input voltage of the inverting input terminal, zero voltage is input to the HPD pin; when the HPD signal changes from low level to high level, the main chip is triggered to pass the main channel Main -Link resends display data to the Tcon chip.

The electronic device shown in FIG. 8 is only for schematic illustration. The display device may be an electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, a computer, etc.; the embodiments of this application are not specifically limited. What needs to be made clear is that the main chip of the electronic device transmits display data to the display through the EDP interface, and the display receives the display data through the EDP interface.

The electronic equipment according to the embodiment of the present application has the same technical effect as the anti-interference device in the above embodiment, that is, it has the advantages of having no impact on the EDP signal and good anti-interference effect on the interference signal.

Furthermore, while illustrative embodiments are described herein, the scope includes any and all alternatives, modifications, omissions, combinations (e.g., combinations of aspects across various embodiments), adaptations, or changes based on the present disclosure. All examples. Elements in the claims are to be interpreted broadly based on the language used in the claims, and not limited to the examples described in this specification or during the lifetime of this application. Furthermore, the steps of the disclosed methods may be modified in any way, including by reordering steps or inserting or deleting steps. It is therefore intended that the description be considered as examples only, with the true scope being indicated by the following claims and their full scope of equivalents.

The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. After reading the above description, other embodiments may be utilized by, for example, one of ordinary skill in the art. Furthermore, in the above detailed description, various features may be combined together to simplify the present disclosure. This should not be construed to mean that no disclosed feature is intended to be essential to any claim. Thus, the following claims are incorporated into the Detailed Description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that these embodiments may be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims (9)

1. An anti-interference device for displaying signals, characterized in that the anti-interference device is connected to an embedded display interface EDP; The embedded display interface EDP includes N pairs of differential signal terminals and one HPD pin; The anti-interference device includes N first anti-interference circuits; the first anti-interference circuit includes: a differential amplifier circuit and a first voltage comparator; wherein, one differential amplifier circuit is connected to a pair of differential signal terminals; the differential The amplifier circuit outputs the voltage difference of the differential signal to the first voltage comparator; the first voltage comparator is connected to the HPD pin and inputs a low level voltage or zero voltage to the HPD pin; When there is an interference signal in the differential signal and the differential signal is interfered so that its coupling voltage is greater than or equal to the maximum voltage it can withstand, a low-level voltage - VHPD is input to the hot plug detection HPD signal in the differential signal. ; When the interference signal in the differential signal disappears and the voltage difference of the differential signal is less than the maximum voltage that can be tolerated, zero voltage is input to the HPD signal, causing the HPD signal to change from low level to high level, generating a Virtual hot plug action. 2. The anti-interference device for display signals according to claim 1, wherein the differential amplification circuit includes an operational amplifier, a first resistor, a second resistor, a third resistor and a fourth resistor; wherein the first resistor The resistance values of the second resistor, the third resistor and the fourth resistor are the same; one end of the first resistor is connected to the first signal end of the differential signal end, and the other end of the first resistor is connected to the non-inverting input end of the operational amplifier; so One end of the third resistor is connected between the first resistor and the non-inverting input end of the operational amplifier, the other end of the third resistor is connected to the output end of the operational amplifier; one end of the second resistor is connected to the second signal of the differential signal end. end, the other end of the second resistor is connected to the inverting input end of the operational amplifier; one end of the fourth resistor is connected between the second resistor and the inverting input end of the operational amplifier, and the other end of the fourth resistor is connected to the inverting input end of the operational amplifier. One end is connected to ground; the output end of the operational amplifier is connected to the non-inverting input end of the first voltage comparator. 3. The anti-interference device for display signals according to claim 2, characterized in that the input voltage of the non-inverting input terminal of the first voltage comparator is the voltage difference of the differential signal; The input voltage of the input terminal is the maximum voltage that the EDP signal can withstand; when the input voltage of the non-inverting input terminal of the first voltage comparator is greater than or equal to the input voltage of the inverting input terminal, the output terminal of the first voltage comparator is output to the HPD pin The low-level voltage of the HPD signal, otherwise, the output terminal of the first voltage comparator outputs zero voltage to the HPD pin. 4. The anti-interference device for display signals according to claim 1, wherein the embedded display interface EDP further includes a single-ended signal terminal; The anti-interference device further includes a second anti-interference circuit; the second anti-interference circuit includes a second voltage comparator; wherein the input voltage of the non-inverting input terminal of the second voltage comparator is the voltage of the single-ended signal terminal; The input voltage of the reverse input terminal of the voltage comparator is the maximum voltage of the EDP signal; when the input voltage of the non-inverting input terminal of the voltage comparator is greater than or equal to the input voltage of the reverse input terminal, the output terminal of the first voltage comparator leads to the HPD. pin outputs the low-level voltage of the HPD signal; otherwise, the output end of the first voltage comparator outputs zero voltage to the HPD pin. 5. The anti-interference device for display signals according to claim 1, wherein the interference signal is a periodic signal. 6. A display, characterized in that it includes: a timing controller Tcon chip and an anti-interference device for display signals according to any one of claims 1 to 5; the timing controller Tcon chip includes an embedded display interface EDP; Embedded display interface EDP and anti-interference device connection. 7. An electronic device, characterized in that it includes a motherboard and the display of claim 6; the motherboard is connected to the embedded display interface EDP of the display through an EDP signal line; the EDP signal line includes a main channel Main-Link and a thermal Plug and pull detection HPD signal line; the main channel Main-Link includes N differential signal line pairs. 8. The electronic device according to claim 7, characterized in that the differential amplifier circuit of each first anti-interference circuit inputs the voltage difference of the differential signal to the non-inverting input terminal of the first voltage comparator; when any first anti-interference circuit The input voltage of the non-inverting input terminal of the first voltage comparator of the interference circuit is greater than or equal to the input voltage of the inverting input terminal. The output terminal of the first voltage comparator outputs the low-level voltage of the HPD signal to the HPD pin. When the first voltage The input voltage of the non-inverting input terminal of the comparator is less than the input voltage of the inverting input terminal, and zero voltage is input to the HPD pin; when the HPD signal changes from low level to high level, the motherboard is triggered to re-send the signal to the Tcon chip through the main channel Main-Link. Display Data. 9. The electronic device according to claim 7, characterized in that when the input voltage of the non-inverting input terminal of the second voltage comparator of any second anti-interference circuit is greater than or equal to the input voltage of the inverting input terminal, the second The output terminal of the voltage comparator outputs the low-level voltage of the HPD signal to the HPD pin. When the input voltage of the non-inverting input terminal of the second voltage comparator is less than the input voltage of the inverting input terminal, zero voltage is input to the HPD pin; when the HPD signal Changing from low level to high level triggers the main chip to re-send display data to the Tcon chip through the main channel Main-Link.