CN117075677A - Voltage regulator and signal amplifying circuit - Google Patents

Abstract

A voltage regulator and a signal amplifying circuit are provided. The voltage regulator includes an error amplification circuit, an output stage circuit, and an output feedback path. The error amplifying circuit includes a first stage amplifier and a second stage amplifier. The first stage amplifier is used for amplifying a difference value between the output feedback signal and the reference signal to generate a first differential signal and a second differential signal. The second-stage amplifier is used for amplifying the difference value of the first differential signal and the second differential signal to generate an output control signal. The output stage circuit is coupled to the first power terminal and includes a switch. The switch is used for generating an output signal at the output node according to the output control signal. The output feedback path is coupled to the output node and the error amplifying circuit, and is used for generating an output feedback signal according to the output signal.

Description

Voltage regulator and signal amplifying circuit

Technical Field

The present disclosure relates to voltage regulators, and more particularly, to a voltage regulator and a signal amplifying circuit capable of improving ringing phenomenon.

Background

The traditional linear voltage stabilizing circuit is composed of an error amplifying circuit, a power transistor and a feedback circuit. The error amplifying circuit controls the conduction degree of the power transistor according to the comparison result between the feedback signal and the reference signal so as to generate stable output voltage. In the conventional linear voltage stabilizing circuit, the error amplifying circuit generally has a transistor with a larger size to reduce noise, but this design may cause a larger parasitic component to reduce a phase margin (phase margin), so that the output voltage is easy to generate ringing (ringing) phenomenon when the load changes, and a longer stabilizing time is required. However, based on the requirements of high quality communication and video streaming, the electronic devices are continuously developed towards high speed and high resolution, so that the conventional linear voltage stabilizing circuit cannot meet the current circuit design requirements.

Disclosure of Invention

The present disclosure provides a voltage regulator that includes an error amplification circuit, an output stage circuit, and an output feedback path. The error amplifying circuit includes a first stage amplifier and a second stage amplifier. The first stage amplifier is used for amplifying a difference value between the output feedback signal and the reference signal to generate a first differential signal and a second differential signal. The second-stage amplifier is used for amplifying the difference value of the first differential signal and the second differential signal to generate an output control signal. The output stage circuit is coupled to the first power terminal and includes a switch. The switch is used for generating an output signal at the output node according to the output control signal. The output feedback path is coupled to the output node and the error amplifying circuit, and is used for generating an output feedback signal according to the output signal.

The present disclosure provides a signal amplifying circuit including an error amplifying circuit and an output stage circuit. The error amplifying circuit includes a first stage amplifier and a second stage amplifier. The first stage amplifier is used for amplifying a difference value between the first input signal and the second input signal to generate a first differential signal and a second differential signal. The second-stage amplifier is used for amplifying the difference value of the first differential signal and the second differential signal to generate an output control signal. The output stage circuit is coupled to the first power terminal and includes a switch. The switch is used for generating an output signal at the output node according to the output control signal.

The voltage regulator and the signal amplifying circuit have the advantages of low noise and improved ringing phenomenon.

Drawings

FIG. 1A is a functional block diagram of a voltage regulator according to an embodiment of the present disclosure.

FIG. 1B is a functional block diagram of a voltage regulator according to an embodiment of the present disclosure.

Fig. 2 is a schematic diagram of an error amplifying circuit according to an embodiment of the disclosure.

Fig. 3 is a schematic diagram of a common mode feedback circuit according to an embodiment of the disclosure.

Fig. 4 is a frequency response curve of a prior art voltage regulator.

Fig. 5 is a frequency response curve of a voltage regulator according to an embodiment of the present disclosure.

Fig. 6 is a schematic diagram of an error amplifying circuit according to an embodiment of the disclosure.

Fig. 7 is a schematic diagram of an error amplifying circuit according to an embodiment of the disclosure.

Fig. 8 is a functional block diagram of a signal amplifying circuit according to an embodiment of the disclosure.

Detailed Description

Embodiments of the present disclosure will be described below with reference to the accompanying drawings. In the drawings, like reference numerals designate identical or similar components or process flows.

Fig. 1A is a functional block diagram of a voltage regulator 100A according to an embodiment of the present disclosure. The voltage regulator 100A includes an error amplifying circuit 110, an output stage circuit 120 and an output feedback path 130A. The error amplifying circuit 110 is configured to compare the output feedback signal Vofb with the reference signal Vref and generate the output control signal Vad based on a difference between the output feedback signal Vofb and the reference signal Vref. In one embodiment, the error amplifying circuit 110 receives the reference signal Vref at its inverting input and the output feedback signal Vofb at its non-inverting input. The output stage circuit 120 is coupled between the first power source terminal PD1 and the output node Nout, and is configured to convert the input power source VDD of the first power source terminal PD1 according to the output control signal Vad to provide the output signal Vout at the output node Nout. In addition, the output feedback path 130A is coupled between the output node Nout and the second power source terminal PD2 (e.g., the ground terminal), and is coupled to the error amplifying circuit 110 (e.g., the non-inverting input terminal). The output feedback path 130A is configured to generate an output feedback signal Vofb according to the output signal Vout. In some embodiments, the voltage regulator 100A may be implemented as a Low-dropout regulator (Low-dropout regulator, LDO regulator).

The output stage circuit 120 includes a switch Mp coupled between the first power source terminal PD1 and the output node Nout, and a control terminal thereof for receiving the output control signal Vad. The output control signal Vad is used to control the conduction of the switch Mp to convert the input power VDD into the output signal Vout. In this embodiment, the switch Mp may be implemented with a power P-type metal-oxide-semiconductor (MOS) field effect transistor.

In some embodiments, the output feedback path 130A is a voltage divider circuit and includes voltage dividing resistors R1 and R2 connected in series, wherein the voltage dividing resistors R1 and R2 are used for dividing the output signal Vout to generate the output feedback signal Vofb.

Fig. 1B is a functional block diagram of a voltage regulator 100B according to an embodiment of the present disclosure. The voltage regulator 100B is similar to the voltage regulator 100A of fig. 1A, so only differences are described below. The voltage regulator 100B includes an error amplifying circuit 110, an output stage circuit 120 and an output feedback path 130B. The output feedback path 130B is coupled to the output node Nout and the error amplifying circuit 110 (e.g., a non-inverting input). The output feedback path 130B is used to pass the output signal Vout as the output feedback signal Vofb to the error amplifying circuit 110. In some embodiments, the output feedback path 130B is a metal trace coupled between the output node Nout and the error amplification circuit 110 (e.g., non-inverting input). In some embodiments, the voltage regulator 100B may be implemented as a low drop-out voltage regulator.

Fig. 2 is a schematic diagram of an error amplifying circuit 200 according to an embodiment of the disclosure. The error amplification circuit 200 may be used to implement the error amplification circuit 110 of fig. 1A and 1B and includes a first stage amplifier 210 and a second stage amplifier 220. The first stage amplifier 210 has a first input terminal Ia1 (e.g., a non-inverting input terminal) for receiving the output feedback signal Vofb, and a second input terminal Ia2 (e.g., an inverting input terminal) for receiving the reference signal Vref. The first stage amplifier 210 is configured to amplify a difference between the output feedback signal Vofb and the reference signal Vref to generate the first differential signal Vdf and the second differential signal Vdf2, i.e., the first stage amplifier 210 is a fully differential amplifier (fully differential amplifier). On the other hand, the first input terminal Ib1 (e.g., non-inverting input terminal) of the second stage amplifier 220 is configured to receive the second differential signal Vdf2, and the second input terminal Ib2 (e.g., inverting input terminal) thereof is configured to receive the first differential signal Vdf1. The second stage amplifier 220 is configured to amplify the difference between the first differential signal Vdf1 and the second differential signal Vdf to generate the error amplified signal Vea, i.e., the second stage amplifier 220 is a differential-to-single ended amplifier (differential to single ended amplifier). In one embodiment, the error amplification signal Vea is outputted to the output stage 120 as the output control signal Vad.

The circuit structure and operation of the first stage amplifier 210 are first described below. The first stage amplifier 210 includes a first current source Sa, a full differential amplifying circuit 212, and a common mode feedback circuit 214. The first current source Sa is coupled to the first power source terminal PD1. The fully differential amplifying circuit 212 is coupled between the first current source Sa and the second power source PD2, and is configured to amplify a difference between the output feedback signal Vofb and the reference signal Vref to output the first differential signal Vdf1 and the second differential signal Vdf at the first differential node Ndf1 and the second differential node Ndf2, respectively. The common mode feedback circuit 214 is coupled to the first differential node Ndf1 and the second differential node Ndf for providing a common mode feedback signal Vcmfb to the fully differential amplifying circuit 212 according to the first differential signal Vdf and the second differential signal Vdf. The common mode feedback signal Vcmfb is used to control the conduction degree of the transistors in the fully differential amplifying circuit 212, so as to stabilize the dc common mode voltage of the first differential signal Vdf and the second differential signal Vdf.

For example, when the dc common mode voltage of the first differential signal Vdf and the second differential signal Vdf increases, the common mode feedback signal Vcmfb causes the fully differential amplifying circuit 212 to decrease the dc common mode voltage, and vice versa. In other words, the common mode feedback circuit 214 forms a voltage negative feedback path NFP with the fully differential amplifying circuit 212.

In one embodiment, the fully differential amplifying circuit 212 includes a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4. The first transistor M1 is coupled between the first current source Sa and the first differential node Ndf1, and has a control terminal for receiving the output feedback signal Vofb, such that the first transistor M1 generates the first differential signal Vdf at the first differential node Ndf1 under the control of the output feedback signal Vofb. The second transistor M2 is coupled between the first current source Sa and the second differential node Ndf, and has a control terminal for receiving the reference signal Vref, such that the second transistor M2 generates the second differential signal Vdf2 at the second differential node Ndf under the control of the reference signal Vref. The third transistor M3 is coupled between the first differential node Ndf1 and the second power source terminal PD2, and the fourth transistor M4 is coupled between the second differential node Ndf and the second power source terminal PD2, wherein a control terminal of the third transistor M3 and a control terminal of the fourth transistor M4 are configured to receive the common mode feedback signal Vcmfb. In other words, the common mode feedback signal Vcmfb is used to control the turn-on degree of the third transistor M3 and the fourth transistor M4 to stabilize the dc common mode voltage.

In one embodiment, the first transistor M1 and the second transistor M2 may be differential input pairs implemented by P-type MOS field effect transistors, and the third transistor M3 and the fourth transistor M4 may be implemented by N-type MOS field effect transistors.

Referring to fig. 3, fig. 3 is a schematic diagram of a common mode feedback circuit 214 according to an embodiment of the disclosure. In the present embodiment, the common mode feedback circuit 214 is configured to compare the first differential signal Vdf and the second differential signal Vdf with the common mode control signal Vccm, and generate the common mode feedback signal Vcmfb according to the comparison result. The common mode feedback circuit 214 includes a first amplification circuit 310 and a second amplification circuit 320. The first input terminal and the second input terminal of the first amplifying circuit 310 are respectively configured to receive the common mode control signal Vccm and the first differential signal Vdf1. The first amplifying circuit 310 is configured to amplify a difference between the first differential signal Vdf1 and the common-mode control signal Vccm to generate a first output current Io1. The first input terminal and the second input terminal of the second amplifying circuit 320 are respectively configured to receive the second differential signal Vdf and the common-mode control signal Vccm. The second amplifying circuit 320 is configured to amplify a difference between the second differential signal Vdf2 and the common-mode control signal Vccm to generate a second output current Io2. The common mode feedback circuit 214 is configured to generate a common mode feedback signal Vcmfb according to the first output current Io1 and the second output current Io2.

Structurally, the first amplifying circuit 310 includes a second current source Sb, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The second current source Sb is coupled to the first power source terminal PD1. The fifth transistor M5 is coupled between the second current source Sb and the first node N1, and has a control terminal for receiving the first differential signal Vdf1. The sixth transistor M6 is coupled between the second current source Sb and the second node N2 for providing the first output current Io1 to the second node N2, and has a control terminal for receiving the common mode control signal Vccm. The first terminal and the control terminal of the seventh transistor M7 are coupled to the first node N1 and the third node N3, and the second terminal of the seventh transistor M7 is coupled to the second power terminal PD2. The first terminal and the control terminal of the eighth transistor M8 are coupled to the second node N2 and the fourth node N4, and the second terminal of the eighth transistor M8 is coupled to the second power terminal PD2.

The second amplifying circuit 320 includes a third current source Sc, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The third current source Sc is coupled to the first power source terminal PD1. The ninth transistor M9 is coupled between the third current source Sc and the fourth node N4 for providing the second output current Io2 to the fourth node N4, and has a control terminal for receiving the common mode control signal Vccm. The tenth transistor M10 is coupled between the third current source Sc and the third node N3, and has a control terminal for receiving the second differential signal Vdf.

By means of the diode connection structure, the eighth transistor M8 can convert the first output current Io1 and the second output current Io2 into the common mode feedback signal Vcmfb at its control terminal. In an embodiment, the control terminal of the eighth transistor M8 is coupled to the control terminal of the third transistor M3 and the control terminal of the fourth transistor M4 in fig. 2.

In some embodiments, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9 and the tenth transistor M10 may be implemented with P-type MOS field effect transistors, and the seventh transistor M7 and the eighth transistor M8 may be implemented with N-type MOS field effect transistors. In an embodiment, the eighth transistor M8 may be implemented by a resistor coupled between the second node N2 and the second power supply terminal PD2.

In operation, when the dc common mode voltage of the first differential signal Vdf1 and the second differential signal Vdf is greater than the common mode control signal Vccm, the first output current Io1 and the second output current Io2 rise accordingly. Therefore, the voltage of the common mode feedback signal Vcmfb increases to increase the turn-on degree of the third transistor M3 and the fourth transistor M4 in fig. 2, thereby reducing the dc common mode voltage. Conversely, when the dc common mode voltage of the first differential signal Vdf1 and the second differential signal Vdf is smaller than the common mode control signal Vccm, the voltage of the common mode feedback signal Vcmfb decreases to increase the dc common mode voltage.

Referring to fig. 2 again, the circuit structure and operation of the second stage amplifier 220 will be described below. The second stage amplifier 220 includes a fourth current source Sd and a differential to single ended amplifying circuit 222. The fourth current source Sd is coupled between the differential-to-single-ended amplifying circuit 222 and the second power terminal PD2. The differential to single-ended amplifying circuit 222 is coupled to the first power source terminal PD1, and is configured to amplify a difference between the first differential signal Vdf and the second differential signal Vdf to output an error amplifying signal Vea.

Structurally, the differential-to-single-ended amplifying circuit 222 includes an eleventh transistor M11 and a twelfth transistor M12 that form a current mirror, and includes a thirteenth transistor M13 and a fourteenth transistor M14 that form a differential input pair. The eleventh transistor M11 is coupled between the first power source terminal PD1 and the inverting node Nnp, and its control terminal is also coupled to the inverting node Nnp. The twelfth transistor M12 is coupled between the first power source terminal PD1 and the gain node Ng, and its control terminal is coupled to the inverting node Nnp. The gain node Ng is for providing the error amplified signal Vea as the output control signal Vad. The thirteenth transistor M13 is coupled between the inverting node Nnp and the fourth current source Sd, and has a control terminal for receiving the second differential signal Vdf. The fourteenth transistor M14 is coupled between the gain node Ng and the fourth current source Sd, and has a control terminal for receiving the first differential signal Vdf1. In some embodiments, the current mirror in the differential-to-single ended amplifying circuit 222 may be replaced with other kinds of current mirrors, such as cascode current mirrors, as will be appreciated by those of ordinary skill in the art, given the benefit of this disclosure.

In some voltage regulators, the first stage amplifier of the error amplifying circuit includes a current mirror, and because the first stage amplifier contributes more to noise, the transistors of the first stage amplifier are designed to have a larger size (or width to length ratio) to reduce noise. However, when the size of the current mirror is larger, the current mirror has significant parasitic components, so that the arrangement mode can reduce the phase margin of the voltage regulator, and the output voltage of the voltage regulator is easy to have ringing phenomenon.

In contrast, the error amplifying circuit 200 of fig. 2 sets the current mirror (the eleventh transistor M11 and the twelfth transistor M12) at the second stage amplifier 220. The contribution of the second stage amplifier 220 to the input-referred noise is much smaller than the first stage amplifier 210, and thus the transistors in the second stage amplifier 220 do not add noise even if they are designed to have a relatively small size. In this way, the size of the current mirror is reduced to reduce parasitic components, which is helpful to improve the phase margin of the voltage regulator 100A of fig. 1A and the voltage regulator 100B of fig. 1B to suppress ringing.

Fig. 4 is a frequency response curve of a prior art voltage regulator, which corresponds to a voltage regulator in which a current mirror is provided in a first stage amplifier. Fig. 5 is a frequency response curve of the voltage regulator 100A according to an embodiment of the disclosure. The phase margin is defined as the difference between the phase of the output signal and-180 deg. at a gain of 0 dB. The phase margin of the embodiment of fig. 4 is about 230 deg., and the phase margin of the embodiment of fig. 5 is about 260 deg., so the phase margin of the voltage regulator 100A is improved by about 30 deg. compared to the prior art. The voltage regulator 100B of fig. 1B is similar to the voltage regulator 100A, and has the advantage of a wide phase margin, and for brevity, the description thereof will not be repeated here.

Fig. 6 is a schematic diagram of an error amplifying circuit 600 according to an embodiment of the disclosure. The error amplifying circuit 600 may be used to implement the error amplifying circuit 110 of fig. 1A and 1B, and includes a first stage amplifier 210, a second stage amplifier 220, and a buffer circuit 630. The circuit structure and operation of the first stage amplifier 210 and the second stage amplifier 220 are similar to those described above in conjunction with fig. 2-3, and for brevity, the description is not repeated here.

The buffer circuit 630 is coupled to the gain node Ng and is used for adjusting the error amplified signal Vea to generate an adjusted error amplified signal Vea'. In one embodiment, the adjustment may be that the buffer circuit 630 applies a unit gain or higher to the error amplified signal Vea. In this case, the adjusted error amplified signal Vea' is provided as an output control signal Vad to the output stage circuit 120 of fig. 1A or 1B. Structurally, the buffer circuit 630 includes a fifteenth transistor M15, a fifth current source Se, and a sixth current source Sf. The fifth current source Se is coupled between the first power source terminal PD1 and a driving node Nd for providing the adjusted error amplified signal Vea'. The sixth current source Sf is coupled to the second power source PD2, the fifteenth transistor M15 is coupled between the driving node Nd and the sixth current source Sf, and the control terminal of the fifteenth transistor M15 is configured to receive the error amplifying signal Vea. In some embodiments, the fifteenth transistor M15 may be implemented by a P-type MOS field effect transistor.

It should be noted that the buffer circuit 630 further shifts the poles in the frequency response curves of the voltage regulators 100A and 100B toward high frequency, thereby helping to further improve the phase margin of the voltage regulators 100A and 100B.

Fig. 7 is a schematic diagram of an error amplifying circuit 700 according to an embodiment of the disclosure. The error amplification circuit 700 may be used to implement the error amplification circuit 110 of fig. 1A and 1B, and includes a first stage amplifier 710, a second stage amplifier 720, and a buffer circuit 730. The first stage amplifier 710 is similar to the first stage amplifier 210 of fig. 2, except that the first current source Sa of the first stage amplifier 710 includes a sixteenth transistor M16, and the sixteenth transistor M16 is coupled between the first power source terminal PD1 and the fully differential amplifying circuit 212. The second stage amplifier 720 is similar to the second stage amplifier 220 of fig. 2, except that the fourth current source Sd of the second stage amplifier 720 includes a seventeenth transistor M17, and the seventeenth transistor M17 is coupled between the differential-to-single-ended amplifying circuit 222 and the second power supply terminal PD2. The buffer circuit 730 is similar to the buffer circuit 630 of fig. 6, except that the fifth current source Se and the sixth current source Sf of the buffer circuit 730 include an eighteenth transistor M18 and a nineteenth transistor M19, respectively. The eighteenth transistor M18 is coupled between the first power terminal PD1 and the driving node Nd, and the nineteenth transistor M19 is coupled between the fifteenth transistor M15 and the second power terminal PD2. In one embodiment, the control terminal of the sixteenth transistor M16 and the control terminal of the eighteenth transistor M18 are configured to receive the same first bias signal Vb1, and the control terminal of the seventeenth transistor M17 and the control terminal of the nineteenth transistor M19 are configured to receive the same second bias signal Vb2.

In some embodiments, the sixteenth transistor M16 and the eighteenth transistor M18 may be implemented by P-type MOS field effect transistors, and the seventeenth transistor M17 and the nineteenth transistor M19 may be implemented by N-type MOS field effect transistors.

Fig. 8 is a functional block diagram of a signal amplifying circuit 800 according to an embodiment of the disclosure. The signal amplifying circuit 800 is a general-purpose signal amplifying circuit, and includes an error amplifying circuit 110 and an output stage circuit 120. The error amplifying circuit 110 is configured to amplify a difference between the first input signal Vi1 and the second input signal Vi2 to generate an output control signal Vad. The output stage circuit 120 is coupled between the first power source terminal PD1 and the output node Nout, and is configured to convert the input power source VDD of the first power source terminal PD1 according to the output control signal Vad to provide the output signal Vout at the output node Nout. The output stage circuit 120 includes a switch Mp coupled between the first power source terminal PD1 and the output node Nout, and a control terminal thereof for receiving the output control signal Vad. The error amplification circuit 110 of fig. 8 may be implemented by the error amplification circuit 200, 600, or 700 of fig. 2, 6, or 7. In this case, the first input Ia1 and the second input Ia2 of the first stage amplifier (e.g., the first stage amplifier 210 or 710) are used to receive the first input signal Vi1 and the second input signal Vi2, respectively. The remaining corresponding components, connections and operations of the error amplification circuit 110 of fig. 8 are similar to those described above in conjunction with fig. 2, 6 or 7, and are not repeated here for brevity.

Certain terms are used throughout the description and claims to refer to particular components. However, it will be understood by those of ordinary skill in the art that like components may be referred to by different names. The description and claims do not identify differences in names, but rather are used as references to differences in functions of the components. In the description and claims, the terms "comprise" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. In addition, "coupled" herein includes any direct or indirect connection. Accordingly, if a first element couples to a second element, that connection may be through an electrical or wireless transmission, an optical transmission, etc., directly to the second element, or through other elements or connections indirectly to the second element.

In addition, any singular reference is intended to include the plural reference unless the context clearly dictates otherwise.

The foregoing is only illustrative of the preferred embodiments of the present disclosure, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

[ symbolic description ]

100A, 100B: voltage regulator

110: error amplifying circuit

120: output stage circuit

130A, 130B: output feedback path

200. 600, 700: error amplifying circuit

210. 710: first stage amplifier

212: full differential amplifying circuit

214: common mode feedback circuit

220. 720: second stage amplifier

222: differential to single-ended amplifying circuit

310: first amplifying circuit

320: second amplifying circuit

330: current-to-voltage conversion circuit

630. 730: buffer circuit

800: signal amplifying circuit

Ia1, ib1: a first input end

Ia2, ib2: a second input terminal

Sa: a first current source

Sb: a second current source

Sc: third current source

Sd: fourth current source

Se: fifth current source

Sf: sixth current source

M1: first transistor

M2: second transistor

M3: third transistor

M4: fourth transistor

M5: fifth transistor

M6: sixth transistor

M7: seventh transistor

M8: eighth transistor

M9: ninth transistor

M10: tenth transistor

M11: eleventh transistor

M12: twelfth transistor

M13: thirteenth transistor

M14: fourteenth transistor

M15: fifteenth transistor

M16: sixteenth transistor

M17: seventeenth transistor

M18: eighteenth transistor

M19: nineteenth transistor

Vref: reference signal

Vofb: output feedback signal

Vad: output control signal

Vb1: first bias signal

Vb2: second bias signal

Vout: output signal

VDD: input power supply

Vdf1: first differential signal

Vdf2: second differential signal

Vea: error amplified signal

Vea': post-adjustment error amplified signal

Vcmfb: common mode feedback signal

Vccm: common mode control signal

Vi1: first input signal

Vi2: a second input signal

Io1: first output current

Io2: second output current

NFP: negative feedback path

Mp: switch

Nout: output node

Ndf1: first differential node

Ndf2: second differential node

Nnp: inverting node

Ng: gain node

N1: first node

N2: second node

And N3: third node

N4: fourth node

PD1: a first power supply terminal

PD2: a second power supply terminal

R1 and R2: voltage dividing resistor

Claims (10)

1. A voltage regulator, comprising:

an error amplifying circuit, the error amplifying circuit comprising:

a first stage amplifier for amplifying a difference between the output feedback signal and the reference signal to generate a first differential signal and a second differential signal; and

a second stage amplifier for amplifying a difference between the first differential signal and the second differential signal to generate an output control signal;

the output stage circuit is coupled to the first power supply end and comprises a switch, wherein the switch is used for generating an output signal at an output node according to the output control signal; and

and the output feedback path is coupled to the output node and the error amplifying circuit and is used for generating the output feedback signal according to the output signal.

2. The voltage regulator of claim 1, wherein the first stage amplifier comprises:

the first current source is coupled to the first power end;

the full differential amplifying circuit is coupled between the first current source and the second power end and is used for amplifying the difference value between the output feedback signal and the reference signal to output the first differential signal and the second differential signal; and

and the common mode feedback circuit is used for providing a common mode feedback signal to the full differential amplifying circuit according to the first differential signal and the second differential signal so as to stabilize the direct current common mode voltage of the first differential signal and the second differential signal.

3. The voltage regulator of claim 2, wherein the fully differential amplifying circuit comprises:

a first transistor coupled between the first current source and a first differential node for generating the first differential signal at the first differential node under control of the output feedback signal;

a second transistor coupled between the first current source and a second differential node for generating the second differential signal at the second differential node under control of the reference signal;

a third transistor coupled between the first differential node and the second power supply terminal and controlled by the common mode feedback signal; and

and a fourth transistor coupled between the second differential node and the second power supply terminal and controlled by the common mode feedback signal.

4. The voltage regulator of claim 2, wherein the common mode feedback circuit comprises:

a first amplifying circuit for amplifying the difference between the first differential signal and the common mode control signal to generate a first output current; and

a second amplifying circuit for amplifying the difference between the second differential signal and the common mode control signal to generate a second output current,

the common mode feedback circuit is used for generating the common mode feedback signal according to the first output current and the second output current.

5. The voltage regulator of claim 4, wherein the first amplifying circuit comprises:

the second current source is coupled to the first power end;

a fifth transistor coupled between the second current source and the first node and controlled by the first differential signal;

a sixth transistor coupled between the second current source and a second node for providing the first output current to the second node under control of the common mode control signal;

a seventh transistor, wherein a first terminal and a control terminal of the seventh transistor are coupled to the first node and the third node, and a second terminal of the seventh transistor is coupled to the second power terminal; and

an eighth transistor, wherein a first terminal and a control terminal of the eighth transistor are coupled to the second node and the fourth node, and a second terminal of the eighth transistor is coupled to the second power terminal,

wherein the second amplifying circuit includes:

the third current source is coupled to the first power end;

the seventh transistor;

the eighth transistor;

a ninth transistor coupled between the third current source and the fourth node for providing the second output current to the fourth node under control of the common mode control signal; and

and a tenth transistor coupled between the third current source and the third node and controlled by the second differential signal.

6. The voltage regulator of claim 2, wherein the second stage amplifier comprises:

the differential to single-ended amplifying circuit is coupled to the first power end and is used for amplifying the difference value of the first differential signal and the second differential signal to output an error amplified signal, wherein the voltage regulator generates the output control signal according to the error amplified signal; and

and a fourth current source coupled between the differential-to-single-ended amplifying circuit and the second power supply terminal.

7. The voltage regulator of claim 6, wherein the differential-to-single ended amplifying circuit comprises:

an eleventh transistor coupled between the first power supply terminal and the inverting node;

a twelfth transistor coupled between the first power supply terminal and a gain node for providing the error amplified signal, the control terminal of the eleventh transistor and the control terminal of the twelfth transistor being coupled to the inverting node;

a thirteenth transistor coupled between the inverting node and the fourth current source and controlled by the second differential signal; and

a fourteenth transistor coupled between the gain node and the fourth current source and controlled by the first differential signal.

8. The voltage regulator of claim 1, wherein the output feedback path comprises:

a first voltage dividing resistor for receiving the output signal; and

the second voltage dividing resistor is coupled in series with the first voltage dividing resistor, wherein the first voltage dividing resistor and the second voltage dividing resistor are used for dividing the output signal to generate the output feedback signal.

9. The voltage regulator of claim 1, wherein the output feedback path is configured to pass the output signal as the output feedback signal to the error amplification circuit.

10. A signal amplifying circuit, comprising:

an error amplifying circuit comprising:

a first stage amplifier for amplifying a difference between the first input signal and the second input signal to generate a first differential signal and a second differential signal; and

a second stage amplifier for amplifying a difference between the first differential signal and the second differential signal to generate an output control signal; and

the output stage circuit is coupled to the first power supply terminal and comprises a switch, wherein the switch is used for generating an output signal at an output node according to the output control signal.