CN117060924A - Correction system for eliminating influence of phase noise and analog-to-digital conversion device comprising same - Google Patents

Abstract

The present disclosure provides a correction system for eliminating the influence of phase noise and an analog-to-digital conversion device including the correction system. The correction system includes a jitter extraction analog-to-digital converter (ADC), a correction value generation circuit and a first operation circuit. The jitter extraction ADC is used for sampling a clock signal to be sampled according to the operation clock signal so as to generate a first quantized output. The correction value generation circuit is used for receiving the first quantized output and the second quantized output of the ADC to be corrected to generate a correction value. The operation clock signal is used for driving the ADC sampling to be corrected, and the correction value is related to the phase noise of the operation clock signal. The first operation circuit is coupled to the correction value generation circuit and is used for subtracting the correction value from the second quantized output to generate a third quantized output. The correction system and the analog-to-digital conversion device can improve or eliminate sampling errors caused by phase noise of the clock signal in the quantized output.

Description

Correction system to eliminate the effects of phase noise and analog to digital conversion including the same device

Technical field

This disclosure document relates to a calibration technology for an analog-to-digital converter (ADC), and in particular, to a calibration system that eliminates the influence of phase noise and an analog-to-digital conversion device including the calibration system.

Background technique

Phase locked loops are often used in various high-speed circuits. For example, a phase locked loop can be used for frequency synthesis to produce an output signal with a frequency that is an integer multiple of the frequency of the input signal. The clock signal generated by the phase-locked loop can be used to drive an analog-to-digital converter (ADC) for sampling. However, the clock signal generated by the phase-locked loop usually has a jitter phenomenon and is difficult to meet the stability of the high-speed ADC for the clock signal. Require. On the other hand, clock generators that produce low-jitter signals, such as crystal oscillators, are generally more expensive.

Contents of the invention

This disclosure document provides a correction system, which includes a jitter acquisition analog-to-digital converter (ADC), a correction value generation circuit and a first operation circuit. The jitter acquisition ADC is used to sample the clock signal to be sampled according to the operating clock signal to generate a first quantized output. The correction value generation circuit is configured to receive the first quantization output and the second quantization output of the ADC to be corrected to generate a correction value. The operating clock signal is used to drive the ADC samples to be corrected, and the correction value is related to the phase noise of the operating clock signal. The first operation circuit is coupled to the correction value generating circuit and is used for subtracting the correction value from the second quantized output to generate a third quantized output.

In some embodiments of the above correction system, the correction value generation circuit includes an error acquisition circuit, a differential circuit and a second operation circuit. The error acquisition circuit is used for receiving the first quantization output, and for obtaining the sampling time error of the ADC to be corrected from the first quantization output, and the sampling time error is related to the phase noise. The differentiating circuit is configured to receive the second quantized output and calculate the slope of the second quantized output. The second operation circuit is used to multiply the sampling time error by the slope to generate a correction value.

In some embodiments of the above correction system, the error acquisition circuit obtains the product of the sampling time error and a constant from the first quantized output, and then obtains the sampling time error, and the constant is negatively related to the period of the operating clock signal.

In some embodiments of the above correction system, the period of the operating clock signal is M times the period of the clock signal to be sampled, M is a positive number and the constant is positively related to M.

In some embodiments of the above correction system, the correction system further includes a signal processing circuit. The signal processing circuit is used to perform one or more of the following on the clock signal to be sampled: amplification, frequency division and slope adjustment before the clock pulse signal to be sampled is input to the jitter acquisition ADC.

In some embodiments of the above calibration system, the clock signal to be sampled is used to input the clock generator, and the operating clock signal is generated by the clock generator based on the clock signal to be sampled.

In some embodiments of the above correction system, the clock signal to be sampled outputted by the signal processing circuit has a ramp waveform or a sawtooth waveform.

This disclosure document provides a correction system, which includes a jitter acquisition ADC, a correction value generation circuit and a first operation circuit. The jitter acquisition ADC is used to sample the clock signal to be sampled according to the operating clock signal to generate a first quantized output. The correction value generation circuit is configured to receive the first quantization output and the second quantization output of the ADC to be corrected to generate a correction value. The clock signal to be sampled is used to drive the ADC to be corrected for sampling, and the correction value is related to the phase noise of the clock signal to be sampled.

In some embodiments of the above correction system, the correction value generating circuit includes an error acquisition circuit, a differential circuit and a second operation circuit. The error acquisition circuit is used for receiving the first quantization output, and for obtaining the sampling time error of the ADC to be corrected from the first quantization output, and the sampling time error is related to the phase noise. The differentiating circuit is configured to receive the second quantized output and calculate the slope of the second quantized output. The second operation circuit is used to multiply the sampling time error by the slope to generate a correction value.

In some embodiments of the above calibration system, the error acquisition circuit obtains the product of the sampling time error from the first quantized output and a constant, and then obtains the sampling time error, and the constant is negatively related to the period of the operating clock signal.

In some embodiments of the above correction system, the period of the operating clock signal is 1/M times the period of the clock signal to be sampled, M is a positive number and the constant is negatively related to M.

In some embodiments of the above correction system, the correction system further includes a signal processing circuit. The signal processing circuit is used to perform one or more of the following on the clock signal to be sampled: amplification, frequency division and slope adjustment before the clock pulse signal to be sampled is input to the jitter acquisition ADC.

In some embodiments of the above calibration system, the operating clock signal is used to input the clock generator, and the clock signal to be sampled is generated by the clock generator based on the operating clock signal.

In some embodiments of the above correction system, the clock signal to be sampled outputted by the signal processing circuit has a ramp waveform or a sawtooth waveform.

This disclosure document provides an analog-to-digital conversion device, which includes a clock generator, at least one ADC to be corrected, and a correction system. Each ADC to be corrected is used to generate a second quantized output, and one of the at least one ADC to be corrected samples according to the output of the clock generator to generate the second quantized output. The correction system is configured to receive the input of the clock generator, the output of the clock generator and the second quantized output of at least one of the ADCs to be corrected to generate a correction value, and to correct each ADC to be corrected according to the correction value. The second quantized output is used to produce a third quantized output. The correction value is related to the phase noise at the output of the clock generator.

In some embodiments of the above analog-to-digital conversion device, at least one ADC to be corrected includes a plurality of ADCs to be corrected, and each ADC to be corrected is sampled based on the output of the clock generator.

In some embodiments of the above analog-to-digital conversion device, at least one ADC to be corrected includes a plurality of ADCs to be corrected, and the plurality of ADCs to be corrected are sampled according to a plurality of time-interleaved clock signals. The plurality of time-interleaved clock signals include an output of a clock generator, and the phase of the output of the clock generator leads the phase of the remaining time-interleaved clock signals in the plurality of time-interleaved clock signals.

In some embodiments of the above analog-to-digital conversion device, at least one ADC to be corrected includes a plurality of ADCs to be corrected. The correction system includes a jitter acquisition ADC, a correction value generation circuit and a plurality of first operation circuits. The jitter acquisition ADC is used for sampling the input of the clock generator according to the output of the clock generator to generate a first quantized output. The correction value generating circuit is configured to receive a first quantized output and a second quantized output of one of at least one ADC to be corrected to generate a correction value. A plurality of first operation circuits are coupled to the correction value generating circuit, and are respectively coupled to a plurality of ADCs to be corrected. Each first operation circuit is used to subtract the correction value from the second quantization output of a corresponding one of the plurality of ADCs to be corrected to generate a third quantization output.

In some embodiments of the above analog-to-digital conversion device, at least one ADC to be corrected includes a plurality of ADCs to be corrected. The correction system includes a jitter acquisition ADC, a correction value generation circuit and a plurality of first operation circuits. The jitter acquisition ADC is used for sampling the output of the clock generator according to the input of the clock generator to generate a first quantized output. The correction value generating circuit is configured to receive a first quantized output and a second quantized output of one of at least one ADC to be corrected to generate a correction value. A plurality of first operation circuits are coupled to the correction value generating circuit, and are respectively coupled to a plurality of ADCs to be corrected. Each first operation circuit is used to subtract the correction value from the second quantization output of a corresponding one of the plurality of ADCs to be corrected to generate a third quantization output.

One of the advantages of the above-mentioned correction system and analog-to-digital conversion device is that it can improve or eliminate the sampling error caused by the phase noise of the clock signal in the quantized output.

Description of the drawings

Figure 1 is a simplified functional block diagram of an analog-to-digital conversion device according to an embodiment of this disclosure document;

Figure 2 is a simplified functional block diagram of a correction value generating circuit according to an embodiment of this disclosure document;

Figure 3 is a simplified functional block diagram of an analog-to-digital conversion device according to an embodiment of this disclosure document;

FIG. 4 is a simplified functional block diagram of an analog-to-digital conversion device according to an embodiment of this disclosure document;

FIG. 5 is a simplified functional block diagram of an analog-to-digital conversion device according to an embodiment of this disclosure document;

FIG. 6 is a simplified functional block diagram of an analog-to-digital conversion device according to an embodiment of this disclosure document;

FIG. 7 is a simplified functional block diagram of an analog-to-digital conversion device according to an embodiment of this disclosure document;

Figure 8 is a simplified functional block diagram of an analog-to-digital conversion device according to an embodiment of this disclosure document;

Figure 9 is a simplified functional block diagram of an analog-to-digital conversion device according to an embodiment of this disclosure document;

FIG. 10 is a schematic diagram of a spectrum of quantized output according to an embodiment of the present disclosure.

【Symbol Description】

100,300,400,500,600,700,800,900:Analog to digital conversion device

110,310,410,510,610,710,810,910: Clock generator

120,320,420,520,620,720,820,920: Analog to digital converter (ADC) to be calibrated

130,330,430,530,630,730,830,930: Calibration system

132,332,432,532,632,732,832,932: Jitter capture ADC

134,334,434,534,634,734,834,934: Correction value generation circuit

136,336,636,736: Arithmetic circuit

436_0～436_n-1: Operation circuit

536_0～536_n-1: Operation circuit

836_0～836_n-1: Operation circuit

936_0～936_n-1: Operation circuit

200: Correction value generation circuit

210: Error capture circuit

220: Differential circuit

230: Arithmetic circuit

dX(n)/dt: the slope of the correct sampling result

t_jn: Sampling time error

338,738:Signal processing circuit

In_0～In_n-1: input signal

Qtb_0～Qtb_n-1,Qjit,Qout_0～Qout_n-1: quantized output

CKin,CKs_0～CKs_n-1: clock signal

Vc: Correction value

10,20:Spectrum

Detailed ways

The embodiments of this disclosure document will be described below with reference to relevant drawings. In the drawings, the same reference numerals represent the same or similar elements or method flows.

FIG. 1 is a simplified functional block diagram of an analog-to-digital conversion device 100 according to an embodiment of the present disclosure. The analog-to-digital conversion device 100 includes a clock generator 110 , an analog-to-digital converter (ADC) 120 to be calibrated, and a calibration system 130 . The clock generator 110 is configured to receive the clock signal CKin to generate the clock signal CKs_0. In some embodiments, the frequency of the clock signal CKin is M times the frequency of the clock signal CKs_0, that is, the period of the clock signal CKs_0 is M times the period of the clock signal CKin, where M is a positive number (eg 4/19). In some embodiments, clock generator 110 includes a phase locked loop. The ADC 120 to be calibrated is coupled to the clock generator 110 and the calibration system 130 . The ADC 120 to be corrected is used to sample the input signal In_0 according to the clock signal CKs_0 to output the quantized output Qtb_0 to be corrected to the correction system 130 . The correction system 130 is used to correct the quantized output Qtb_0 to improve or eliminate the sampling error in the quantized output Qtb_0 caused by the phase noise of the clock signal CKs_0, thereby generating the quantized output Qout_0. Phase noise can be understood as the signal jitter phenomenon of the clock signal CKs_0 in the time domain. In some embodiments, the sampling error is the voltage difference between the correct sampling result of the ADC 120 to be corrected and the actual sampling result.

In some embodiments, the quantized output Qtb_0 of the ADC 120 to be corrected can be represented by the following "Formula 1", and "Formula 1" can be rewritten as the following "Formula 2" based on the sum-angle formula. In "Formula 1" and "Formula 2", the symbol "Fin_0" represents the frequency of the input signal In_0; the symbol "n" represents the nth sampling, where n is a positive integer; the symbol "Ts" represents the period of the clock signal CKs_0 ; The symbol “t_jn” represents the sampling time error of the ADC 120 to be corrected caused by the phase noise of the clock signal CKs_0.

Q_tb0＝sin[2×π×Fin_0×(n×Ts+t_jn)] 《Formula 1》

Q_tb0＝sin[2×π×Fin_0×(n×Ts)]×cos(2×π×Fin_0×t_jn)+cos[2×π×Fin_0×(n×Ts)]×sin(2×π×Fin_0 ×t_jn) 《Formula 2》

In the following paragraphs, for the sake of simplicity, the correct sampling result of the ADC 120 to be corrected in the formula (that is, sin[2×π×Fin_0×(n×Ts)] in "Formula 2") will be represented by the symbol "X( n)" means. In some embodiments, the value of the sampling time error t_jn caused by phase noise is usually very small, for example, approximately 0, so "Formula 2" can be further rewritten as the following "Formula 3". It is worth noting that for high-speed ADCs, the signals they sample usually have frequencies of megahertz (MHz) or gigahertz (GHz) levels, so even a small sampling time error t_jn may cause the ADC to produce very different outputs. It can be seen from "Formula 3" that the quantized output Qtb_0 is essentially the sum of the following two: (1) the correct sampling result (symbol "X(n)") and (2) the slope of the correct sampling result (symbol "dX(n)" /dt”) and the product of the sampling time error t_jn.

In some embodiments, the correction system 130 includes a jitter acquisition ADC 132, a correction value generation circuit 134, and an operation circuit 136. The jitter acquisition ADC 132 is used to sample the clock signal CKin according to the clock signal CKs_0 to generate the quantized output Qjit, that is, the jitter acquisition ADC 132 is used to sample the input of the clock generator 110 according to the output of the clock generator 110 .

The correction value generation circuit 134 is configured to receive the quantization output Qjit from the jitter acquisition ADC 132 and receive the quantization output Qtb_0 from the ADC 120 to be corrected. The correction value generation circuit 134 is also used to generate the correction value Vc according to the quantization outputs Qjit and Qtb_0. In one embodiment, the correction value Vc is related to the phase noise of the clock signal CKs_0, that is, related to the sampling time error t_jn in the aforementioned "Equation 3". The operation circuit 136 is coupled to the ADC to be corrected 120 and the correction value generation circuit 134, and is used to subtract the correction value Vc from the quantized output Qtb_0 to correct the sampling error, thereby obtaining a quantized output Qout_0 that is essentially the correct sampling result of the ADC 120 to be corrected. .

Next, the calculation method of the correction voltage Vc will be described. For ease of understanding, M is set to a positive integer in the embodiments in the following paragraphs, but this disclosure document is not limited thereto. In some embodiments, the quantized output Qjit of the jitter acquisition ADC 132 can be represented by the following "Formula 4", and "Formula 4" can be rewritten as the following "Formula 5" based on the sum-angle formula. In "Formula 4" and "Formula 5", the symbol "Fs" represents the frequency of the clock signal CKs_0, and "M×Fs" is the frequency of the clock signal CKin.

Q_jit＝sin[2×π×M×Fs×(n×Ts+t_jn)]《Formula 4》

In the embodiment where M is a positive integer, "Formula 5" can be rewritten as the following "Formula 6". It can be seen from "Formula 6" that the quantized output Qjit is essentially a constant (for example, 0) plus a constant multiple of the sampling time error t_jn, because the period and M of the clock signal CKs_0 are known parameters.

FIG. 2 is a simplified functional block diagram of a correction value generating circuit 200 according to an embodiment of the present disclosure. The correction value generation circuit 200 may be used to implement the correction value generation circuit 134 of FIG. 1 . The correction value generating circuit 200 includes an error acquisition circuit 210, a differential circuit 220 and an arithmetic circuit 230. The error acquisition circuit 210 is used to receive the quantization output Qjit from the jitter acquisition ADC 132, and to calculate the sampling time error t_jn _- from the quantization output Qjit according to the period of the clock signal CKs_0. In some embodiments, the error acquisition circuit 210 obtains the product of the sampling time error t_jn and a constant from the quantized output Qjit, thereby obtaining the sampling time error t_jn. It can be seen from "Formula 6" that this constant is 2×π×M×(1/Ts), that is, this constant is negatively related to the period of the clock signal CKs_0 and positively related to M.

The differentiating circuit 220 is used to receive the quantized output Qtb_0 from the ADC 120 to be corrected, and calculate the slope of the quantized output Qtb_0. In some embodiments, the differential circuit 220 calculates the slope based on the n-1th and n+1th sampling results in the quantized output Qtb_0, but this disclosure document is not limited to this. The differential circuit 220 can further use the nth -2nd and n+2nd sampling results, or further use the n-3rd and n+3th sampling results. In a short time interval, the impact of the jitter of the clock signal CKs_0 can be ignored, so the n-1th and n+1th sampling results can be regarded as correct sampling results (hereinafter respectively represented by the symbol "X(n- 1)" and "X(n+1)" represent). Therefore, the slope of the quantized output Qtb_0 calculated by the differential circuit 220 is essentially the slope of the correct sampling result in "Formula 3". The differential circuit 220 can calculate the slope through the following "Formula 7".

The operation circuit 230 is used to multiply the sampling time error t_jn by the slope of the correct sampling result to obtain the correction value Vc, that is, Vc=(dX(n)/dt)×t_jn. Then, the operation circuit 230 may provide the correction value Vc to the operation circuit 136 of FIG. 1 .

FIG. 3 is a simplified functional block diagram of an analog-to-digital conversion device 300 according to an embodiment of the present disclosure. The analog-to-digital conversion device 300 includes a clock generator 310, an ADC to be corrected 320, and a correction system 330. The analog-to-digital conversion device 300 is similar to the analog-to-digital conversion device 100 of FIG. 1 , and for the sake of simplicity, only the differences will be described below.

The correction system 330 includes a jitter acquisition ADC 332, a correction value generation circuit 334, an operation circuit 336 and a signal processing circuit 338. The signal processing circuit 338 is coupled between the input terminal of the clock generator 310 and the input terminal of the jitter acquisition ADC 332 . The signal processing circuit 338 is used to receive the clock signal CKin, and to perform one or more of the following signal processing on the clock signal CKin before the clock signal CKin is input into the jitter capture ADC 332: amplification, frequency division, and slope adjustment. In some embodiments, the clock signal CKin processed by the signal processing circuit 338 has a ramp waveform or a sawtooth waveform. The signal processing circuit 338 controls the value of M and improves the signal-to-noise ratio of the clock signal CKin by controlling the waveform and frequency of the clock signal CKin to stabilize the values of multiple constants in "Equation 6" and improve the accuracy of the correction system 330. The accuracy of the obtained sampling time error t_jn.

The jitter acquisition ADC 332 is used to sample the clock signal CKin output by the signal processing circuit 338 according to the clock signal CKs_0 to generate and output the quantized output Qjit to the correction value generation circuit 334 . The components, connection relationships, and operations of the correction value generation circuit 334 and the operation circuit 336 are similar to the correction value generation circuit 134 and the operation circuit 136 of FIG. 1 respectively, and will not be repeated here for the sake of simplicity.

FIG. 4 is a simplified functional block diagram of an analog-to-digital conversion device 400 according to an embodiment of the present disclosure. The analog-to-digital conversion device 400 includes a clock generator 410, a plurality of ADCs 420_0˜420_n-1 to be corrected, and a correction system 430. The clock generator 410 is similar to the clock generator 110 in FIG. 1 , and for the sake of simplicity, the details are not repeated here. The ADCs 420_0 to 420_n-1 to be calibrated are respectively used to receive the input signals In_0 to In_n-1, but this disclosure document is not limited to this. The ADCs 420_0 to 420_n-1 to be calibrated do not need to receive different input signals. The ADCs 420_0 to 420_n-1 to be corrected are used to sample the input signals In_0 to In_n-1 according to the clock signal CKs_0 to generate quantized outputs Qtb_0 to Qtb_n-1 respectively. In other words, each of the ADCs 420_0˜420_n-1 to be corrected samples according to the clock signal CKs_0.

The correction system 430 is used to correct the quantized outputs Qout_0˜Qout_n-1 to improve or eliminate the sampling errors in the quantized outputs Qout_0˜Qout_n-1 caused by the phase noise of the clock signal CKs_0. The correction system 430 includes a jitter acquisition ADC 432, a correction value generation circuit 434, and a plurality of operation circuits 436_0˜436_n-1. The operation circuits 436_0˜436_n-1 are used to receive the quantized outputs Qtb_0˜Qtb_n-1 respectively, and receive the correction value Vc from the correction value generation circuit 434. The operation circuits 436_0˜436_n-1 are also used to subtract the correction value Vc from each of the quantized outputs Qtb_0˜Qtb_n-1 to generate the quantized outputs Qout_0˜Qout_n-1 respectively. The quantized outputs Qout_0~Qout_n-1 are essentially the correct sampling results of the ADCs 420_0~420_n-1 to be corrected respectively.

The components, connection relationships and operations of the jitter acquisition ADC 432 and the correction value generation circuit 434 are respectively similar to the jitter acquisition ADC 132 and the correction value generation circuit 134 in FIG. 1 , and will not be repeated here for the sake of brevity. It is worth mentioning that the correction value generation circuit 434 can use any one of the quantized outputs Qtb_0˜Qtb_n-1 to calculate the correction value Vc.

FIG. 5 is a simplified functional block diagram of an analog-to-digital conversion device 500 according to an embodiment of the present disclosure. The analog-to-digital conversion device 500 includes a clock generator 510, a plurality of ADCs 520_0˜520_n-1 to be corrected, and a correction system 530. The correction system 530 includes a jitter acquisition ADC 532, a correction value generation circuit 534 and a plurality of operation circuits 536_0˜536_n-1. The analog-to-digital conversion device 500 is similar to the analog-to-digital conversion device 400 of FIG. 4 , so only the differences will be described below.

The ADCs 520_0 to 520_n-1 to be corrected are used to respectively sample the input signal In_0 according to a plurality of clock signals CKs_0 to CKs_n-1 to generate quantized outputs Qtb_0 to Qtb_n-1 respectively. The clock signals CKs_0˜CKs_n-1 are time-interleaved clock signals. In some embodiments, the analog-to-digital conversion device 500 may be used to implement a time-interleaved ADC, and may include a multiplexer (not shown in FIG. 5 ) to generate a digital output signal based on the quantized outputs Qout_0˜Qout_n-1. The ADC to be corrected 520_0 and the jitter acquisition ADC 532 sample according to the clock signal CKs_0. In some embodiments, the phase of the clock signal CKs_0 leads the phases of the remaining time-interleaved clock signals CKs_1˜CKs_n-1.

In some embodiments, the correction system 430 of FIG. 4 or the correction system 530 of FIG. 5 further includes a signal processing circuit (not shown), and the clock signal CKin is input to the jitter capture ADC 432 of FIG. 4 or the jitter capture ADC of FIG. 5 Before obtaining the ADC 532, the signal processing circuit is used to perform one or more of the following signal processing on the clock signal CKin: amplification, frequency division and slope adjustment. In addition, the clock signal CKs_0 provided by the signal processing circuit to the jitter acquisition ADC 432 of FIG. 4 or the jitter acquisition ADC 532 of FIG. 5 may have a ramp waveform or a sawtooth waveform.

FIG. 6 is a simplified functional block diagram of an analog-to-digital conversion device 600 according to an embodiment of the present disclosure. The analog-to-digital conversion device 600 includes a clock generator 610, an ADC to be corrected 620, and a correction system 630. The clock generator 610 and the ADC to be corrected 620 are respectively similar to the clock generator 110 and the ADC to be corrected 120 in FIG. 1 , and for the sake of simplicity, the details are not repeated here. The correction system 630 is used to correct the quantized output Qtb_0 to improve or eliminate the sampling error in the quantized output Qtb_0 caused by the phase noise of the clock signal CKs_0, thereby generating the quantized output Qout_0.

The correction system 630 includes a jitter acquisition ADC 632, a correction value generation circuit 634 and an operation circuit 636. The jitter acquisition ADC 632 is used to sample the clock signal CKs_0 according to the clock signal CKin to generate the quantized output Qjit, that is, the jitter acquisition ADC 632 is used to sample the output of the clock generator 610 according to the input of the clock generator 610 .

The correction value generation circuit 634 is configured to receive the quantization output Qjit from the jitter acquisition ADC 632 and receive the quantization output Qtb_0 from the ADC 620 to be corrected. The correction value generation circuit 634 is also used to generate the correction value Vc according to the quantization outputs Qjit and Qtb_0. In one embodiment, the correction value Vc is related to the phase noise of the clock signal CKs_0, that is, related to the sampling error time t_jn of the aforementioned "Formula 3". The operation circuit 636 is coupled to the ADC to be corrected 620 and the correction value generation circuit 634, and is used to subtract the correction value Vc from the quantized output Qtb_0 to correct the sampling error, thereby obtaining a quantized output Qout_0 that is essentially the correct sampling result of the ADC 620 to be corrected. .

Next, the calculation method of the correction voltage Vc will be described. In some embodiments, the quantized output Qjit of the jitter acquisition ADC 632 can be represented by the following "Formula 8", and "Formula 8" can be rewritten as the following "Formula 9" based on the sum-angle formula. In "Formula 8" and "Formula 9", the symbol "Tcin" represents the period of the clock signal CKin, and "(1/M)×Tcin" is the period of the clock signal CKs_0.

Q_jit＝sin[2×π×Fs×(n×Tcin+t_jn)]《Formula 8》

In the embodiment where 1/M is a positive integer, "Formula 9" can be rewritten as the following "Formula 10". It can be seen from "Formula 10" that the quantized output Qjit is essentially a constant (for example, 0) plus a constant multiple of the sampling time error t_jn, because the period and M of the clock signal CKin are known parameters.

In some embodiments, the correction value generation circuit 634 may be implemented using the correction value generation circuit 200 of FIG. 2 . Please refer to FIG. 2 and FIG. 6 at the same time. In this case, the error acquisition circuit 210 is used to receive the quantization output Qjit from the jitter acquisition ADC 632, and is used to calculate the sampling time error from the quantization output Qjit according to the period of the clock signal CKin. t_jn. In some embodiments, the error acquisition circuit 210 obtains the product of the sampling time error t_jn and a constant from the quantized output Qjit, and then obtains the sampling time error t_jn, where it can be known from "Formula 10" that this constant is 2×π×(1/ M) × (1/Tcin), that is, this constant is negatively related to the period of the clock signal CKin, and is negatively related to M.

Then, the correction value generation circuit 634 calculates the correction value Vc according to the sampling time error t_jn. The rest of the calculation process is similar to the content described above with reference to FIG. 2 , and for the sake of simplicity, the details are not repeated here. The correction value generation circuit 634 may provide the correction value Vc to the operation circuit 636.

FIG. 7 is a simplified functional block diagram of an analog-to-digital conversion device 700 according to an embodiment of the present disclosure. The analog-to-digital conversion device 700 includes a clock generator 710 , an ADC to be corrected 720 and a correction system 730 . The analog-to-digital conversion device 700 is similar to the analog-to-digital conversion device 600 of FIG. 6 . For the sake of simplicity, only the differences will be described below.

The correction system 730 includes a jitter acquisition ADC 732, a correction value generation circuit 734, an operation circuit 736 and a signal processing circuit 738. The signal processing circuit 738 is coupled between the output terminal of the clock generator 710 and the input terminal of the jitter acquisition ADC 732 . The signal processing circuit 738 is used to receive the clock signal CKs_0, and to perform one or more of the following signal processing on the clock signal CKs_0 before the clock signal CKs_0 is input to the jitter capture ADC 732: amplification, frequency division, and slope adjustment. In some embodiments, the clock signal CKs_0 processed by the signal processing circuit 738 has a ramp waveform or a sawtooth waveform. The signal processing circuit 738 controls the value of M and improves the signal-to-noise ratio of the clock signal CKs_0 by controlling the waveform and frequency of the clock signal CKs_0 to stabilize the values of multiple constants in "Formula 10" and improve the calibration system 730 The accuracy of the obtained sampling time error t_jn.

The jitter acquisition ADC 732 is used to sample the clock signal CKs_0 output by the signal processing circuit 738 according to the clock signal CKin, so as to generate and output the quantized output Qjit to the correction value generation circuit 734 . The components, connection relationships, and operations of the correction value generation circuit 734 and the operation circuit 736 are respectively similar to the correction value generation circuit 634 and the operation circuit 636 in FIG. 6 , and will not be repeated here for the sake of simplicity.

FIG. 8 is a simplified functional block diagram of an analog-to-digital conversion device 800 according to an embodiment of the present disclosure. The analog-to-digital conversion device 800 includes a clock generator 810, a plurality of ADCs 820_0˜820_n-1 to be corrected, and a correction system 830. The clock generator 810 is similar to the clock generator 110 in FIG. 1 , and for the sake of simplicity, the details are not repeated here. The ADCs 820_0 to 820_n-1 to be calibrated are respectively used to receive the input signals In_0 to In_n-1, but this disclosure document is not limited to this. The ADCs 820_0 to 820_n-1 to be calibrated do not need to receive different input signals. The ADCs 820_0 to 820_n-1 to be corrected are used to sample the input signals In_0 to In_n-1 according to the clock signal CKs_0 to generate quantized outputs Qtb_0 to Qtb_n-1 respectively. In other words, each of the ADCs 820_0˜820_n-1 to be corrected samples according to the clock signal CKs_0.

The correction system 830 is used to correct the quantized outputs Qout_0˜Qout_n-1 to improve or eliminate the sampling errors in the quantized outputs Qout_0˜Qout_n-1 caused by the phase noise of the clock signal CKs_0. The correction system 830 includes a jitter acquisition ADC 832, a correction value generation circuit 834 and a plurality of operation circuits 836_0˜836_n-1. The operation circuits 836_0˜836_n-1 are used to receive the quantized outputs Qtb_0˜Qtb_n-1 respectively, and receive the correction value Vc from the correction value generation circuit 834. The operation circuits 836_0˜836_n-1 are also used to subtract the correction value Vc from each of the quantized outputs Qtb_0˜Qtb_n-1 to generate the quantized outputs Qout_0˜Qout_n-1 respectively. The quantized outputs Qout_0~Qout_n-1 are essentially the correct sampling results of the ADCs 820_0~820_n-1 to be corrected respectively.

The components, connection relationships and operations of the jitter acquisition ADC 832 and the correction value generation circuit 834 are respectively similar to the jitter acquisition ADC 632 and the correction value generation circuit 634 in FIG. 6 , and will not be repeated here for the sake of brevity. It is worth mentioning that the correction value generation circuit 834 can use any one of the quantized outputs Qtb_0˜Qtb_n-1 to calculate the correction value Vc.

FIG. 9 is a simplified functional block diagram of an analog-to-digital conversion device 900 according to an embodiment of the present disclosure. The analog-to-digital conversion device 900 includes a clock generator 910, a plurality of ADCs 920_0˜920_n-1 to be corrected, and a correction system 930. The correction system 930 includes a jitter acquisition ADC 932, a correction value generation circuit 934, and a plurality of operation circuits 936_0˜936_n-1. The analog-to-digital conversion device 900 is similar to the analog-to-digital conversion device 800 of FIG. 8 , so only the differences will be described below.

The ADCs 920_0 to 920_n-1 to be corrected are used to respectively sample the input signal In_0 according to a plurality of clock signals CKs_0 to CKs_n-1 to generate quantized outputs Qtb_0 to Qtb_n-1 respectively. The clock signals CKs_0˜CKs_n-1 are time-interleaved clock signals. In other words, in some embodiments, the analog-to-digital conversion device 900 may be used to implement a time-interleaved ADC, and may include a multiplexer (not shown in FIG. 9 ) to generate a digital output based on the quantized outputs Qout_0˜Qout_n-1 Signal. The ADC 920_0 to be corrected samples according to the clock signal CKs_0. In some embodiments, the phase of the clock signal CKs_0 leads the phases of the remaining time-interleaved clock signals CKs_1˜CKs_n-1.

In some embodiments, the correction system 830 of FIG. 8 or the correction system 930 of FIG. 9 further includes a signal processing circuit (not shown), and the clock signal CKs_0 is input to the jitter capture ADC 832 of FIG. 8 or the jitter capture ADC of FIG. 9 Before obtaining the ADC 932, the signal processing circuit is used to perform one or more of the following signal processing on the clock signal CKs_0: amplification, frequency division and slope adjustment. In addition, the clock signal CKs_0 provided by the signal processing circuit to the jitter acquisition ADC 832 of FIG. 8 or the jitter acquisition ADC 932 of FIG. 9 may have a ramp waveform or a sawtooth waveform.

In the above-mentioned embodiments, the ADC to be corrected and the jitter acquisition ADC may have the same or different circuit structures.

Please refer to FIG. 1 and FIG. 10 at the same time. FIG. 10 is a schematic spectrum diagram of quantized output according to an embodiment of this disclosure document. In the embodiment of FIG. 10 , the frequency of the clock signal CKin is 52 MHz, and the frequency of the clock signal CKs_0 is 247 MHz. The spectrum 10 with a slope shape corresponds to the quantization output Qtb_0 to be corrected in FIG. 1 . The slope shape of the spectrum 10 represents that the quantized output Qtb_0 is affected by phase noise and has a sampling error. On the other hand, spectrum 20 corresponds to the corrected quantized output Qout_0 in Figure 1 . The spectrum 20 does not have a slope-shaped part, thus proving that the corrected quantization output Qout_0 is not or almost not affected by phase noise.

Certain words are used in the description and claims to refer to specific elements. However, those with ordinary skill in the art will understand that the same components may be referred to by different names. This description and the claims do not use differences in names as a means of distinguishing components; rather, differences in functions of the components serve as a basis for distinction. The word "include" mentioned in the description and claims is an open-ended term, so it should be interpreted as "include but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if a first element is described as being coupled to a second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection such as wireless transmission or optical transmission, or through other elements or connections. Means are indirectly electrically or signal connected to the second component.

The expression "and/or" used herein includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any term in the singular shall also include the plural.

The above are only preferred embodiments of this disclosure document. Various modifications and equal changes can be made to the structure of this disclosure document without departing from the scope or spirit of this disclosure document. In summary, all modifications and equivalent changes made to this disclosure document within the scope of the appended claims are within the scope of this disclosure document.

Claims (19)

1. A correction system, characterized in that it includes: a jitter acquisition analog-to-digital converter (ADC) for sampling a clock signal to be sampled according to an operating clock signal to generate a first quantized output; A correction value generation circuit for receiving the first quantization output and a second quantization output of an ADC to be corrected to generate a correction value, wherein the operation clock signal is used to drive the ADC to be corrected for sampling, and the correction value a phase noise associated with the operating clock signal; and A first operation circuit, coupled to the correction value generating circuit, is used to subtract the correction value from the second quantized output to generate a third quantized output. 2. The correction system according to claim 1, characterized in that the correction value generating circuit includes: an error acquisition circuit for receiving the first quantized output and for obtaining a sampling time error of the ADC to be corrected from the first quantized output, wherein the sampling time error is associated with the phase noise; a differentiating circuit for receiving the second quantized output to calculate a slope of the second quantized output; and A second operation circuit is used to multiply the sampling time error by the slope to generate the correction value. 3. The calibration system of claim 2, wherein the error acquisition circuit obtains the product of the sampling time error and a constant from the first quantized output, and then obtains the sampling time error, wherein the constant is negatively correlated. period of the operating clock signal. 4. The calibration system according to claim 3, wherein the period of the operating clock signal is M times the period of the clock signal to be sampled, where M is a positive number and the constant is positively related to M. 5. The calibration system according to claim 1, characterized in that the calibration system further includes: A signal processing circuit for performing one or more of the following on the clock signal to be sampled: amplification, frequency division and slope adjustment before the clock signal to be sampled is input to the jitter capture ADC. 6. The calibration system according to claim 5, wherein the clock signal to be sampled is used to input a clock generator, and the operating clock signal is generated by the clock generator based on the clock signal to be sampled. 7. The calibration system according to claim 5, wherein the clock signal to be sampled outputted by the signal processing circuit has a ramp waveform or a sawtooth waveform. 8. A correction system, characterized by comprising: a jitter acquisition analog-to-digital converter (ADC) for sampling a clock signal to be sampled according to an operating clock signal to generate a first quantized output; A correction value generation circuit for receiving the first quantization output and a second quantization output of an ADC to be corrected to generate a correction value, wherein the clock signal to be sampled is used to drive the ADC to be corrected for sampling, and the correction a phase noise value associated with the clock signal to be sampled; and A first operation circuit, coupled to the correction value generating circuit, is used to subtract the correction value from the second quantized output to generate a third quantized output. 9. The correction system according to claim 8, characterized in that the correction value generating circuit includes: an error acquisition circuit for receiving the first quantized output and for obtaining a sampling time error of the ADC to be corrected from the first quantized output, wherein the sampling time error is associated with the phase noise; a differentiating circuit for receiving the second quantized output to calculate a slope of the second quantized output; and A second operation circuit is used to multiply the sampling time error by the slope to generate the correction value. 10. The calibration system according to claim 9, wherein the error acquisition circuit obtains the product of the sampling time error and a constant from the first quantized output, and then obtains the sampling time error, wherein the constant is negatively correlated. period of the operating clock signal. 11. The calibration system according to claim 10, wherein the period of the operating clock signal is 1/M times the period of the clock signal to be sampled, where M is a positive number and the constant is negatively related to M . 12. The calibration system according to claim 8, characterized in that the calibration system further includes: A signal processing circuit for performing one or more of the following on the clock signal to be sampled: amplification, frequency division and slope adjustment before the clock signal to be sampled is input to the jitter capture ADC. 13. The calibration system according to claim 12, wherein the operating clock signal is used to input a clock generator, and the clock signal to be sampled is generated by the clock generator based on the operating clock signal. 14. The calibration system according to claim 12, wherein the clock signal to be sampled output by the signal processing circuit has a ramp waveform or a sawtooth waveform. 15. An analog-to-digital conversion device, characterized by comprising: a clock pulse generator; At least one analog-to-digital converter (ADC) to be corrected, wherein each ADC to be corrected is used to generate a second quantized output, and one of the at least one ADC to be corrected samples according to the output of the clock generator. generating the second quantized output; and A correction system for receiving the input of the clock generator, the output of the clock generator and the second quantized output of the one of the at least one ADC to be corrected to generate a correction value, and for generating a correction value according to the The correction value corrects the second quantized output of each ADC to be corrected to generate a third quantized output; The correction value is associated with a phase noise at the output of the clock generator. 16. The analog-to-digital conversion device of claim 15, wherein the at least one ADC to be corrected includes a plurality of ADCs to be corrected, wherein each ADC to be corrected samples based on the output of the clock generator. 17. The analog-to-digital conversion device according to claim 15, wherein the at least one ADC to be corrected includes a plurality of ADCs to be corrected, wherein the plurality of ADCs to be corrected are sampled according to a plurality of time-interleaved clock signals, and the The plurality of time-interleaved clock signals includes the output of the clock generator, and the phase of the output of the clock generator leads the phase of the remaining time-interleaved clock signals in the plurality of time-interleaved clock signals. 18. The analog-to-digital conversion device of claim 15, wherein the at least one ADC to be corrected includes a plurality of ADCs to be corrected, wherein the correction system includes: a jitter acquisition ADC for sampling the input of the clock generator according to the output of the clock generator to generate a first quantized output; a correction value generation circuit for receiving the first quantization output and the second quantization output of the one of the at least one ADC to be corrected to generate the correction value; and A plurality of first operation circuits are coupled to the correction value generation circuit and are respectively coupled to the plurality of ADCs to be corrected, wherein each first operation circuit is used to convert the corresponding one of the plurality of ADCs to be corrected. The correction value is subtracted from the second quantized output to produce the third quantized output. 19. The analog-to-digital conversion device of claim 15, wherein the at least one ADC to be corrected includes a plurality of ADCs to be corrected, wherein the correction system includes: a jitter acquisition ADC for sampling the output of the clock generator according to the input of the clock generator to generate a first quantized output; a correction value generation circuit for receiving the first quantization output and the second quantization output of the one of the at least one ADC to be corrected to generate the correction value; and A plurality of first operation circuits are coupled to the correction value generation circuit and are respectively coupled to the plurality of ADCs to be corrected, wherein each first operation circuit is used to convert the corresponding one of the plurality of ADCs to be corrected. The correction value is subtracted from the second quantized output to produce the third quantized output.