CN117059720B - Light-emitting chip, preparation method thereof and display panel - Google Patents
Light-emitting chip, preparation method thereof and display panel Download PDFInfo
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Abstract
The application provides a light-emitting chip, a preparation method thereof and a display panel. The preparation method of the light-emitting chip comprises sequentially epitaxially growing an epitaxial layer on a substrate; depositing a transparent conductive layer on the surface of the second semiconductor layer away from the substrate; etching from one side of the transparent conductive layer to form a groove structure, and dividing the epitaxial layer into a plurality of light-emitting units which are arranged at intervals; the groove structure comprises a first groove which exposes the first semiconductor layer; a first electrode is arranged at the bottom of the first groove; the first electrode is in contact with the first semiconductor layer; an insulating layer is arranged on one side of the substrate; opening at the position of the insulating layer corresponding to the transparent conductive layer, and exposing a part of the surface of the transparent conductive layer far away from the substrate; a second electrode is arranged on one side of the insulating layer away from the substrate; the second electrode is contacted with the exposed part of the surface of the transparent conductive layer; the second electrode extends from the top surface of one light emitting unit to the top surface of an adjacent light emitting unit. The method can reduce the probability of broken wires of the light-emitting chip and strengthen the reliability of the light-emitting chip.
Description
Technical Field
The invention relates to the technical field of display, in particular to a light-emitting chip, a preparation method thereof and a display panel.
Background
The Micro-LED chip utilizes a micron-sized (generally less than 50 um) inorganic LED device as a luminous pixel to realize active luminous matrix display, and has the characteristics of quick response, active illumination, high contrast, long service life and the like as an emerging technology. Micro-LED array structures are divided into active and passive matrices. Compared with an active matrix Micro-LED array, the passive matrix Micro-LED array has the advantages of simple preparation process, low cost, high technical maturity and the like, and still has certain application in some specific occasions.
For the existing passive matrix light-emitting chip, the problem of wire breakage in the light-emitting chip causes that the light-emitting chip cannot work normally, so that the reliability is reduced, and the yield of products is greatly influenced.
Disclosure of Invention
The application provides a light-emitting chip, a preparation method thereof and a display panel, which mainly solve the technical problems that the light-emitting chip cannot work normally and the reliability is reduced and the yield of products is greatly affected due to the fact that the wire breakage problem exists in the light-emitting chip.
In order to solve the technical problems, the application provides a preparation method of a light-emitting chip, which comprises the following steps:
Sequentially epitaxially growing a buffer layer, a first semiconductor layer, a light-emitting layer and a second semiconductor layer on a substrate; wherein the first semiconductor layer, the light emitting layer, and the second semiconductor layer are defined as epitaxial layers;
depositing a transparent conductive layer on a surface of the second semiconductor layer away from the substrate;
etching from one side of the transparent conductive layer to form a groove structure, wherein the groove structure divides the epitaxial layer into a plurality of light-emitting units which are arranged at intervals; the groove structure comprises a first groove which exposes the first semiconductor layer;
A first electrode is arranged at the bottom of the first groove; the first electrode is in contact with the first semiconductor layer;
An insulating layer is arranged on one side of the substrate, and the insulating layer covers the buffer layer, the epitaxial layer, the first electrode and the transparent conductive layer;
Opening at the position of the insulating layer corresponding to the transparent conductive layer, and exposing a part of the surface of the transparent conductive layer away from the substrate;
A second electrode is arranged on one side of the insulating layer away from the substrate; the second electrode is contacted with the exposed part of the surface of the transparent conductive layer; the second electrode extends from a top surface of one of the light emitting units to a top surface of an adjacent light emitting unit.
Wherein, the step of etching from one side of the transparent conductive layer to form a groove structure comprises the following steps:
Etching from the transparent conductive layer until the first semiconductor layer is exposed, and forming the first groove;
Etching from one side of the first semiconductor layer until the buffer layer is exposed, and forming a second groove;
starting etching from the buffer layer until the substrate is exposed, and forming a third groove;
In the step of providing an insulating layer on one side of the substrate, the insulating layer covers the first groove, the second groove, and the third groove.
Wherein, the step of disposing an insulating layer on one side of the substrate comprises:
And performing multiple depositions at positions corresponding to the first groove, the second groove and the third groove, so that the thickness of the insulating layer at the positions corresponding to the first groove, the second groove and the third groove is larger than that of the insulating layers at other positions.
Wherein, the step of disposing an insulating layer on one side of the substrate comprises: the insulating layer is formed by multiple sputter depositions and the substrate is rotated between the steps of adjacent sputter depositions.
The deposition time of the multiple sputtering deposition is gradually reduced, and other parameters in the process of each sputtering deposition are kept unchanged; or (b)
The deposition power of the multiple sputtering deposition is gradually reduced, and other parameters in the process of each sputtering deposition are kept unchanged.
Wherein, the step of disposing an insulating layer on one side of the substrate comprises:
forming the insulating layer by multiple sputter deposition and tilting the substrate between adjacent sputter deposition steps to change the deposition direction;
Wherein other parameters in each sputter deposition process remain unchanged.
Wherein the step of tilting the substrate between adjacent sputter deposition steps comprises:
And enabling the deposition direction of the raw materials of the insulating layer to face the gap between the first electrode and the light-emitting layer, wherein the included angle between the deposition direction and the substrate is 30-60 degrees.
In order to solve the above technical problems, another technical solution adopted by the present application is to provide a light emitting chip, which is prepared by any one of the preparation methods described above, including:
A substrate;
the buffer layer is arranged on one side of the substrate;
The epitaxial layer is arranged on one side of the buffer layer away from the substrate; the epitaxial layer comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer;
The transparent conductive layer is arranged on one side of the epitaxial layer, which is far away from the substrate; the light-emitting chip is provided with a groove structure formed on one side of the transparent conductive layer, and the groove structure divides the epitaxial layer into a plurality of light-emitting units which are arranged at intervals; the groove structure comprises a first groove formed in one side of the transparent conductive layer, so that the first semiconductor layer is exposed; the groove structure further comprises a second groove formed in one side of the first semiconductor layer, so that the buffer layer is exposed; the groove structure further comprises a third groove formed in one side of the buffer layer, so that the substrate is exposed;
The first electrode is arranged at the bottom of the first groove and is in contact electrical connection with the first semiconductor layer;
An insulating layer arranged on one side of the substrate and covering the buffer layer, the epitaxial layer, the first electrode and the transparent conductive layer; the insulating layer is provided with an opening at the position corresponding to the transparent conductive layer, and a part of the surface of one side of the transparent conductive layer far away from the substrate is exposed;
the second electrode is arranged on one side of the insulating layer away from the substrate and is in contact with the exposed part of the surface of the transparent conductive layer; the second electrode extends from a top surface of one of the light emitting units to a top surface of an adjacent light emitting unit.
The thickness of the insulating layer corresponding to the positions of the first groove, the second groove and the third groove is larger than that of the insulating layer at other positions.
In order to solve the above technical problems, another technical solution adopted by the present application is to provide a method for manufacturing a light emitting chip, where the light emitting chip or the display panel manufactured by the method according to any one of the above related aspects includes any one of the light emitting chips according to any one of the above related aspects.
The application provides a light-emitting chip and a preparation method thereof, and a display panel, wherein the preparation method of the light-emitting chip comprises the steps of sequentially epitaxially growing a buffer layer, a first semiconductor layer, a light-emitting layer and a second semiconductor layer on a substrate; wherein the first semiconductor layer, the light emitting layer and the second semiconductor layer are defined as epitaxial layers; depositing a transparent conductive layer on the surface of the second semiconductor layer away from the substrate; etching from one side of the transparent conductive layer to form a groove structure, wherein the groove structure divides the epitaxial layer into a plurality of light-emitting units which are arranged at intervals; the groove structure comprises a first groove which exposes the first semiconductor layer; a first electrode is arranged at the bottom of the first groove; the first electrode is in contact with the first semiconductor layer; an insulating layer is arranged on one side of the substrate, and the insulating layer covers the buffer layer, the epitaxial layer, the first electrode and the transparent conductive layer; opening at the position of the insulating layer corresponding to the transparent conductive layer, and exposing a part of the surface of the transparent conductive layer far away from the substrate; a second electrode is arranged on one side of the insulating layer away from the substrate; the second electrode is contacted with the exposed part of the surface of the transparent conductive layer; the second electrode extends from the top surface of one light emitting unit to the top surface of an adjacent light emitting unit. According to the method, the groove structure is formed by etching, so that the height difference of the groove is reduced, the probability of broken lines of the light-emitting chip can be reduced, the reliability of the light-emitting chip is enhanced, and the yield is effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart illustrating steps of a method for manufacturing a light emitting chip according to a first embodiment of the present application;
fig. 2 is a schematic diagram of the specific structure of step S01;
Fig. 3 is a schematic diagram of the specific structure of step S02;
Fig. 4 is a schematic structural diagram of step S03;
fig. 5 is a schematic structural diagram of step S04;
fig. 6 is a schematic diagram of the specific structure of step S05;
fig. 7 is a schematic diagram of the specific structure of step S06;
fig. 8 is a specific structural diagram of step S07;
FIG. 9 is a flowchart illustrating steps of a method for fabricating a light emitting chip according to a second embodiment of the present application;
Fig. 10 is a specific flowchart of step S03A;
Fig. 11 is a schematic diagram showing specific structures of step S03A1, step S03A2 and step S03 A3;
fig. 12 is a schematic structural diagram of a light emitting chip manufactured by a manufacturing method of a light emitting chip according to a second embodiment of the present application;
FIG. 13 is a flowchart showing steps of a method for manufacturing a light emitting chip according to a third embodiment of the present application;
Fig. 14 is a schematic structural diagram of a light emitting chip manufactured by a manufacturing method of a light emitting chip according to a third embodiment of the present application;
FIG. 15 is a flowchart showing steps of a method for manufacturing a light emitting chip according to a fourth embodiment of the present application;
FIG. 16 is a schematic view showing a specific structure of an insulating layer in the prior art;
Fig. 17 is a schematic structural diagram of an insulating layer prepared by the method for preparing a light emitting chip according to the fourth embodiment;
FIG. 18 is a flowchart showing steps of a method for fabricating a light emitting chip according to a fifth embodiment of the present application;
FIG. 19 is a schematic view showing the construction of a fifth embodiment of the process;
fig. 20 is a schematic structural diagram of a light emitting chip according to an embodiment of the present application.
Reference numerals illustrate:
10-a substrate; 20-a buffer layer; 30-a first semiconductor layer; 40-a light emitting layer; 50-a second semiconductor layer; 60-a transparent conductive layer; 70-a first electrode; 80-an insulating layer; 90-a second electrode; 1000-a light emitting chip; a-groove structure; a1-a first groove; a2-a second groove; a3-a third groove; a4-fourth grooves; b-opening; c-gap; a D-light emitting unit; g-through holes; w-epitaxial layer.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, interfaces, techniques, etc., in order to provide a thorough understanding of the present application.
The terms "first," "second," "third," and the like in this disclosure are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. All directional indications (such as up, down, left, right, front, back … …) in the embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular gesture (as shown in the drawings), and if the particular gesture changes, the directional indication changes accordingly. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
The present application will be described in detail with reference to the accompanying drawings and examples.
Referring to fig. 1, fig. 1 is a flowchart illustrating steps of a method for manufacturing a light emitting chip according to a first embodiment of the present application.
Step S01: and sequentially epitaxially growing a buffer layer, a first semiconductor layer, a light-emitting layer and a second semiconductor layer on the substrate.
Referring to fig. 2, fig. 2 is a schematic structural diagram of step S01. The buffer layer 20, the first semiconductor layer 30, the light emitting layer 40, and the second semiconductor layer 50 are sequentially epitaxially grown on the substrate 10 using a Metal Organic Chemical Vapor Deposition (MOCVD) apparatus. Wherein the thickness of the buffer layer 20 is 1-5um. The epitaxial layer W includes a first semiconductor layer 30 having a thickness of 1-5um, a light emitting layer 40 having a thickness of 50-200nm, and a second semiconductor layer 50 having a thickness of 0.1-0.5 um.
Specifically, the material of the substrate 10 may be one of silicon carbide, silicon, sapphire, and the like; the present embodiment will be mainly described by taking the sapphire substrate 10 as an example. Specifically, the buffer layer 20 is a gallium nitride (GaN) layer; the first semiconductor layer 30 is an N-type semiconductor layer; the light emitting layer 40 is a multiple quantum well (Multiple Quantum Well, MQW) layer; the second semiconductor layer 50 is a P-type semiconductor layer.
In this embodiment, the buffer layer 20 is a GaN layer with a thickness of 3 um. The first semiconductor layer 30 is an N-type GaN layer having a thickness of 2um, the light emitting layer 40 is an InGaN/GaN multiple quantum well layer having a thickness of 100nm, and the second semiconductor layer 50 is a P-type GaN layer having a thickness of 0.2 um.
Step S02: and depositing a transparent conductive layer on the surface of the second semiconductor layer away from the substrate.
Referring to fig. 3, fig. 3 is a schematic structural diagram of step S02. Depositing a transparent conductive layer 60 on a surface of the second semiconductor layer 50 remote from the substrate 10 by an electron beam evaporation apparatus or a magnetron sputtering apparatus; next, ohmic contact between the transparent conductive layer 60 and the second semiconductor layer 50 is formed through an annealing process. Specifically, the transparent conductive layer 60 is an Indium Tin Oxide (ITO) film, and the transparent conductive layer 60 functions as a current diffusion layer.
Step S03: etching from one side of the transparent conductive layer to form a groove structure, wherein the groove structure divides the epitaxial layer into a plurality of light-emitting units which are arranged at intervals; the recess structure includes a first recess that exposes the first semiconductor layer.
In a specific embodiment, step S03 further includes starting etching from the first semiconductor layer 30 side until the substrate 10 is exposed, forming a fourth recess A4. Referring to fig. 4, fig. 4 is a schematic structural diagram of step S03. The groove structure a is etched from one side of the transparent conductive layer 60. The groove structure A divides the epitaxial layer W into a plurality of light-emitting units D which are arranged at intervals; the light emitting unit D includes a first semiconductor layer 30, a light emitting layer 40, and a second semiconductor layer 50. Specifically, the groove structure a includes a first groove A1 and a fourth groove A4 etched from the transparent conductive layer 60 side such that the first semiconductor layer 30 is exposed, forming the first groove A1; the etching is started from the first semiconductor layer 30 side, i.e., the bottom surface of the first recess A1, until the substrate 10 is exposed, forming a fourth recess A4.
Step S04: a first electrode is arranged at the bottom of the first groove; the first electrode is in contact with the first semiconductor layer.
Referring to fig. 5, fig. 5 is a schematic structural diagram of step S04. The first electrode 70 is formed on a side surface of the first semiconductor layer 30 at the bottom of the first recess A1 remote from the substrate 10 by sputter deposition. Specifically, the first electrode 70 is an N-type electrode and contacts the first semiconductor layer 30, and the first electrode 70 and the light emitting layer 40 are disposed at a distance. The material of the first electrode 70 may be metal Ti or metal Au, or a multi-layer structure of metal Ti and Au, or other conductive metals, which is not limited in the present application.
Step S05: an insulating layer is arranged on one side of the substrate, and covers the buffer layer, the epitaxial layer, the first electrode and the transparent conductive layer.
Referring to fig. 6, fig. 6 is a schematic structural diagram of step S05. The insulating layer 80 is formed by sputter deposition on one side of the substrate 10 by a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus. The insulating layer 80 covers the buffer layer 20, the epitaxial layer W, the first electrode 70, and the transparent conductive layer 60. The insulating layer 80 serves to isolate the first electrode 70 from the second electrode 90. Specifically, the thickness of the insulating layer 80 is 300-600nm, and the main material is silicon oxide or nitride or metal oxide. In this embodiment, the material of the insulating layer 80 is silicon dioxide.
Step S06: and opening the insulating layer at a position corresponding to the transparent conductive layer, and exposing a part of the surface of the transparent conductive layer away from the substrate.
Referring to fig. 7, fig. 7 is a schematic diagram of a specific structure of step S06. An opening B is etched in the insulating layer 80 at a position corresponding to the transparent conductive layer 60, the opening B exposing a portion of the surface of the transparent conductive layer 60 away from the substrate 10.
Step S07: a second electrode is arranged on one side of the insulating layer away from the substrate; the second electrode is contacted with the exposed part of the surface of the transparent conductive layer; the second electrode extends from the top surface of one light emitting unit to the top surface of an adjacent light emitting unit.
Referring to fig. 8, fig. 8 is a schematic diagram showing a specific structure of step S07. Similar to the previous preparation of the first electrode 70, the second electrode 90 is formed by sputter deposition on the side of the insulating layer 80 remote from the substrate 10. The second electrode 90 is a P-type electrode and contacts with a portion of the exposed surface of the transparent conductive layer 60. The second electrodes 90 extend through the groove structure a in a lateral direction, climb up and down at the position of the groove structure a, extend from the top surface of one light emitting unit D to the top surface of an adjacent light emitting unit D, so that the second electrodes 90 of the plurality of light emitting units D are connected to each other.
The light emitting chip 1000 can be prepared by the preparation method, and the first groove A1 and the fourth groove A4 in the light emitting chip 1000 reduce the height difference at the groove structure A, so that the second electrode 90 climbs up and down at the position of the groove structure A and is not easy to break, and the probability of breaking the light emitting chip 1000 can be reduced.
Referring to fig. 9, fig. 9 is a flowchart illustrating steps of a method for manufacturing a light emitting chip according to a second embodiment of the present application. The preparation method in this embodiment is the same as the steps in the first embodiment, except that in this embodiment, the groove structure a prepared in step S03A includes a first groove A1, a second groove A2, and a third groove A3; and in the step of disposing the insulating layer 80 on one side of the substrate 10, the insulating layer 80 covers the first, second and third grooves A1, A2 and A3.
Referring to fig. 10, fig. 10 is a specific flowchart of step S03A. Wherein step 030 includes:
step S03A1: the first recess is formed from the transparent conductive layer until the first semiconductor layer is exposed.
Step S03A2: and etching from one side of the first semiconductor layer until the buffer layer is exposed, so as to form a second groove.
Step S03A3: and etching from the buffer layer until the substrate is exposed, and forming a third groove.
Referring to fig. 11, fig. 11 is a schematic diagram showing specific structures of step S03A1, step S03A2, and step S03 A3. The first recess A1 is formed from the start of etching of the transparent conductive layer 60 until the first semiconductor layer 30 is exposed. The second recess A2 is formed from the side of the first semiconductor layer 30 until the buffer layer 20 is exposed. The third recess A3 is formed from the start of etching of the buffer layer 20 until the substrate 10 is exposed.
With further reference to fig. 11 and fig. 12, fig. 12 is a schematic structural diagram of a light emitting chip manufactured by a light emitting chip manufacturing method according to a second embodiment of the present application. According to the preparation method of the light-emitting chip 1000, a transitional step is added in the etching process, the second groove A2 and the third groove A3 are formed by etching, the problem that the height difference is too large due to the fact that only the fourth groove A4 is formed is solved, the risk that the second electrode 90 is easy to break is further reduced, and the reliability of the light-emitting chip 1000 is improved.
Referring to fig. 13 and 14, fig. 13 is a flowchart illustrating steps of a method for manufacturing a light emitting chip according to a third embodiment of the present application; fig. 14 is a schematic structural diagram of a light emitting chip manufactured by a manufacturing method of a light emitting chip according to a third embodiment of the present application. The preparation method in this embodiment is substantially the same as the steps of the second embodiment, except that the step S05A of disposing the insulating layer 80 on one side of the substrate 10 in this embodiment further includes:
and performing multiple depositions at positions corresponding to the first groove, the second groove and the third groove, so that the thickness of the insulating layer at the positions corresponding to the first groove, the second groove and the third groove is larger than that of the insulating layer at other positions.
It will be appreciated that the second electrode 90 at the groove structure a needs to climb a slope and thus the risk of wire breakage is more likely to occur. Therefore, on the basis of the first embodiment, the multiple depositions are performed at the positions corresponding to the first groove A1, the second groove A2 and the third groove A3, so that the thickness of the insulating layer 80 at the positions corresponding to the first groove A1, the second groove A2 and the third groove A3 is larger than that of the insulating layer 80 at other positions, the height difference at the groove structure a is further slowed down, the topography is more gentle, the risk that the second electrode 90 is easy to break is more likely to be reduced, and the reliability of the light emitting chip 1000 is improved; in addition, increasing the thickness of the insulating layer 80 may also reduce the probability of the light emitting chip 1000 being shorted.
Referring to fig. 15, fig. 15 is a flowchart illustrating steps of a method for manufacturing a light emitting chip according to a fourth embodiment of the present application. The preparation method in this embodiment is the same as the steps of the second embodiment, except that step S05B of disposing the insulating layer 80 on one side of the substrate 10 in this embodiment includes:
the insulating layer is formed by multiple sputter depositions and the substrate is rotated between the steps of adjacent sputter depositions.
In the present embodiment, the insulating layer 80 may be formed by sputtering deposition a plurality of times and rotating the substrate 10 between the steps of the adjacent two times, or the thickness and the compactness of the insulating layer 80 corresponding to the positions of the first groove A1, the second groove A2, and the third groove A3 may be increased by sputtering deposition a plurality of times and rotating the substrate 10 between the steps of the adjacent two times.
Referring to fig. 16, fig. 16 is a schematic view showing a specific structure of an insulating layer in the prior art. It has been found that during the course of a particular experiment, after the insulating layer 80 is initially formed, a number of pores are formed due to the non-densification, and as the deposition time increases, the insulating layer 80 continues to grow, and a number of pores are covered. While a small portion of the small hole grows only along the edge of the small hole due to the insulating layer 80, and finally a through-hole G shown in fig. 16 is formed. Thus, the present embodiment adopts a "step deposition" method, that is, the insulating layer 80 is formed by multiple sputtering depositions, and the substrate 10 is rotated between the steps of two adjacent sputtering depositions, and in a specific embodiment, the substrate 10 may be rotated by arranging a rotary table under the substrate 10 or by configuring a mechanical arm to rotate the substrate 10, which is not limited in the present application.
With further reference to fig. 17, fig. 17 is a schematic structural diagram of an insulating layer prepared by using the method for preparing a light emitting chip according to the fourth embodiment. It can be intuitively seen that the probability of forming the through hole G can be effectively reduced, the compactness of the insulating layer 80 is improved, and the possibility of occurrence of short circuit between the first electrode 70 and the second electrode 90 is reduced. The structure of the light emitting chip 1000 finally obtained in this embodiment is substantially the same as that of the light emitting chip 1000 of the second embodiment in fig. 12, except that the insulating layer 80 prepared by the preparation method provided in this embodiment is denser than the insulating layer 80 of the second embodiment.
In a specific implementation, multiple depositions may be performed in different ways. The first mode is that the deposition time of the multi-time sputtering deposition is gradually reduced, and other parameters in the process of each sputtering deposition are kept unchanged. With the time of each sputter deposition reduced, it is further ensured that the thickness of the finally formed insulating layer 80 is smaller than that of the insulating layer 80 in the first embodiment, and the probability of forming the through hole G is effectively reduced, so that the possibility of occurrence of short circuit between the first electrode 70 and the second electrode 90 is reduced. It will be appreciated that due to the routing of the first electrode 70 and the second electrode 90, the first electrode 70 and the second electrode 90 may be partially laminated, and the laminated position is isolated only by the insulating layer 80. If the insulating layer 80 penetrates the hole G too much, the first electrode 70 and the second electrode 90 are liable to be short-circuited at the lamination position.
The second mode is that the deposition power of the multi-time sputtering deposition is gradually reduced, and other parameters in the process of each sputtering deposition are kept unchanged. With the gradual decrease of the power of each sputter deposition, the thickness of the finally formed insulating layer 80 and the thickness of the insulating layer 80 in the first embodiment can be ensured to be smaller, and the probability of forming the through hole G can be effectively reduced, so that the possibility of short circuit between the first electrode 70 and the second electrode 90 is reduced.
Referring to fig. 18, fig. 18 is a flowchart illustrating steps of a method for manufacturing a light emitting chip according to a fifth embodiment of the present application. The preparation method in this embodiment is the same as the steps of the second embodiment, except that the step S05C of disposing the insulating layer 80 on one side of the substrate 10 in this embodiment includes:
The insulating layer is formed by multiple sputter deposition and the substrate is tilted between adjacent sputter deposition steps to change the deposition direction.
In the present embodiment, the insulating layer 80 may be formed by sputtering deposition a plurality of times and tilting the substrate 10 between the steps of the adjacent two times, and the thickness and the compactness of the insulating layer 80 corresponding to the positions of the first groove A1, the second groove A2, and the third groove A3 may also be increased by sputtering deposition a plurality of times and tilting the substrate 10 between the steps of the adjacent two times.
In particular, other parameters during each sputter deposition remain unchanged. The present embodiment changes the deposition direction by tilting the substrate 10 between the steps of the adjacent two sputter depositions. As the substrate 10 is tilted between the two adjacent sputtering deposition steps to change the deposition direction, the probability of forming the through hole G can be effectively reduced, and the possibility of occurrence of short circuit between the first electrode 70 and the second electrode 90 can be reduced.
Referring to fig. 19, fig. 19 is a schematic structural view of a preparation process of a fifth embodiment. In a specific implementation, the step of tilting the substrate 10 between the steps of two adjacent sputter depositions includes directing the deposition direction of the raw material of the insulating layer 80 toward the gap C between the first electrode 70 and the light emitting layer 40, and the deposition direction has an included angle of 30-60 degrees with the substrate 10.
By tilting the substrate 10 between adjacent sputter deposition steps, the angle of the deposition direction from the substrate 10 can be varied, wherein the angle is in the range of 30-60 degrees, such as 45 degrees. Meanwhile, the deposition direction of the raw material of the insulating layer 80 is directed to the gap C between the first electrode 70 and the light emitting layer 40, so that the gap C generated between the first electrode 70 and the light emitting layer 40 in the deposition process can be filled, the insulating layer 80 is flatter at the gap C, the risk that the second electrode 90 is easy to break at the gap C is reduced, and the reliability of the light emitting chip 1000 is improved.
The method for manufacturing the light emitting chip 1000 provided in the above embodiment of the present application may be combined between the methods of the different embodiments. For example, the method of the second embodiment may be combined with the method of the third embodiment, and the thickness of the insulating layer 80 corresponding to the positions of the first, second and third grooves A1, A2 and A3 may be made larger than the thickness of the insulating layer 80 at other positions, so as to reduce the probability of short-circuiting of the light emitting chip 1000; meanwhile, the problem that the height difference of the groove structure A is too large is solved, and the risk that the second electrode 90 is easy to break is further reduced. The combined method can reduce the probability of short circuit of the light emitting chip 1000, reduce the risk of disconnection and improve the reliability of the light emitting chip 1000. For example, the method of the first embodiment may be combined with the methods of the third embodiment and the fourth embodiment, that is, without adding an etching step on the basis of the first embodiment, deposition is performed only for a plurality of times at positions corresponding to the first grooves A1 and the fourth grooves A4, so that the thickness of the insulating layer 80 at the positions corresponding to the first grooves A1 and the fourth grooves A4 is greater than the thickness of the insulating layer 80 at other positions; in sputter depositing the insulating layer 80, the insulating layer 80 is formed by multiple sputter depositions and the substrate 10 is rotated between the steps of adjacent sputter depositions. The structure does not need to add an etching step, has simple process, relieves the height difference of the groove structure A, and reduces the risk that the second electrode 90 is easy to break.
By optimizing the etching step and the deposition process of the insulating layer 80, the preparation method of the light emitting chip 1000 provided by the embodiment of the application effectively reduces the risk of disconnection of the second electrode 90 and the risk of short circuit between the first electrode 70 and the second electrode 90, and enhances the reliability of the light emitting chip 1000. And the preparation method is simple, the cost is low, and the yield of the product is improved.
Referring to fig. 20, fig. 20 is a schematic structural diagram of a light emitting chip according to an embodiment of the application. The present application also provides a light emitting chip 1000, where the light emitting chip 1000 may be prepared by the preparation method of the light emitting chip 1000 provided in any of the foregoing embodiments, and the present embodiment mainly uses the light emitting chip 1000 obtained by the preparation method of the second embodiment as an example. The light emitting chip 1000 includes a substrate 10, a buffer layer 20, an epitaxial layer W, a transparent conductive layer 60, a first electrode 70, an insulating layer 80, and a second electrode 90.
The material of the substrate 10 may be one of silicon carbide, silicon, sapphire, and the like. The buffer layer 20 is disposed on one side of the substrate 10. The epitaxial layer W is disposed on a side of the buffer layer 20 remote from the substrate 10. The epitaxial layer W includes a first semiconductor layer 30, a light emitting layer 40, and a second semiconductor layer 50. Specifically, the buffer layer 20 is a gallium nitride layer; the first semiconductor layer 30 is an N-type semiconductor layer; the light emitting layer 40 is an InGaN/GaN multiple quantum well (Multiple Quantum Well, MQW) layer; the second semiconductor layer 50 is a P-type semiconductor layer.
The transparent conductive layer 60 is disposed on a side of the epitaxial layer W remote from the substrate 10. Specifically, the transparent conductive layer 60 is an Indium Tin Oxide (ITO) film, and the transparent conductive layer 60 functions as a current diffusion layer. The light emitting chip 1000 has a groove structure a formed on one side of the transparent conductive layer 60, and the groove structure a divides the epitaxial layer W into a plurality of light emitting units D arranged at intervals; the groove structure A comprises a first groove A1 formed on one side of the transparent conductive layer 60, so that the first semiconductor layer 30 is exposed; the groove structure a further includes a second groove A2 opened from one side of the first semiconductor layer 30 so that the buffer layer 20 is exposed; the recess structure a further includes a third recess A3 opened from one side of the buffer layer 20 so that the substrate 10 is exposed.
The first electrode 70 is disposed at the bottom of the first recess A1 and is in contact electrical connection with the first semiconductor layer 30. An insulating layer 80 is provided on one side of the substrate 10 and covers the buffer layer 20, the epitaxial layer W, the first electrode 70, and the transparent conductive layer 60. The insulating layer 80 has an opening B at a position corresponding to the transparent conductive layer 60, exposing a portion of the surface of the transparent conductive layer 60 on a side away from the substrate 10. The second electrode 90 is disposed on a side of the insulating layer 80 away from the substrate 10 and contacts with a portion of the exposed surface of the transparent conductive layer 60; the second electrode 90 extends from the top surface of one light emitting cell D to the top surface of an adjacent light emitting cell D. Specifically, the main material of the insulating layer 80 is silicon dioxide. Specifically, the materials of the first electrode 70 and the second electrode 90 may be metal Ti or metal Au, or may be other conductive metals, which is not limited in the present application.
The thickness of the insulating layer 80 at the positions corresponding to the first, second and third grooves A1, A2 and A3 in the light emitting chip 1000 is greater than the thickness of the insulating layer 80 at other positions. The height difference at the groove structure A can be slowed down, so that the topography is more gentle, the risk that the second electrode 90 is easy to break is reduced more possibly, and the reliability of the light-emitting chip 1000 is improved; in addition, increasing the thickness of the insulating layer 80 may reduce the probability of short circuit of the light emitting chip 1000.
The present application also provides a display panel including the light emitting chip 1000 described above, or a display panel including the light emitting chip 1000 prepared by the preparation method provided in the above embodiments. Specifically, in this embodiment, by manufacturing the light emitting chip 1000 in the display panel, the risk of wire breakage and short circuit can be reduced by the light emitting chip 1000 provided in this embodiment, so that a better light emitting effect is provided, and further the display panel has a better display effect. The display panel comprises the light-emitting chip 1000 prepared by the preparation method, so that the risks of wire breakage and short circuit can be reduced, and a better display effect is further achieved.
It will be evident to those skilled in the art that the application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.
Claims (8)
1. A method of manufacturing a light emitting chip, comprising:
Sequentially epitaxially growing a buffer layer, a first semiconductor layer, a light-emitting layer and a second semiconductor layer on a substrate; wherein the first semiconductor layer, the light emitting layer, and the second semiconductor layer are defined as epitaxial layers;
depositing a transparent conductive layer on a surface of the second semiconductor layer away from the substrate;
etching from one side of the transparent conductive layer to form a groove structure, wherein the groove structure divides the epitaxial layer into a plurality of light-emitting units which are arranged at intervals; the groove structure comprises a first groove which exposes the first semiconductor layer;
A first electrode is arranged at the bottom of the first groove; the first electrode is in contact with the first semiconductor layer;
An insulating layer is arranged on one side of the substrate, and the insulating layer covers the buffer layer, the epitaxial layer, the first electrode and the transparent conductive layer;
Opening at the position of the insulating layer corresponding to the transparent conductive layer, and exposing a part of the surface of the transparent conductive layer away from the substrate;
A second electrode is arranged on one side of the insulating layer away from the substrate; the second electrode is contacted with the exposed part of the surface of the transparent conductive layer; the second electrode extends from the top surface of one light emitting unit to the top surface of the adjacent light emitting unit;
wherein, the step of disposing an insulating layer on one side of the substrate comprises:
Forming the insulating layer by multiple sputter deposition and tilting the substrate between adjacent sputter deposition steps to change the deposition direction; wherein, other parameters in each sputtering deposition process are kept unchanged;
Wherein the step of tilting the substrate between adjacent sputter deposition steps comprises:
And enabling the deposition direction of the raw materials of the insulating layer to face the gap between the first electrode and the light-emitting layer, wherein the included angle between the deposition direction and the substrate is 30-60 degrees.
2. The method of manufacturing according to claim 1, wherein the step of etching the transparent conductive layer from one side to form a groove structure comprises:
Etching from the transparent conductive layer until the first semiconductor layer is exposed, and forming the first groove;
Etching from one side of the first semiconductor layer until the buffer layer is exposed, and forming a second groove;
starting etching from the buffer layer until the substrate is exposed, and forming a third groove;
In the step of providing an insulating layer on one side of the substrate, the insulating layer covers the first groove, the second groove, and the third groove.
3. The method of manufacturing according to claim 2, wherein the step of providing an insulating layer on one side of the substrate comprises:
And performing multiple depositions at positions corresponding to the first groove, the second groove and the third groove, so that the thickness of the insulating layer at the positions corresponding to the first groove, the second groove and the third groove is larger than that of the insulating layers at other positions.
4. The method of manufacturing according to claim 1, wherein the step of providing an insulating layer on one side of the substrate further comprises: the substrate is rotated between adjacent sputter deposition steps.
5. The method of claim 4, wherein the deposition time of the multiple sputter depositions is gradually reduced and other parameters in each sputter deposition process remain unchanged; or (b)
The deposition power of the multiple sputtering deposition is gradually reduced, and other parameters in the process of each sputtering deposition are kept unchanged.
6. A light-emitting chip, characterized by being produced by the production method according to any one of claims 1 to 5, comprising:
A substrate;
the buffer layer is arranged on one side of the substrate;
The epitaxial layer is arranged on one side of the buffer layer away from the substrate; the epitaxial layer comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer;
The transparent conductive layer is arranged on one side of the epitaxial layer, which is far away from the substrate; the light-emitting chip is provided with a groove structure formed on one side of the transparent conductive layer, and the groove structure divides the epitaxial layer into a plurality of light-emitting units which are arranged at intervals; the groove structure comprises a first groove formed in one side of the transparent conductive layer, so that the first semiconductor layer is exposed; the groove structure further comprises a second groove formed in one side of the first semiconductor layer, so that the buffer layer is exposed; the groove structure further comprises a third groove formed in one side of the buffer layer, so that the substrate is exposed;
The first electrode is arranged at the bottom of the first groove and is in contact electrical connection with the first semiconductor layer;
An insulating layer arranged on one side of the substrate and covering the buffer layer, the epitaxial layer, the first electrode and the transparent conductive layer; the insulating layer is provided with an opening at the position corresponding to the transparent conductive layer, and a part of the surface of one side of the transparent conductive layer far away from the substrate is exposed;
the second electrode is arranged on one side of the insulating layer away from the substrate and is in contact with the exposed part of the surface of the transparent conductive layer; the second electrode extends from a top surface of one of the light emitting units to a top surface of an adjacent light emitting unit.
7. The light-emitting chip according to claim 6, wherein a thickness of the insulating layer at a position corresponding to the first groove, the second groove, and the third groove is larger than a thickness of the insulating layer at other positions.
8. A display panel comprising the light-emitting chip prepared by the preparation method according to any one of claims 1 to 5 or the display panel comprising the light-emitting chip according to any one of claims 6 to 7.
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| CN105655462B (en) * | 2015-12-31 | 2018-04-17 | 上海交通大学 | High voltage direct current gallium nitride based light emitting diode and its manufacture method |
| CN109560100B (en) * | 2018-11-23 | 2021-04-20 | 江苏新广联科技股份有限公司 | Forward-mounted GaN-based LED micro-display device and manufacturing method thereof |
| CN113745380A (en) * | 2021-08-16 | 2021-12-03 | 泉州三安半导体科技有限公司 | Light emitting diode and lighting or display device |
| CN113571621B (en) * | 2021-08-20 | 2025-06-24 | 江西兆驰半导体有限公司 | A multi-unit light emitting diode and a method for manufacturing the same |
| CN116207202B (en) * | 2023-03-24 | 2025-12-26 | 厦门乾照光电股份有限公司 | A method for fabricating a high-voltage micro light-emitting device |
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| CN107768490A (en) * | 2017-10-26 | 2018-03-06 | 江苏新广联半导体有限公司 | A kind of preparation method for optimizing GaN base LED core piece performance |
| CN112635629A (en) * | 2020-12-30 | 2021-04-09 | 深圳第三代半导体研究院 | Light emitting diode and manufacturing method thereof |
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