CN117054715A - Sampling synchronization method for multiple digital oscilloscopes - Google Patents

Abstract

The invention discloses a sampling synchronization method of a plurality of digital oscilloscopes, which mainly comprises two steps of clock synchronization and trigger synchronization; in the clock synchronization part, a master device crystal oscillator provides a source clock and outputs a synchronous clock signal to a slave device, and the slave device obtains the transmission delay time of the synchronous clock signal through an internal counter and performs phase compensation to realize sampling clock synchronization; in a trigger synchronization part, the master device and the slave device set the same trigger depth, the slave device establishes a trigger system through a FIFO read-write enabling signal and an intermediate control signal FIFO_MID generated by the master device to realize the read-write operation of trigger data, then the FPGA performs delay processing on the extracted acquisition data to compensate the deterministic delay of edge detection and the uncertain delay of a transmission path, and finally performs time sequence adjustment on the slave trigger signal FIFO_MID to complete trigger synchronization; and when the digital oscilloscopes connected in series sequentially complete sampling clock synchronization and trigger synchronization, finally realizing sampling synchronization of a plurality of digital oscilloscopes.

Description

A sampling synchronization method for multiple digital oscilloscopes

Technical field

The invention belongs to the technical field of digital oscilloscopes, and more specifically, relates to a sampling synchronization method for multiple digital oscilloscopes.

Background technique

Digital Storage oscilloscope (DSO) is a high-speed and high-precision measuring instrument that is widely used in various complex electronic measurement fields. Compared with analog oscilloscopes, it has the ability to store waveform data and process data, and triggers The method is richer and the ability to capture complex waveforms is stronger. With the advancement of electronic technology, the size of electronic devices has become larger and larger, and the test environment has become more and more complex. Therefore, in order to improve the adaptability of test instruments to different test environments, the demand for portable and miniaturized digital oscilloscopes is increasing day by day. In order to reduce the size and weight of the equipment, such small digital oscilloscopes are often designed with a small number of channels and are not suitable for test scenarios that require simultaneous measurement of multiple signals. Therefore, in order to improve the testing capabilities of small digital oscilloscopes, it is necessary to design a method that can synchronize multiple digital oscilloscopes so that they can achieve synchronous precision sampling.

Contents of the invention

The purpose of the present invention is to overcome the shortcomings of the existing technology and provide a sampling synchronization method for multiple digital oscilloscopes, through clock synchronization and trigger synchronization, to achieve multi-device data collection synchronization, storage synchronization, and display synchronization to achieve multi-device synchronization. Triggered high-precision indicators.

In order to achieve the above-mentioned object of the invention, the present invention is a sampling synchronization method for multiple digital oscilloscopes, which is characterized in that it includes the following steps:

(1) Assume that there are M digital oscilloscopes in the system that need sampling synchronization, and each digital oscilloscope is connected in series in turn;

(2) Synchronization of sampling clocks between master and slave devices;

(2.1) Use the first digital oscilloscope as the master device and the second digital oscilloscope as the slave device to perform the digital oscilloscope acquisition process;

(2.1.1) The internal crystal oscillator of the main device provides a 10MHz clock source for the clock chip, and at the same time outputs a separate 10MHz synchronous clock signal;

(2.1.2) The internal circuit design of the master and slave devices is the same. Both clock interfaces A and B are designed with bidirectional input and output functions. The 10MHz synchronous clock signal is transmitted to the clock interface B through the FPGA clock programming control circuit in the master device. This interface Connected to the slave device clock interface A through a coaxial line;

(2.1.3), the 10MHz synchronous clock signal is transmitted to the clock circuit of the slave device through the FPGA clock programming control circuit in the slave device. The circuit continuously adjusts the phase of the slave device crystal oscillator to make it equal to the phase of the 10MHz synchronous clock signal. When the adjustment is good The crystal oscillator provides a 10MHz clock source for the slave device clock chip;

(2.1.4). The master and slave devices use their respective clock sources to generate the sampling clock of the ADC through the same clock chip, start data collection, and the analog signal is transmitted to the internal FIFO memory of the FPGA through the ADC through the same path;

(2.2) Carry out the estimation process and calculate the transmission delay time ΔT _clk of the synchronous clock signal from the master device crystal oscillator to the slave device crystal oscillator;

(2.2.1), start the signal generator to generate a 10MHz test signal, use equal-length coaxial cables to connect to the clock interface A of the master device and the clock interface B of the slave device, and enter the FPGA in each device. This transmission Time is recorded as T1 and T2, T1=T2;

(2.2.2). The test signal in the main device is transmitted to the clock circuit through the FPGA clock programming control module. The clock circuit continuously adjusts the phase of the crystal oscillator of the main device to make it equal to the phase of the test signal. This transmission time is recorded as Tclk; the adjusted The crystal oscillator is transmitted to the clock interface A of the slave device according to the transmission path (2.1.2), and finally transmitted to the internal device FPGA. The transmission time is recorded as Tnet;

(2.2.3), start the FPGA internal counter from the device, and use the FPGA internal wiring tool to make the path of the test signal to the counter the same as the transmission path of the clock signal in the FPGA clock programming control circuit. The counter detects that the signal generator outputs the test signal. Then start counting, and end counting after detecting the synchronous clock signal. The counting time is: T=T1+Tclk+Tnet-T2=Tclk+Tnet;

(2.2.4), from the synchronous clock signal transmission path in (2.1.2) and (2.1.3) and the FPGA internal wiring layout in (2.2.3), it can be seen that the synchronous clock signal is transmitted from the master device crystal oscillator to the slave device crystal oscillator. Transmission delay ΔT _clk =Tclk + Tnet, that is, ΔT _clk =T;

(2.3), master-slave sampling clock skew correction;

Let ΔT _{clk_min} be the phase difference between the latest rising edge of the master-slave sampling clock, T is the sampling clock period, and N is the maximum number of complete sampling clock cycles included in ΔT _clk . According to ΔT _clk = ΔT _{clk min} + NT, the ADC sampling of the slave device is delayed. The clock phase difference is until the sampling clock phases of the master and slave devices are consistent, and the sampling clock synchronization of the master and slave devices is completed;

(3) Trigger synchronization of master and slave devices;

(3.1). The trigger source of the master device is set to its own analog channel mode, the trigger source of the slave device is set to the external trigger channel mode, and the master and slave devices set the same trigger depth;

(3.2) Set the trigger conditions of the master device. The FPGA of the master device generates FIFO read and write enable signals that control data storage and reading according to the trigger conditions;

(3.2.1), the master device jointly generates the intermediate control signal FIFO_MID according to the FIFO read and write enable signals. The specific generation process is: when the rising edge of the FIFO write enable signal is detected, the FIFO_MID is pulled high. When the FIFO read enable is detected, After the falling edge of the signal, FIFO_MID is pulled low and remains unchanged at other times;

(3.2.2), FIFO_MID enters the slave device through the connection cable of the master-slave device, and the FPGA of the slave device generates a FIFO read and write enable signal that controls the storage and reading of data from the slave device based on FIFO_MID; when the FPGA of the slave device detects FIFO_MID After the rise of signal, at this time the FIFO is simultaneously writing and reading the collected data;

When the FPGA of the slave device detects the falling edge of FIFO_MID, it pulls the FIFO read enable signal of the slave device low, the FIFO stops reading data, and starts writing the collected data into the post-trigger storage area until the post-trigger storage area is filled with data, and then Control the write enable of the slave device to be low and the read enable to be high, take out the collected data after writing for subsequent processing, and complete the slave device triggering process;

(3.3), trigger point offset correction;

The FPGA of the slave device performs delay processing on the collected data taken out to compensate for the delay in edge detection and transmission path. This delay value is adjusted by the host computer until the trigger point position returns to the ideal trigger position;

(3.4) Adjust the timing of the slave trigger signal FIFO_MID to keep it away from the metastable range of the slave processing clock;

The optimal delay value is determined according to the following steps: delay the slave trigger signal until it is just far away from the metastable range, and the data transmission is from unaligned to aligned as the starting point delay0, and then increase the delay value until the data is exactly from aligned to unaligned as the end point delay1 , then the optimal delay value is (delay0+delay1)/2, and then the FPGA calls the internal IDELAYE2 resource to independently adjust the delay of the slave trigger signal, thus completing the master-slave device trigger synchronization.

(4) After the synchronization of the first and second digital oscilloscopes is completed, set the second digital oscilloscope as the master device and the third digital oscilloscope as the slave device, and then follow steps (2) and (3) to complete the synchronization. Then by analogy, complete the synchronization of all digital oscilloscopes;

(5) After all digital oscilloscopes are synchronized, any digital oscilloscope can be selected as the master device, and the rest of the digital oscilloscopes are slave devices, thus forming a multi-channel data acquisition system.

The invention purpose of the present invention is achieved in this way:

The present invention is a sampling synchronization method for multiple digital oscilloscopes. The method mainly includes two steps: clock synchronization and trigger synchronization; in the clock synchronization part, the master device crystal oscillator provides the source clock and outputs the synchronization clock signal to the slave device, and the slave device passes the internal counter Obtain the transmission delay time of the synchronous clock signal and perform phase compensation to achieve sampling clock synchronization; in the trigger synchronization part, the master and slave devices set the same trigger depth, and the slave device reads and writes the enable signal through the FIFO and the intermediate control signal FIFO_MID generated by the master device Establish a trigger system to realize the reading and writing operations of trigger data. Then the FPGA performs delay processing on the collected data to compensate for the deterministic delay of edge detection and the uncertain delay of the transmission path. Finally, the timing adjustment of the slave trigger signal FIFO_MID is completed. Trigger synchronization. Digital oscilloscopes connected in series complete sampling clock synchronization and trigger synchronization in sequence, and finally achieve sampling synchronization of multiple digital oscilloscopes.

At the same time, the sampling synchronization method of multiple digital oscilloscopes of the present invention also has the following beneficial effects:

(1). By calculating and compensating the transmission delay time, the method of the present invention can accurately realize the clock synchronization and trigger synchronization of the master-slave device and ensure the consistency of the sampling and triggering moments of multiple digital oscilloscopes. Compared with the traditional multi-machine synchronization The method improves synchronization accuracy; higher synchronization accuracy can eliminate sampling errors caused by clock and trigger inconsistencies and provide more accurate and credible data;

(2) The method of the present invention supports the series connection of multiple digital oscilloscopes. Multiple oscilloscopes can be combined according to actual scene requirements to expand the number of channels; it can also expand the application scope of digital oscilloscopes in high-speed multi-signal testing scenarios. It solves the problem of relatively small number of channels, realizes a wider range of signal collection and analysis, and meets the needs of complex experiments or testing;

(3) The multi-machine synchronization function is an important basis for the subsequent development of multi-machine data splicing. The sampling data of multiple machines can be spliced at intervals, and a TIADC-like solution can be used to increase the maximum sampling rate of the digital oscilloscope and further improve the acquisition performance of the digital oscilloscope.

Description of the drawings

Figure 1 is a flow chart of a sampling synchronization method for multiple digital oscilloscopes according to the present invention;

Figure 2 is a schematic diagram of the connection of multiple digital oscilloscopes;

Figure 3 is the clock circuit structure diagram of the slave device;

Figure 4 is a schematic diagram of the clock signal transmission path delay.

Detailed ways

Specific embodiments of the present invention will be described below in conjunction with the accompanying drawings, so that those skilled in the art can better understand the present invention. It is important to note that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

Example

Figure 1 is a flow chart of a sampling synchronization method for multiple digital oscilloscopes according to the present invention.

In this embodiment, as shown in Figure 1, a sampling synchronization method for multiple digital oscilloscopes of the present invention includes the following steps:

S1. Suppose there are M digital oscilloscopes in the system that need sampling synchronization. Each digital oscilloscope is connected in series in turn. The connection method is shown in Figure 2;

S2. The sampling clocks of the master and slave devices are synchronized;

S2.1. Use the first digital oscilloscope as the master device and the second digital oscilloscope as the slave device to perform the digital oscilloscope acquisition process;

S2.1.1. The internal crystal oscillator of the main device provides a 10MHz clock source for the clock chip, and at the same time outputs a separate 10MHz synchronous clock signal;

S2.1.2. The internal circuit design of the master and slave devices is the same. Both clock interfaces A and B are designed with bidirectional input and output functions. The clock circuit design structure diagram and the clock signal transmission path in acquisition mode are shown in Figure 3. The 10MHz synchronous clock signal passes through The FPGA clock programming control circuit in the master device transmits it to the clock interface B, which is connected to the slave device clock interface A through a coaxial line;

S2.1.3, 10MHz synchronous clock signal is transmitted to the clock circuit of the slave device through the FPGA clock programming control circuit in the slave device. The circuit is composed of a voltage optimization circuit, a phase-locked controller and a voltage-controlled oscillator VCO. This structure forms a phase-locked The ring continuously adjusts the phase of the slave device crystal oscillator to make it equal to the phase of the synchronous clock signal. The adjusted crystal oscillator provides a 10MHz clock source for the slave device clock chip;

S2.1.4. The master and slave devices use their respective clock sources to generate the sampling clock of the ADC through the same clock chip, start data collection, and the analog signal is transmitted to the internal FIFO memory of the FPGA through the ADC through the same path;

S2.2. Carry out the estimation process and calculate the transmission delay time ΔT _clk of the synchronized clock signal from the master device crystal oscillator to the slave device crystal oscillator;

S2.2.1. Start the signal generator to generate a 10MHz test signal. Use equal-length coaxial cables to connect to the clock interface A of the master device and the clock interface B of the slave device respectively, and enter the FPGA in each device. The transmission time is recorded For T1 and T2, T1=T2, the signal transmission path delay is shown in Figure 4;

S2.2.2. The test signal in the main device is transmitted to the clock circuit through the FPGA clock programming control module. The clock circuit continuously adjusts the phase of the main device crystal oscillator to make it equal to the phase of the test signal. This transmission time is recorded as Tclk; the adjusted crystal oscillator presses The S2.1.2 transmission path is transmitted to the clock interface A of the slave device, and finally transmitted to the internal device FPGA. The transmission time is recorded as Tnet;

S2.2.3. Start the FPGA internal counter from the device, and use the FPGA internal wiring tool to make the path of the test signal to the counter the same as the transmission path of the clock signal in the FPGA clock programming control circuit. The counter starts after detecting the test signal output by the signal generator. Counting, the counting ends after detecting the synchronous clock signal, the counting time is: T=T1+Tclk+Tnet-T2=Tclk+Tnet;

S2.2.4. From the synchronous clock signal transmission path in S2.1.2 and S2.1.3 and the internal wiring layout of S2.2.3FPGA, it can be seen that the transmission delay of the synchronous clock signal from the master device crystal oscillator to the slave device crystal oscillator ΔT _clk = Tclk + Tnet, That is ΔT _clk =T;

S2.3, master-slave sampling clock skew correction;

The sampling clock phase adjustment can be adjusted inside the clock chip HMC7044 or ADC. HMC7044 provides an analog adjustment solution for the output clock, with an adjustment step of 25ps and a maximum adjustment of 600ps. This design uses the ADC to adjust the clock delay in a coarse adjustment step of 1.13ps, with a maximum adjustment of 289ps, and a fine adjustment of 19fs, with a maximum adjustment of 4.9ps. After comprehensive consideration, an ADC internal adjustment scheme with higher adjustment accuracy is selected;

Let ΔT _{clk_min} be the phase difference between the latest rising edge of the master-slave sampling clock, T is the sampling clock period, and N is the maximum number of complete sampling clock cycles included in ΔT _clk . According to ΔT _clk = ΔT _{clk_min} +NT, the ADC sampling clock of the slave device is delayed. The phase difference is until the sampling clock phases of the master and slave devices are consistent, and the sampling clock synchronization of the master and slave devices is completed;

S3, trigger synchronization of master and slave devices;

S3.1. The trigger source of the master device is set to its own analog channel mode, the trigger source of the slave device is set to the external trigger channel mode, and the master and slave devices set the same trigger depth;

S3.2. Set the trigger condition of the master device. The FPGA of the master device generates a FIFO read and write enable signal that controls data storage and reading according to the trigger condition;

S3.2.1. The master device jointly generates the intermediate control signal FIFO_MID based on the FIFO read and write enable signals. The specific generation process is: when the rising edge of the FIFO write enable signal is detected, the FIFO_MID is pulled high. When the FIFO read enable signal is detected, Pull FIFO_MID low after the falling edge and remain unchanged at other times;

S3.2.2. FIFO_MID enters the slave device through the connection cable of the master-slave device. The FPGA of the slave device generates a FIFO read and write enable signal that controls the data storage and reading of the slave device based on FIFO_MID; when the FPGA of the slave device detects the rise of FIFO_MID After the edge, pull up the FIFO write enable signal of the slave device. At this time, start writing the acquisition data to the FIFO of the slave device until the length of the written data is equal to the pre-trigger depth, and then pull up the FIFO read enable signal of the slave device. At this time, the FIFO performs writing and reading operations of collected data at the same time;

When the FPGA of the slave device detects the falling edge of FIFO_MID, it pulls the FIFO read enable signal of the slave device low, the FIFO stops reading data, and starts writing the collected data into the post-trigger storage area until the post-trigger storage area is filled with data, and then Control the write enable of the slave device to be low and the read enable to be high, take out the collected data after writing for subsequent processing, and complete the slave device triggering process;

S3.3. Trigger point offset correction;

There is a certain delay between the slave control signal and the master control signal, including the definite beat delay caused by edge detection and the uncertain delay caused by the transmission path. Since the clock circuit synchronization has been designed before the triggering process, the sampling points of the master and slave devices have been synchronized, so the delay of the slave trigger signal means that the trigger point will enter the FIFO earlier than the trigger signal, which will lead to a deviation in the trigger points of the master and slave devices. And the trigger point of the slave device deviates from the normal situation, so these delays must be corrected to promote the trigger points of the master and slave devices to be synchronized and appear at the ideal trigger position;

The beat delay is fixed and known. The beat clock is 320MHz. The delay brought by each beat is 1/320MHz=3.125ns. The number of beats is two beats when the master detects one edge and the slave detects one edge. Therefore It is only necessary to collect data from the slave and perform two tapping operations; for the uncertain delay caused by the transmission path, the IDELAYE2 statement integrated within the FPGA is used to adjust the delay of the collected data, and the corresponding port configuration value is modified in the host computer software for dynamic adjustment. Delay value until the trigger point position returns to the ideal trigger position;

S3.4. Adjust the timing of the slave trigger signal FIFO_MID to keep it away from the metastable range of the slave processing clock;

When the total slave trigger signal transmission delay is close to the processing clock cycle, the setup and hold time requirements of the slave processing clock may not be met, resulting in metastability. Once the metastable state is generated, the signal may not take effect until one or even multiple cycles, which will cause the timing of the trigger signal to be confused in the acquisition mode. The FIFO will perform incorrect read and write control, and the trigger point position displayed on the waveform will be the position of the trigger point each time the power is turned on. It will all be different. In order to keep the transmission signal away from the metastable range of the slave processing clock, appropriate timing delay is required;

The optimal delay value is determined according to the following steps: delay the FIFO_MID signal until it is just far away from the metastable range, and the data transmission is from unaligned to aligned as the starting point delay0, and then increase the delay value until the data is exactly from aligned to unaligned as the end point delay1, then The optimal delay value is (delay0+delay1)/2, and then the FPGA calls the internal IDELAYE2 resource to independently adjust the delay of the slave trigger signal, thus completing the master-slave device trigger synchronization.

S4. After the synchronization of the first and second digital oscilloscopes is completed, set the second digital oscilloscope as the master device and the third digital oscilloscope as the slave device. Then follow steps (2) and (3) to complete the synchronization, and then use By analogy, the synchronization of all digital oscilloscopes is completed;

S5. When all digital oscilloscopes are synchronized, select any digital oscilloscope as the master device, and the rest of the digital oscilloscopes are slave devices, thus forming a multi-channel data acquisition system.

Although the illustrative specific embodiments of the present invention are described above to facilitate those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, As long as the various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

Claims (1)

1. A sampling synchronization method for multiple digital oscilloscopes, characterized in that it includes the following steps: (1) Assume that there are M digital oscilloscopes in the system that need sampling synchronization, and each digital oscilloscope is connected in series in turn; (2) Synchronization of sampling clocks between master and slave devices; (2.1) Use the first digital oscilloscope as the master device and the second digital oscilloscope as the slave device to perform the digital oscilloscope acquisition process; (2.1.1) The internal crystal oscillator of the main device provides a 10MHz clock source for the clock chip, and at the same time outputs a separate 10MHz synchronous clock signal; (2.1.2) The internal circuit design of the master and slave devices is the same. Both clock interfaces A and B are designed with bidirectional input and output functions. The 10MHz synchronous clock signal is transmitted to the clock interface B through the FPGA clock programming control circuit in the master device. This interface Connected to the slave device clock interface A through a coaxial line; (2.1.3), the 10MHz synchronous clock signal is transmitted to the clock circuit of the slave device through the FPGA clock programming control circuit in the slave device. The circuit continuously adjusts the phase of the slave device crystal oscillator to make it equal to the phase of the 10MHz synchronous clock signal. When the adjustment is good The crystal oscillator provides a 10MHz clock source for the slave device clock chip; (2.1.4). The master and slave devices use their respective clock sources to generate the sampling clock of the ADC through the same clock chip, start data collection, and the analog signal is transmitted to the internal FIFO memory of the FPGA through the ADC through the same path; (2.2) Carry out the estimation process and calculate the transmission delay time ΔT _clk of the synchronous clock signal from the master device crystal oscillator to the slave device crystal oscillator; (2.2.1), start the signal generator to generate a 10MHz test signal, use equal-length coaxial cables to connect to the clock interface A of the master device and the clock interface B of the slave device, and enter the FPGA in each device. This transmission Time is recorded as T1 and T2, T1=T2; (2.2.2). The test signal in the main device is transmitted to the clock circuit through the FPGA clock programming control module. The clock circuit continuously adjusts the phase of the crystal oscillator of the main device to make it equal to the phase of the test signal. This transmission time is recorded as Tclk; the adjusted The crystal oscillator is transmitted to the clock interface A of the slave device according to the transmission path (2.1.2), and finally transmitted to the internal device FPGA. The transmission time is recorded as Tnet; (2.2.3), start the FPGA internal counter from the device, and use the FPGA internal wiring tool to make the path of the test signal to the counter the same as the transmission path of the clock signal in the FPGA clock programming control circuit. The counter detects that the signal generator outputs the test signal. Then start counting, and end counting after detecting the synchronous clock signal. The counting time is: T=T1+Tclk+Tnet-T2=Tclk+Tnet; (2.2.4), from the synchronous clock signal transmission path in (2.1.2) and (2.1.3) and the FPGA internal wiring layout in (2.2.3), it can be seen that the synchronous clock signal is transmitted from the master device crystal oscillator to the slave device crystal oscillator. Transmission delay ΔT _clk =Tclk + Tnet, that is, ΔT _clk =T; (2.3), master-slave sampling clock skew correction; Let ΔT _{clk_min} be the phase difference between the latest rising edge of the master-slave sampling clock, T is the sampling clock period, and N is the maximum number of complete sampling clock cycles included in ΔT _clk . According to ΔT _clk = ΔT _{clk_min} +NT, the ADC sampling clock of the slave device is delayed. The phase difference is until the sampling clock phases of the master and slave devices are consistent, and the sampling clock synchronization of the master and slave devices is completed; (3) Trigger synchronization of master and slave devices; (3.1). The trigger source of the master device is set to its own analog channel mode, the trigger source of the slave device is set to the external trigger channel mode, and the master and slave devices set the same trigger depth; (3.2) Set the trigger conditions of the master device. The FPGA of the master device generates FIFO read and write enable signals that control data storage and reading according to the trigger conditions; (3.2.1), the master device jointly generates the intermediate control signal FIFO_MID according to the FIFO read and write enable signals. The specific generation process is: when the rising edge of the FIFO write enable signal is detected, the FIFO_MID is pulled high. When the FIFO read enable is detected, After the falling edge of the signal, FIFO_MID is pulled low and remains unchanged at other times; (3.2.2), FIFO_MID enters the slave device through the connection cable of the master-slave device, and the FPGA of the slave device generates a FIFO read and write enable signal that controls the storage and reading of data from the slave device based on FIFO_MID; when the FPGA of the slave device detects FIFO_MID After the rise of signal, at this time the FIFO is simultaneously writing and reading the collected data; When the FPGA of the slave device detects the falling edge of FIFO_MID, it pulls the FIFO read enable signal of the slave device low, the FIFO stops reading data, and starts writing the collected data into the post-trigger storage area until the post-trigger storage area is filled with data, and then Control the write enable of the slave device to be low and the read enable to be high, take out the collected data after writing for subsequent processing, and complete the slave device triggering process; (3.3), trigger point offset correction; The FPGA of the slave device performs delay processing on the collected data taken out to compensate for the delay in edge detection and transmission path. This delay value is adjusted by the host computer until the trigger point position returns to the ideal trigger position; (3.4) Adjust the timing of the slave trigger signal FIFO_MID to keep it away from the metastable range of the slave processing clock; The optimal delay value is determined according to the following steps: delay the FIFO_MID signal until it is just far away from the metastable range, and the data transmission is from unaligned to aligned as the starting point delay0, and then increase the delay value until the data is exactly from aligned to unaligned as the end point delay1, then The optimal delay value is (delay0+delay1)/2, and then the FPGA calls the internal IDELAYE2 resource to independently adjust the delay of the slave trigger signal. At this point, the master-slave device trigger synchronization is completed; (4) After the synchronization of the first and second digital oscilloscopes is completed, set the second digital oscilloscope as the master device and the third digital oscilloscope as the slave device, and then follow steps (2) and (3) to complete the synchronization. Then by analogy, complete the synchronization of all digital oscilloscopes; (5) After all digital oscilloscopes are synchronized, any digital oscilloscope can be selected as the master device, and the rest of the digital oscilloscopes are slave devices, thus forming a multi-channel data acquisition system.