CN117033254A - Memory page access frequency determining method and computing device - Google Patents

Abstract

The embodiment of the application provides a method for determining the access times of a memory page and a computing device, wherein in the method, a storage address of a page attribution table is acquired in response to receiving a first instruction sent by a processor; the first instruction comprises an address of a memory page; the first instruction is used for indicating an address for accessing the memory page; the page attribution table is used for recording the mapping relation between the address of the memory page and the barrel identification; determining a barrel identification corresponding to the address of the memory page based on the memory address of the page attribution table and the address of the memory page; the count value of a counter corresponding to the barrel dividing mark is increased according to a preset stepping value; wherein, the preset step value is 1. The scheme can improve the accuracy of access times statistics of the memory pages.

Description

A method and computing device for determining the number of accesses to a memory page

Technical field

Embodiments of the present application relate to the field of server technology, and in particular to a method for determining the number of accesses to a memory page and a computing device.

Background technique

Based on the different performance of different storage media, users expect to put the data in frequently accessed memory pages (hot pages) in the memory into storage media with better performance. To do this, the number of accesses to each memory page in memory needs to be determined.

In the process of determining the number of accesses to a memory page, the related technology regards a continuous device physical address (DPA) area as a bucket, and determines the number of accesses to the memory page by determining the number of accesses to the bucket. .

However, in related technologies, when the hot data (highly accessed data) of the same task is dispersed into different buckets, and each bucket includes multiple memory pages, it will cause the multiple buckets to include The statistics of the number of accesses to each memory page will be affected by hot data, which leads to the problem of low accuracy in the method of determining the number of accesses to a memory page in related technologies.

Contents of the invention

Embodiments of the present application provide a method and computing device for determining the number of access times of a memory page. Can improve the accuracy of determining the number of accesses to a memory page.

In the first aspect, embodiments of the present application provide a method for determining the number of accesses to a memory page. The method includes:

In response to receiving the first instruction sent by the processor, obtain the storage address of the page ownership table; wherein the first instruction includes the address of the memory page; the first instruction is used to indicate access to the address of the memory page; the page ownership table is used to record the memory The mapping relationship between the page address and the bucket identifier;

Based on the storage address of the page ownership table and the address of the memory page, determine the bucket identifier corresponding to the address of the memory page;

The count value of the counter corresponding to the bucket identification is incremented according to a preset step value; wherein, the preset step value is 1.

A page ownership table is provided, which describes the mapping relationship between the physical address of the memory page and the bucket identifier. When receiving the first instruction, the memory access controller can find the bucket identifier corresponding to the address of the memory page from the page ownership table, and increment the count value of the counter corresponding to the bucket identifier according to a preset step value. Through the above-mentioned method of flexibly defining the mapping relationship of bucket identifiers by software, memory buckets and memory pages have a flexible mapping relationship. Hot and cold data can be placed in different buckets, and the size of the buckets can be divided non-uniformly, ensuring Accuracy of memory page access count determination.

In one implementation, the page ownership table is a multi-level page table;

The multi-level page table includes the first page ownership table, the second page ownership table and the third page ownership table;

Among them, the first page ownership table is the first-level page table; the second page ownership table is the intermediate-level page table; the third page ownership table is the last-level page table; the second page ownership table is one-level or multi-level page tables;

Each page table entry in the first page ownership table and the second page ownership table is used to store the storage address of the next-level page ownership table; each page table entry in the third page ownership table is used to store the bucket identification.

By setting each page table entry in the last-level page ownership table to include a bucket identifier, and each page table entry in the first-level page ownership table and intermediate-level page ownership table to include the storage address of the next-level page ownership table, you can The page ownership table is stored discretely, which avoids the need for continuous memory space to store all the contents of the page ownership table and improves memory space usage.

In one implementation, the storage address of the page ownership table is the storage address of the first page ownership table;

Based on the storage address of the page ownership table and the address of the memory page, determine the bucket identifier corresponding to the address of the memory page, including:

Based on the storage address of the page ownership table and the first K bits of the address of the memory page, determine the storage address of the second page ownership table in the first page ownership table;

Based on the storage address of the second page ownership table and the middle M bits in the memory page address, determine the storage address of the third page ownership table in the second page ownership table;

Based on the storage address of the third page ownership table and the last N bits of the memory page address, the bucket identifier corresponding to the address of the memory page is determined in the third page ownership table.

Based on the storage address of the page ownership table and the address of the memory page, the bucket identifier corresponding to the address of the memory page can be searched step by step.

In one implementation, the page ownership table is stored in memory.

By storing the page ownership table that takes up a large amount of space in the memory, the storage pressure on the memory access controller is reduced.

In one implementation, after determining the bucket identifier corresponding to the address of the memory page, the method further includes:

Store the bucket identifier corresponding to the address of the memory page in the first memory.

After determining the bucket identifier corresponding to the storage address of the memory page, the storage address of the memory page and its corresponding bucket identifier are stored in the first memory of the memory access controller, so that the address of the memory page can be directly determined subsequently. The corresponding bucket identification improves the speed of obtaining the bucket identification.

In one implementation, before obtaining the storage address of the page ownership table, the method further includes:

Determine whether the first memory stores the bucket identifier corresponding to the address of the memory page;

When the first memory stores the bucket identifier corresponding to the address of the memory page, the count value of the counter corresponding to the bucket identifier is incremented according to a preset step value, where the preset step value is 1.

When receiving the first instruction, it can be identified whether the first memory of the memory access controller stores the bucket identifier corresponding to the address of the memory page, so as to determine whether the bucket identifier can be quickly obtained. On the basis of identifying the bucket identifier corresponding to the address of the memory page stored in the first memory, the bucket identifier can be obtained directly, which improves the acquisition speed of the bucket identifier, thereby increasing the number of accesses to the memory page based on the first instruction. The speed is increased by 1.

In one implementation, the method also includes:

When the first memory does not store the bucket identification corresponding to the address of the memory page, obtain the storage address of the page ownership table.

When it is recognized that the first memory of the memory access controller does not store the bucket identifier corresponding to the address of the memory page, the page ownership table can be searched to determine the bucket identifier corresponding to the memory page.

After incrementing the count value of the counter corresponding to the bucket identifier according to the preset step value, the method also includes:

The count value of the counter corresponding to the bucket identification is stored in the second memory.

The count value of the counter corresponding to the bucket identifier (the number of accesses to the memory page corresponding to the bucket identifier) can be safely stored by storing the count value of the counter corresponding to the bucket identifier in the second memory.

In one implementation, the method also includes:

In response to receiving the second instruction sent by the processor, send the count value of the counter corresponding to the bucket identification to the processor;

The second instruction is used to indicate the number of accesses to obtain the memory page.

In response to receiving the second instruction sent by the processor, the count value of the counter corresponding to the bucket identifier is sent to the processor, so that the processor counts hot and cold pages based on the count value of the counter corresponding to the bucket identifier.

In a second aspect, embodiments of the present application provide a memory access controller, including:

A transceiver module, configured to obtain the storage address of the page ownership table in response to receiving the first instruction sent by the processor; wherein the first instruction includes the address of the memory page; the first instruction is used to indicate access to the address of the memory page; the page ownership The table is used to record the mapping relationship between the address of the memory page and the bucket identifier;

The processing module is used to determine the bucket identification corresponding to the address of the memory page based on the storage address of the page ownership table and the address of the memory page;

The processing module is also used to increment the count value of the counter corresponding to the bucket identification according to a preset step value; wherein the preset step value is 1.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In one implementation, the page ownership table is a multi-level page table;

The multi-level page table includes the first page ownership table, the second page ownership table and the third page ownership table;

Among them, the first page ownership table is the first-level page table; the second page ownership table is the intermediate-level page table; the third page ownership table is the last-level page table; the second page ownership table is one-level or multi-level page tables;

Each page table entry in the first page ownership table and the second page ownership table is used to store the storage address of the next-level page ownership table; each page table entry in the third page ownership table is used to store the bucket identification.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In one implementation, the storage address of the page ownership table is the storage address of the first page ownership table; the processing module is specifically used for:

Based on the storage address of the page ownership table and the first K bits of the address of the memory page, determine the storage address of the second page ownership table in the first page ownership table;

Based on the storage address of the second page ownership table and the middle M bits in the memory address, determine the storage address of the third page ownership table in the second page ownership table;

Based on the storage address of the third page ownership table and the last N bits of the memory address, the bucket identifier corresponding to the address of the memory page is determined in the third page ownership table.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In one implementation, the page ownership table is stored in memory.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In one implementation, after determining the bucket identifier corresponding to the address of the memory page, the processing module is also used to:

Store the bucket identifier corresponding to the address of the memory page in the first memory.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In one implementation,

Before obtaining the storage address of the page ownership table, the processing module is also used to:

Determine whether the first memory stores the bucket identifier corresponding to the address of the memory page;

When the first memory stores the bucket identifier corresponding to the address of the memory page, the count value of the counter corresponding to the bucket identifier is incremented according to a preset step value, where the preset step value is 1.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In one implementation, the processing module is also used to:

When the first memory does not store the bucket identification corresponding to the address of the memory page, obtain the storage address of the page ownership table.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In one implementation, after incrementing the count value of the counter corresponding to the bucket identifier according to a preset step value, the processing module is also used to:

The count value of the counter corresponding to the bucket identification is stored in the second memory.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In one implementation, the transceiver module is also used to:

In response to receiving the second instruction sent by the processor, send the count value of the counter corresponding to the bucket identification to the processor;

The second instruction is used to indicate the number of accesses to obtain the memory page.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In a third aspect, embodiments of the present application also provide a computing device. The computing device includes: a memory, a memory access controller and a processor; wherein the memory and the memory access controller are electrically connected; the memory access controller and the processor are electrically connected;

The memory access controller is configured to perform the method for determining the number of access times of the memory page in the first aspect.

The memory access controller in the computing device provided by this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

Description of the drawings

In order to more clearly explain the technical solutions in the embodiments of the present application or related technologies, a brief introduction will be made below to the drawings that need to be used in the description of the embodiments or related technologies. Obviously, the drawings in the following description are of the present invention. For some embodiments of the application, those of ordinary skill in the art can also obtain other drawings based on these drawings without exerting any creative effort.

Figure 1a is a schematic diagram of a scenario of a method for determining the number of access times of a memory page applicable to related technologies;

Figure 1b is a schematic diagram of a scenario of another method for determining the number of access times of a memory page applicable to related technologies;

Figure 2 is a system architecture diagram of a computing device provided by an embodiment of the present application;

Figure 3 is a schematic flow chart of Embodiment 1 of a method for determining the number of accesses to a memory page provided by an embodiment of the present application;

Figure 4a is a schematic structural diagram of page table entries in page tables at all levels in a page ownership table provided by an embodiment of the present application;

Figure 4b is a schematic diagram of the principle of searching for bucket identification provided by an embodiment of the present application;

Figure 4c is a schematic structural diagram of page table entries in page tables at all levels in another page ownership table provided by an embodiment of the present application;

Figure 5 is a schematic flowchart of Embodiment 3 of a method for determining the number of accesses to a memory page provided by an embodiment of the present application;

Figure 6 is a schematic flowchart of Embodiment 4 of a method for determining the number of accesses to a memory page provided by an embodiment of the present application;

Figure 7 is a schematic diagram of a scenario for building a page attribution table applicable to the embodiment of the present application;

Figure 8 is a schematic structural diagram of a memory access controller provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments These are part of the embodiments of this application, but not all of them. Based on the embodiments in this application, all other embodiments made by those of ordinary skill in the art based on the inspiration of this embodiment fall within the scope of protection of this application.

The terms "first", "second", "third", "fourth", etc. (if present) in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used for Describe a specific order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances so that the embodiments of the application described herein can be practiced in sequences other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus that encompasses a series of steps or units and need not be limited to those explicitly listed. Those steps or elements may instead include other steps or elements not expressly listed or inherent to the process, method, product or apparatus.

Figure 1a is a schematic diagram of a scenario of a method for determining the number of accesses to a memory page that is applicable to related technologies. Figure la shows three buckets (Bucket 1, Bucket 2 and Bucket 3 respectively) and three counters (Bucket 1 counter, Bucket 2 counter and Bucket 3 counter). Each bucket (contiguous area of physical addresses) consists of four memory pages. A, B, C, and D represent four different tasks.

Among them, the four memory pages of bucket 1 store the data of task A, data of task B, data of task C and data of task D respectively. The four memory pages of bucket 2 store the data of task A, the data of task B, the data of task C and the data of task D respectively; the four memory pages of bucket 3 store the data of task A and task B respectively. data, data of task C and data of task D.

When the data of task A is hot data, and the data of task B, task C and data of task D are all cold data, since bucket 1, bucket 2 and bucket 3 all include the data of task A, Therefore, bucket 1, bucket 2, and bucket 3 will all be identified as containing hot data. That is to say, the determination of the number of access times for each memory page included in these multiple buckets will be affected by hot data, which leads to the problem of low accuracy in the method of determining the number of access times for memory pages in related technologies. At the same time, it affects the accuracy of determining hot and cold data.

Figure 1b is a schematic diagram of a scenario of another method for determining the number of access times of a memory page applicable to the related technology. Figure 1b shows three buckets (Bucket 4, Bucket 5 and Bucket 6 respectively) and three counters (Bucket 4 counter, Bucket 5 counter and Bucket 6 counter). Each bucket (contiguous physical address area) can be evenly divided into four memory pages. E, F, G, and H represent four different tasks.

Among them, among the four memory pages in bucket 4, three memory pages store the data of the E task, and one memory page stores the data of the H task. Among the four memory pages in bucket 5, two memory pages store the data of the F task, one memory page stores the data of the G task, and one memory page stores the data of the H task. Among the four memory pages in bucket 6, four memory pages store the data of the H task.

When the data of task H is hot data, and the data of task E, task F and data of task G are cold data, since bucket 4, bucket 5 and bucket 6 all include the data of H task, the data of bucket 4, bucket 5 and bucket 6 all include the data of task H. Bucket 4, bucket 5 and bucket 6 will all be identified as containing hot data. In other words, the determination of the number of accesses for each memory page included in these multiple buckets will be affected by hot data.

In short, in the related art, a continuous device physical address area is regarded as a bucket, and the memory space occupied by the continuous device physical address area corresponding to each bucket is the same size. This method divides the buckets evenly, and divides the buckets evenly. A continuous device physical address is regarded as a bucketing method, which has the problem of low accuracy in determining the number of memory page accesses.

In addition, it should be noted that the hardware (such as the memory access controller) lacks sufficient heuristic information (bucketing logic method) to perform non-uniform bucketing. The hardware can only perform non-uniform bucketing based on the information transferred by the software. It should be noted that the software can also tell the hardware how to perform non-uniform bucketing through multiple interactions with the hardware. For example, the software can inform the hardware to divide the first device physical address area (such as address segment A) into buckets according to the size of 4KB. For the physical address area of the second device (such as address segment B), buckets are divided into buckets according to the size of 8KB. However, when the physical address area (address segment) of the device is fragmented, multiple interactions between software and hardware are required to complete the bucketing process, which is cumbersome.

Based on the above technical problems, embodiments of the present application provide a method for determining the number of accesses to a memory page. In this method, a page ownership table is provided that records the mapping relationship between the address of the memory page and the bucket identifier. When receiving the first instruction including the address of the memory page, the memory access controller can determine the bucket identifier corresponding to the address of the memory page based on the storage address of the page ownership table and the address of the memory page, and assign the bucket identifier corresponding to the bucket identifier The count value of the counter increases according to the preset step value. Through the above-mentioned method of flexibly defining the bucket number mapping relationship by software, the buckets and memory pages have a flexible mapping relationship. Hot and cold data can be placed in different buckets, and the size of the buckets can be divided non-uniformly, ensuring the memory Accuracy of determining the number of page visits.

The following is a detailed description of the method for determining the number of access times of a memory page in the embodiment of the present application.

Figure 2 is a system architecture diagram of a computing device provided by an embodiment of the present application.

As shown in FIG. 2 , the computing device 400 includes: a memory access controller 200 and a processor 100 and a memory 300 that are electrically connected to the memory access controller 200 respectively.

Among them, the memory access controller 200 is used to control the memory 300 and is responsible for data exchange between the memory 300 and the processor 100 .

Processor 100: It can be a central processing unit (CPU for short), an out-of-band controller, or other devices with specific processing capabilities.

Memory access controller 200: The memory access controller 200 can be a memory controller, a computer express link (CXL) memory access controller, or other types of memory controllers that can control memory and be responsible for memory and Processor controller for data exchange.

Memory 300: also called internal memory. The memory 300 is an important component of the computing device 400. It is used to temporarily store operation data in the processor and data exchanged between the processor and external memory. It is a bridge for communication between the external memory (or auxiliary memory) and the processor. The memory 300 can be a CXL memory or a dynamic random access memory (dynamic random access memory, DRAM for short).

It should be noted that one or more software can be run on the processor 100. For example, the management software 101, application software 103 and application software 104 can be run on the processor 100. The processor 100 may also include a third memory 102 for storing the page ownership table. Among them, the page ownership table describes the mapping relationship between the address of the memory page and the bucket identifier.

The memory access controller 200 may include a memory access interface 201, a setting interface 202, and a query interface 203. The above three interfaces can be a multiplexed interface, or they can be multiple independent interfaces.

The memory access controller 200 may also include a first memory 205 .

In an implementable manner, the first memory 205 may be used to store a mapping relationship table between addresses of memory pages and their corresponding bucket identifiers.

In an implementable manner, the first memory 205 can also be used to store the storage address of the page ownership table.

In an implementable manner, there may be two first memories 205, wherein one first memory 205 stores the mapping relationship table of the address of the memory page and its corresponding bucket identification; for example, it is used to store the memory page. The memory of the mapping relationship table of the address of the page and its corresponding bucket identification can be a memory such as a flash memory; the other first memory 205 is used to store the storage address of the page ownership table; for example, it is used to store the page ownership table. The address memory can be a register.

The memory access controller 200 may include a second memory 206, and the second memory 206 may store the count value of the counter corresponding to the bucket identification. It should be noted that the first memory 205 and the second memory 206 may be the same memory or different memories.

The mapping relationship search logic 204 (program) can be run on the memory access controller 200.

The memory access controller 200 can also run a counter 207 (program) (each bucket identifier can correspond to a counter). The timer's count value can be incremented according to a preset step value.

The memory access controller 200 may obtain the page ownership table and the storage address of the page ownership table sent by the processor 100 . The memory access controller 200 may store the storage address of the page ownership table in the first memory 205 and store the page ownership table in the memory 300 . Specifically, the management software 101 on the processor 100 can send the storage address of the page ownership table and the page ownership table to the memory access controller 200 through the setting interface 202 . The memory access controller 200 may store the storage address of the page ownership table in the first memory 205 . The memory access controller 200 may store the page ownership table into the memory 300 .

The memory access controller 200 may respond to the first instruction sent by the host 100, search for the bucket identifier corresponding to the address of the memory page in the first instruction from the page ownership table stored in the memory 100, and match the bucket identifier to The count value of the counter increases according to the preset step value. Specifically, when the application software 103 or the application software 104 of the processor 100 accesses the memory 300 through the memory access interface 201 of the memory access controller 200, the mapping relationship search logic 204 is triggered to search for the page ownership table recorded in the first memory 205. Storage address, and then based on the storage address of the page ownership table and the address of the memory page, determine the bucket ID corresponding to the address of the memory page, and increment the count value of the counter corresponding to the bucket ID according to the preset step value.

The memory access controller 200 may respond to the second instruction sent by the processor 100 and send the count value of the counter corresponding to each bucket identification to the processor 100, so that the processor 100 can use the counter value corresponding to each bucket identification according to the count value of the counter. The count value counts hot and cold pages. Specifically, the management software 101 on the processor 100 can obtain the count value of the counter corresponding to the bucket identification stored in the second memory 206 through the query interface 203 of the memory access controller 200 .

It should be noted that the processor 100, the memory access controller 200 and the memory 300 shown in Figure 2 belong to the same computing device. The processor 100, the memory access controller 200 and the memory 300 may also belong to different computing devices.

In an implementation manner, when the processor 100, the memory access controller 200 and the memory 300 belong to the same computing device, the memory access controller 200 and the memory 300 can be integrated into the same memory device, for example, they are integrated into the same computer. on a board.

In an implementation manner, when the processor 100, the memory access controller 200 and the memory 300 belong to the same computing device, the processor 100 and the memory access controller 200 can be integrated together; for example, the memory access controller 200 can As a memory controller, memory controller 200 may be integrated into processor 100 .

In an implementable manner, when the processor 100, the memory access controller 200 and the memory 300 belong to different computing devices, the processor 100 can belong to the first computing device, and the memory access controller 200 and the memory 300 can belong to the first computing device. In the second computing device (for example, the second computing device may be a CXL device), the memory access controller 200 and the memory 300 may be integrated in the same memory device. The first computing device and the second computing device may be connected by a cable.

It should also be noted that the computing device 400 may be a server or a terminal device (such as a computer, etc.).

It should also be noted that FIG. 2 is only a system architecture diagram of a computing device provided by an embodiment of the present application. The embodiment of the present application does not limit the actual form of various devices included in FIG. 2, nor does it The interaction mode between them is limited, and in the application of the solution, it can be set according to actual needs.

Below, the technical solution of the present application will be described in detail through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

FIG. 3 is a schematic flowchart of Embodiment 1 of a method for determining the number of accesses to a memory page provided by an embodiment of the present application.

Referring to Figure 3, the method specifically includes the following steps:

S301: In response to receiving the first instruction sent by the processor, obtain the storage address of the page ownership table.

In this embodiment, the memory access controller may obtain the storage address of the page ownership table in response to receiving the first instruction sent by the processor.

Among them, the page ownership table is used to record the mapping relationship between the address of the memory page and the bucket number.

The first instruction includes the address of the memory, and the first instruction is used to indicate the address of accessing the memory page. It should be noted that since the address of the memory includes the address of the memory page, the first instruction includes the address of the memory page.

In addition, when receiving the first instruction sent by the memory, the memory access controller can also read the data in the memory page from the memory based on the address of the memory page in the first instruction, and feed back the data in the memory page to processor.

It should be noted that the access controller can obtain the page ownership table sent by the processor in advance and store the page ownership table in the memory. The memory access controller may also obtain in advance the storage address of the page ownership table sent by the processor, and store the storage address of the page ownership table in the first memory of the memory access controller.

It should also be noted that the processor can flexibly construct the page ownership table based on user needs. Among them, the page ownership table describes the mapping relationship between the address of the memory page and the bucket identifier. It should be noted that the size of the memory space occupied by the buckets corresponding to each bucket ID can be the same or different.

Through the above-mentioned method of flexibly defining the bucket number mapping relationship by software, memory buckets and memory pages have a flexible mapping relationship. Hot and cold data can be placed in different buckets, and the size of the buckets can be divided non-uniformly, ensuring Accuracy of memory page access count determination.

For example, the processor can identify the address of the memory page corresponding to the data of each task based on user requirements (the requirement that all the data in the memory pages corresponding to each bucket identification be data of the same task) to divide each The bucket ID corresponding to the address of the memory page corresponding to the data of each task. During the partitioning process, the addresses of multiple memory pages corresponding to the data of each task are mapped to the same bucket ID, or to different bucket IDs. Map the addresses of memory pages corresponding to data of different tasks to different bucket identifiers. In other words, the data of the same task can be stored in the same bucket or in different buckets. The data stored in the same bucket is the data of the same task. In one implementation, the processor can construct a page ownership table based on the mapping relationship between the address of the memory page input by the user and the bucket identifier. By setting the page ownership table in which the same bucket only includes data for the same task, hot and cold data can be placed in different buckets, ensuring the accuracy of determining the number of memory page accesses, thereby improving the memory-based performance of subsequent processors. The number of visits to the page, and the accuracy of counting hot and cold pages.

S302: Based on the storage address of the page ownership table and the address of the memory page, determine the bucket identifier corresponding to the address of the memory page.

In this embodiment, the memory access controller may, after obtaining the storage address of the page ownership table and the address of the memory page, determine the bucket identifier corresponding to the address of the memory page based on the storage address of the page ownership table and the address of the memory page. That is to say, the memory access controller can search the page ownership table stored in the memory based on the storage address of the page ownership table and the address of the memory page to determine the bucket identifier corresponding to the address of the memory page. For example, the bucket identifier may be a bucket number. This embodiment does not limit the specific form of the bucket identification.

It should be noted that, in an implementation manner, the page ownership table can also be stored in the memory access controller. In the case where the memory access controller stores the page ownership table, the memory access controller can respond to the first instruction sent by the processor and directly search for the segment corresponding to the address of the memory page from the page ownership table stored by the memory access controller. Bucket ID, and the count value of the counter corresponding to the bucket ID is incremented according to the preset step value. It should also be noted that the memory access controller can obtain the page ownership table sent by the processor before searching for the bucket identification corresponding to the address of the memory page in the first instruction from the page ownership table, and convert the page ownership table Stored in the first memory of the memory access controller.

S303: Increment the count value of the counter corresponding to the bucket identification according to the preset step value.

In this embodiment, after determining the bucket identifier corresponding to the address of the memory page, the memory access controller may increment the count value of the counter corresponding to the bucket identifier according to a preset step value. Among them, the default step value is 1.

In other words, the memory access controller can increase the number of accesses corresponding to the bucket ID by 1.

In this embodiment, a page ownership table is provided, which describes the mapping relationship between the address of the memory page and the bucket identifier. The memory access controller can obtain the storage address of the page ownership table when receiving the first instruction including the address of the memory page, and determine the bucket identification corresponding to the address of the memory page based on the storage address of the page ownership table and the address of the memory page. , and increment the count value of the counter corresponding to the bucket identifier according to the preset step value to increase the number of accesses to the memory page by 1. Through the above-mentioned method of flexibly defining the mapping relationship between bucket numbers by software, memory buckets and memory pages have a flexible mapping relationship. Hot and cold data can be placed in different buckets, and the size of the buckets can be divided non-uniformly, thereby ensuring This improves the accuracy of identifying hot and cold data, thereby improving the accuracy of subsequent processor statistics on hot and cold pages.

The following is a detailed description of the process in which the memory access controller determines the bucket identifier corresponding to the address of the memory page based on the storage address of the page ownership table and the address of the memory page through the second method embodiment.

In this embodiment, the page ownership table may be a multi-level page table. The page ownership table is stored in memory.

When the page ownership table is a multi-level page table, the multi-level page table includes a first page ownership table, a second page ownership table and a third page ownership table. Among them, the first page ownership table is a first-level page table; the second page ownership table is an intermediate-level page table; the third page ownership table is a last-level page table; and the second page ownership table is one-level or multi-level page tables.

Exemplarily, FIG. 4a is a schematic structural diagram of page table entries in page tables at each level in a page ownership table provided by an embodiment of the present application. Each page table entry in the first page ownership table and the second page ownership table is used to store the storage address of the next-level page ownership table; each page table entry in the third page ownership table is used to store the bucket identification.

In the process of determining the bucket ID corresponding to the address of the memory page based on the storage address of the page ownership table and the address of the memory page, the memory access controller:

After obtaining the storage address of the page ownership table (the storage address of the first page ownership table), the memory access controller obtains the first K of the storage address of the page ownership table (the storage address of the first page ownership table) and the address of the memory page. bit to determine the storage address of the second page ownership table in the first page ownership table. That is to say, the memory access controller can determine a certain page table item in the first page ownership table as the first target page table item based on the storage address of the first page ownership table and the first K bits of the address of the memory page. And the storage address of the next-level page ownership table stored in the first target page table entry is used as the storage address of the second page ownership table.

The memory access controller determines the storage address of the third page ownership table in the second page ownership table based on the storage address of the second page ownership table and the middle M bits in the memory address. That is to say, the memory access controller can determine that a certain page table entry in the second page ownership table is the second target page table entry based on the storage address of the second page ownership table and the middle M bits of the address of the memory page. And the storage address of the next-level page ownership table stored in the second target page table entry is used as the storage address of the third page ownership table.

The memory access controller determines the bucket identifier corresponding to the address of the memory page in the third page ownership table based on the storage address of the third page ownership table and the last N bits of the memory address. That is to say, the memory access controller can determine that a certain page table entry in the third page ownership table is the third target page table entry based on the storage address of the third page ownership table and the last N bits of the address of the memory page. And the bucket identification stored in the third target page table entry is used as the bucket identification corresponding to the address of the memory page.

Figure 4b is a schematic diagram of the principle of searching for bucket identifiers provided by an embodiment of the present application. As shown in Figure 4b, for the address of the first memory page and the address of the second memory page, the memory access controller can determine the bucket identifier corresponding to the address of the first memory page, and determine the bucket identifier corresponding to the address of the second memory page. Bucket ID.

Specifically, when the page ownership table is a three-level page table, in the process of determining the bucket identification corresponding to the address of the first memory page:

The memory access controller may determine which of the plurality of page table entries in the first page ownership table is based on the storage address of the page ownership table (the storage address of the first page ownership table) and the first K bits of the address of the first memory page. The fourth page table entry is the first target page table entry. The memory access controller may determine the storage address of the next-level page ownership table in the first target page table entry as the storage address of the second page ownership table. The memory access controller may determine, based on the middle M bits of the storage address of the second page ownership table and the address of the first memory page, that the second page table entry among the plurality of page table entries in the second page ownership table is the second page table entry. Target page table entry. The memory access controller may determine the storage address of the next-level page ownership table in the second target page table entry as the storage address of the third page ownership table. The memory access controller may determine, based on the storage address of the third page ownership table and the last N bits of the address of the first memory page, that the third page table entry among the plurality of page table entries in the third page ownership table is the third page table entry. Target page table entry. The memory access controller may determine the bucket identifier (bucket identifier 1) stored in the third target page table entry as the bucket identifier corresponding to the address of the first memory page.

When the page ownership table is a three-level page table, in the process of determining the bucket identifier corresponding to the address of the second memory page:

The memory access controller may determine which of the plurality of page table entries in the first page ownership table is based on the storage address of the page ownership table (the storage address of the first page ownership table) and the first K bits of the address of the second memory page. The fourth page table entry is the first target page table entry. The memory access controller may determine the storage address of the next-level page ownership table in the first target page table entry as the storage address of the second page ownership table. The memory access controller may determine, based on the middle M bits of the storage address of the second page ownership table and the address of the second memory page, that the fourth page table entry among the plurality of page table entries in the second page ownership table is the second page table entry. Target page table entry. The memory access controller may determine the storage address of the next-level page ownership table in the second target page table entry as the storage address of the third page ownership table. The memory access controller may determine, based on the storage address of the third page ownership table and the last N bits of the address of the second memory page, that the fifth page table entry among the plurality of page table entries in the third page ownership table is the third page table entry. Target page table entry. The memory access controller may determine the bucket identifier (bucket identifier 4) stored in the third target page table entry as the bucket identifier corresponding to the address of the first memory page. In one implementation, when the page ownership table is a multi-level page table, each page table entry of the first page ownership table and the second page ownership table is used to store the storage address of the next level page ownership table, And the bucket identification corresponding to the next-level page attribution table.

Figure 4c is a schematic structural diagram of page table entries in page tables at all levels in another page ownership table provided by an embodiment of the present application. As shown in Figure 4c, when the page ownership table is a three-level page table, each page table entry in the first page ownership table includes the storage address of the next-level page ownership table (the second page ownership table) and the corresponding Bucket ID. Each page table entry in the second page ownership table includes the storage address of the next-level page ownership table (the third page ownership table) and the corresponding bucket identifier. Each page table entry in the third page ownership table includes a bucket identifier.

In the process of finding the bucket ID corresponding to the address of the memory page:

Each page table entry based on the first page ownership table (first-level page ownership table) includes the storage address of the next-level page ownership table and the corresponding bucket identifier. The memory access controller can be directly based on the storage address of the page ownership table. (the storage address of the first page ownership table), and the first K bits of the address of the memory page, determine the bucket identifier corresponding to the address of the memory page in the first page ownership table.

It should be noted that when all page table entries in a page ownership table of a certain level correspond to the same bucket identifier, they can be directly registered in the page table entries of the page ownership table of the upper level corresponding to the page ownership table. This bucket identification eliminates the need for the memory to store the page ownership table of this level, thus achieving the effect of saving memory.

In addition, it should be noted that since it is easy to distinguish the bucket identifier and the storage address of the next-level page ownership table, the storage address of the next-level page ownership table included in a page table entry can be reused with the same bucket identifier. memory unit, thereby further saving the memory space required to store the page ownership table. For example, the storage address of the next-level page ownership table included in a page table entry may be stored in the same page (Page) as the bucket identifier, where the page (Page) represents the smallest read-write unit in the memory.

In this embodiment, the page ownership table that occupies a larger space is stored in the memory, and the storage address of the page ownership table that occupies a smaller space is stored in the memory access controller. The memory access controller can read the storage address of the page ownership table stored by the memory access controller and the address of the memory page, and find the bucket identifier corresponding to the address of the memory page from the page ownership table. The embodiment of the present application reduces the storage pressure of the memory access controller by storing the storage address of the page ownership table in the memory access controller and storing the page ownership table in a memory with a larger storage space.

FIG. 5 is a schematic flowchart of Embodiment 3 of a method for determining the number of accesses to a memory page provided by an embodiment of the present application.

Referring to Figure 5, the method specifically includes the following steps:

S501: In response to receiving the first instruction sent by the processor, determine whether the first memory stores the bucket identification corresponding to the address of the memory page.

In this embodiment, in response to receiving the first instruction sent by the processor, the memory access controller may determine whether the first memory stores the bucket identification corresponding to the address of the memory page.

When the memory access controller determines that the first memory does not store the bucket identifier corresponding to the address of the memory page, S502 is executed; when the memory access controller determines that the first memory stores the bucket identifier corresponding to the address of the memory page, Execute S506.

S502: Obtain the storage address of the page ownership table.

In this embodiment, when the memory access controller determines that the first memory does not store the bucket identifier corresponding to the address of the memory page, it may obtain the storage address of the page ownership table.

S503: Based on the storage address of the page ownership table and the address of the memory page, determine the bucket identifier corresponding to the address of the memory page.

In this embodiment, after obtaining the storage address of the page ownership table, the memory access controller can determine the bucket identifier corresponding to the address of the memory page based on the storage address of the page ownership table and the address of the memory page. Its specific execution is the same as S302 and will not be described again here.

S504: Increment the count value of the counter corresponding to the bucket identification according to the preset step value.

In this embodiment, the memory access controller may increment the count value of the counter corresponding to the bucket identifier according to a preset step value. Among them, the default step value is 1. Its specific execution is the same as S303 and will not be described again here.

S505: Store the address of the memory page and its corresponding bucket identifier in the first memory.

In this embodiment, the memory access controller may, after determining the bucket identifier corresponding to the address of the memory page, store the address of the memory page and its corresponding bucket identifier into the first memory of the memory access controller, For example, the address of the memory page and its corresponding bucket identifier are stored in the mapping table, so that the bucket identifier corresponding to the memory page can be quickly obtained later.

It should be noted that the embodiment of the present application does not limit the execution order of S504 and S505. The memory access controller can execute S504 first, and then execute S505; the memory access controller can also execute S505 first, and then execute S504.

S506: Increment the count value of the counter corresponding to the bucket identification according to the preset step value.

In this embodiment, when the memory access controller determines the bucket identifier corresponding to the address of the memory page stored in the first memory, the count value of the counter corresponding to the bucket identifier can be incremented according to a preset step value. Among them, the default step value is 1. In one implementation, the memory access controller can also increase the number of calls corresponding to the address of the memory page by 1. The memory access controller can sort the addresses of multiple memory pages stored by the memory access controller based on the number of calls corresponding to the address of each memory page, and sort the addresses of memory pages smaller than the preset serial number and their corresponding buckets Identity for deletion processing.

In one implementation, the memory access controller can establish a mapping relationship between the address of the memory page and the call time information. The memory access controller can filter memory pages whose time interval between the corresponding calling time information and the current time information is greater than the preset time interval, and delete the mapping relationship between the filtered memory pages and the bucket identifier.

In this embodiment, the memory access controller may determine whether the bucket identifier corresponding to the address of the memory page is stored in the first memory when receiving the first instruction. When the bucket identifier corresponding to the address of the memory page is stored in the first memory, the count value of the counter corresponding to the bucket identifier is incremented according to the preset step value; if the bucket identifier corresponding to the address of the memory page is not stored in the first memory, In the case of bucket identification, the storage address of the page ownership table is obtained. Based on the storage address of the page ownership table and the address of the memory page, the bucket identification corresponding to the address of the memory page is determined, and the count value of the counter corresponding to the bucket identification is determined. Increment according to the preset step value. Through the above method of obtaining the bucket identifier directly based on the bucket identifier corresponding to the address of the memory page stored in the first memory of the memory access controller, the acquisition speed of the bucket identifier is improved, and thus the processing speed of the bucket identifier based on the first instruction is improved. The number of accesses to a memory page is increased by 1.

FIG. 6 is a schematic flowchart of Embodiment 4 of a method for determining the number of accesses to a memory page provided by an embodiment of the present application.

Referring to Figure 6, the method specifically includes the following steps:

S601: In response to receiving the first instruction sent by the processor, obtain the storage address of the page ownership table.

In this embodiment, the memory access controller obtains the storage address of the page ownership table in response to receiving the first instruction sent by the processor; wherein the first instruction includes the address of the memory page; the first instruction is used to instruct access to the memory page. The address; the page ownership table is used to record the mapping relationship between the address of the memory page and the bucket identifier.

The specific implementation method is the same as S301 and will not be described again here.

S602: Based on the storage address of the page ownership table and the address of the memory page, determine the bucket identifier corresponding to the address of the memory page.

In this embodiment, the memory access controller may determine the bucket identifier corresponding to the address of the memory page based on the storage address of the page ownership table and the address of the memory page.

The specific implementation method is the same as S302 and will not be described again here.

S603: Increment the count value of the counter corresponding to the bucket identification according to the preset step value.

In this embodiment, the memory access controller may increment the count value of the counter corresponding to the bucket identifier according to a preset step value. Among them, the default step value is 1.

The specific implementation method is the same as S303 and will not be described again here.

S604: Store the count value of the counter corresponding to the bucket identification into the second memory.

In this embodiment, the memory access controller may store the count value of the counter corresponding to the bucket ID into the second memory of the memory access controller to save the count value of the counter corresponding to the bucket number.

S605: In response to receiving the second instruction sent by the processor, send the count value of the counter corresponding to the bucket identification to the processor.

In this embodiment, the memory access controller may send the count value of the counter corresponding to the bucket identification to the processor in response to receiving a second instruction sent by the processor, where the second instruction is used to instruct access to obtain the memory page. frequency.

It should be noted that the processor can count hot and cold pages based on the count value of the counter corresponding to the bucket identifier.

In one implementation, after receiving the count value of the counter corresponding to the bucket identifier, the processor determines the bucket identifier and the corresponding memory page whose count value is greater than the preset threshold as a hot page; The bucket ID equal to the preset threshold and the corresponding memory page are determined to be cold pages.

Specifically, the management software in the processor can determine the hot and cold pages corresponding to each bucket identifier based on the count value of the counter corresponding to the bucket identifier sent by the memory access controller based on the preset threshold value in the user demand, thereby Determine the hot and cold pages corresponding to each memory page.

After the management software in the processor counts the hot and cold pages, it can migrate the data in the hot pages from the memory to the dynamic random access memory (Dynamic Random Access Memory, referred to as DRAM) directly connected to the processor. Specifically, the management software in the processor can allocate a new page in the DRAM, and then copy the data in the old page (memory page counted as a hot page) to the new page. The management software in the processor can unmap the old page (the mapping between logical address and physical address), map the mapping to the new page, and release the old page.

In this embodiment, a page ownership table is provided, which describes the mapping relationship between the address of the memory page and the bucket identifier. The memory access controller obtains the storage address of the page ownership table in response to receiving the first instruction sent by the processor. The memory access controller determines the bucket identifier corresponding to the address of the memory page based on the storage address of the page ownership table and the address of the memory page. The memory access controller increments the count value of the counter corresponding to the bucket identifier according to a preset step value. The memory access controller stores the count value of the counter corresponding to the bucket identification into the second memory. The memory access controller may send the count value of the counter corresponding to the bucket identification to the processor in response to receiving the second instruction sent by the processor. Through the above method of flexibly defining the bucket ID mapping relationship by software, more refined bucketing rules can be provided, thereby improving the accuracy of subsequent processors based on the counter value corresponding to the bucket ID and counting hot and cold pages.

The following is a detailed description of the process in which the memory access controller obtains the page ownership table sent by the processor and stores the page ownership table into the memory through the fifth method embodiment.

In this embodiment, the memory access controller may obtain the page ownership table sent by the processor and store the page ownership table in the memory.

Take the memory as a CXL type3 storage device as an example. The memory access controller can obtain the page ownership table sent by the processor. The page ownership table can be a four-level page table, including a first page ownership table, a second page ownership table and a third page ownership table, where the second page ownership table The table can be a two-level page table.

The size of each level of page ownership table is 4KB. The length of each page table entry in the first page ownership table is 2 bytes, corresponding to a maximum of 65536 buckets (2 bytes 16 bits, which can represent 2 ¹⁶ = 65536 status). The length of page table entries in other levels of page tables is 8 bytes. The entire page ownership table can describe the bucket mapping relationship of up to 512*512*512*2048 memory pages.

In one implementation, the memory access controller may include 256 counters, that is, it supports the use of 256 bucket identifiers.

Figure 7 is a schematic diagram of a scenario for building a page attribution table applicable to the embodiment of the present application.

As shown in Figure 7, the virtual address space (logical address range) of task 1 is 0x1000-0x6000, and 0x21000-0x23000 respectively.

The memory pages corresponding to 0x1000-0x6000 are 0x800000, 0x802000, 0x900000, 0x901000 and 0x902000. The memory pages corresponding to 0x21000-0x23000 are 0x801000 and 0x803000.

The virtual address spaces of task 2 are 0x1000-0x2000 and 0x41000-0x45000 respectively.

The memory pages corresponding to 0x1000-0x2000 are 0x804000. The memory pages corresponding to 0x41000-0x45000 are 0x805000, 0x903000, 0x904000 and 0x905000.

The management software in the processor can construct a page ownership table, which describes the mapping relationship between the address of the memory page and the bucket identifier. In other words, the page ownership table describes the bucket identifiers corresponding to memory pages 0x800000, 0x802000, 0x90000, 0x901000, 0x902000, 0x801000, 0x803000, 0x804000, 0x805000, 0x903000, 0x904000 and 0x905000. .

In one implementation, 0x800000, 0x802000, 0x90000, 0x901000 and 0x902000 correspond to bucket identification 1; 0x801000 and 0x803000 correspond to bucket identification 2; 0x804000 correspond to bucket identification 3; 0x805000, 0x903000, 0x904000 And corresponding to 0x905000 Go to bucket ID 4.

After building the page ownership table, the processor can send the page ownership table to the memory access controller. After receiving the page ownership table, the memory access controller can read the page ownership table in a direct memory access (DMA) manner and store the page ownership table in the memory.

In this embodiment, the processor can flexibly construct the page ownership table based on user needs. Through the above method of flexibly defining the bucket ID mapping relationship by software, more refined bucketing rules can be provided, thereby improving the accuracy of subsequent processors based on the counter value corresponding to the bucket ID and counting hot and cold pages.

The following are device embodiments of the present application, which can be used to execute method embodiments of the present application. For details not disclosed in the device embodiments of this application, please refer to the method embodiments of this application.

An embodiment of the present application also provides a memory access controller. FIG. 8 is a schematic structural diagram of a memory access controller provided by an embodiment of the present application; as shown in FIG. 8 , the memory access controller 80 includes: a transceiver module 81 and a processing module 82 . Among them, the transceiver module 81 is used to obtain the storage address of the page ownership table in response to receiving the first instruction sent by the processor; wherein the first instruction includes the address of the memory page; the first instruction is used to indicate access to the address of the memory page. ; The page ownership table is used to record the mapping relationship between the address of the memory page and the bucket identifier; the processing module 82 is used to determine the bucket identifier corresponding to the address of the memory page based on the storage address of the page ownership table and the address of the memory page; processing Module 82 is also used to increment the count value of the counter corresponding to the bucket identification according to a preset step value; wherein the preset step value is 1.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In one implementation, the page ownership table is a multi-level page table; the multi-level page table includes a first page ownership table, a second page ownership table and a third page ownership table; where the first page ownership table is a first-level page table ;The second page ownership table is an intermediate-level page table; the third page ownership table is the last-level page table; the second page ownership table is one-level or multi-level page tables; each of the first page ownership table and the second page ownership table Each page table entry is used to store the storage address of the next-level page ownership table; each page table entry of the third page ownership table is used to store the bucket identification.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In one implementation, the storage address of the page ownership table is the storage address of the first page ownership table; the processing module 82 is specifically used to: based on the storage address of the page ownership table and the first K bits of the address of the memory page, The storage address of the second page belonging table is determined in the first page belonging table; based on the storage address of the second page belonging table and the middle M bits in the memory page address, the storage of the third page belonging table is determined in the second page belonging table Address; based on the storage address of the third page ownership table and the last N bits of the memory page address, determine the bucket identifier corresponding to the address of the memory page in the third page ownership table.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In one implementation, the page ownership table is stored in memory.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In one implementation, after determining the bucket identifier corresponding to the address of the memory page, the processing module 82 is further configured to: store the bucket identifier corresponding to the address of the memory page into the first memory.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In one implementation, before obtaining the storage address of the page ownership table, the processing module 82 is also used to: determine whether the first memory stores the bucket identifier corresponding to the address of the memory page; store the address of the memory page in the first memory In the case of a corresponding bucket identifier, the count value of the counter corresponding to the bucket identifier is incremented according to a preset step value, where the preset step value is 1.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In one implementation, the processing module 82 is also configured to: obtain the storage address of the page ownership table when the first memory does not store the bucket identification corresponding to the address of the memory page.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In one implementation, after incrementing the count value of the counter corresponding to the bucket identifier according to the preset step value, the processing module 82 is also configured to: store the count value of the counter corresponding to the bucket identifier into the second memory. middle.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

In one implementation, the transceiver module 81 is also configured to: in response to receiving the second instruction sent by the processor, send the count value of the counter corresponding to the bucket identification to the processor; wherein the second instruction is used to instruct the acquisition The number of memory page accesses.

The memory access controller provided in this embodiment can execute the technical solution in the above method embodiment, and its beneficial effects are similar, and will not be described again here.

Embodiments of the present application also provide a computing device, including: a memory, a memory access controller and a processor; wherein the memory and the memory access controller are electrically connected; the memory access controller and the processor are electrically connected;

The memory access controller is used to execute the technical solutions in the foregoing method embodiments. Its implementation principles and technical effects are similar and will not be described again here.

Persons of ordinary skill in the art can understand that all or part of the steps to implement the above method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps including the above-mentioned method embodiments are executed; and the aforementioned storage media include: ROM, magnetic disks, optical disks and other media that can store program codes.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present application, but not to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; these modifications or substitutions do not cause the essence of the corresponding technical solutions to depart from the scope of the technical solutions of the embodiments of the present application. .

Claims (10)

1. The method for determining the access times of the memory page is characterized by comprising the following steps:

responding to a first instruction sent by a processor, and acquiring a storage address of a page attribution table; the first instruction comprises an address of a memory page; the first instruction is used for indicating an address for accessing the memory page; the page attribution table is used for recording the mapping relation between the address of the memory page and the barrel identification;

determining a barrel identification corresponding to the address of the memory page based on the storage address of the page attribution table and the address of the memory page;

the count value of a counter corresponding to the sub-bucket identification is increased according to a preset stepping value; wherein the preset step value is 1.

2. The method of claim 1, wherein the page home table is a multi-level page table;

the multi-level page table comprises a first page attribution table, a second page attribution table and a third page attribution table;

wherein the first page attribution table is a first-stage page table; the second page attribution table is an intermediate-stage page table; the third page attribution table is a final page table; the second page attribution table is a one-level or multi-level page table;

Each page table item of the first page attribution table and the second page attribution table is used for storing a storage address of a next-level page attribution table; each page table entry of the third page home table is used for storing a bucket identifier.

3. The method of claim 2, wherein the memory address of the page home table is the memory address of the first page home table;

the determining the bucket identifier corresponding to the address of the memory page based on the storage address of the page attribution table and the address of the memory page comprises the following steps:

determining the storage address of the second page attribution table in the first page attribution table based on the storage address of the page attribution table and the first K bits in the address of the memory page;

determining the storage address of the third page home table in the second page home table based on the storage address of the second page home table and the middle M bits in the memory page address;

and determining a barrel identification corresponding to the address of the memory page in the third page attribution table based on the storage address of the third page attribution table and the last N bits in the memory page address.

4. A method according to any one of claims 1-3, wherein the page home table is stored in a memory.

5. The method according to any one of claims 2-4, wherein after determining the bucket identifier corresponding to the address of the memory page, the method further comprises:

and storing the address of the memory page and the corresponding sub-bucket identifier into a first memory.

6. The method of any of claims 1-5, wherein prior to retrieving the memory address of the page home table, the method further comprises:

determining whether the first storage stores a bucket identifier corresponding to an address of the memory page;

and under the condition that the first storage stores the sub-bucket identifications corresponding to the addresses of the memory pages, the count value of the counter corresponding to the sub-bucket identifications is increased according to a preset step value, wherein the preset step value is 1.

7. The method according to any one of claims 1-6, further comprising:

and under the condition that the first storage does not store the bucket identification corresponding to the address of the memory page, acquiring the storage address of the page attribution table.

8. The method according to any one of claims 1-7, wherein after incrementing the count value of the counter corresponding to the bucket identifier by a preset step value, the method further comprises:

and storing the count value of the counter corresponding to the barrel identification into a second memory.

9. The method of claim 8, wherein the method further comprises:

in response to receiving a second instruction sent by the processor, sending a count value of a counter corresponding to the barrel identification to the processor;

the second instruction is used for indicating the access times for acquiring the memory page.

10. A computing device, the computing device comprising: memory, memory access controller and processor; the memory is electrically connected with the memory access controller; the access controller is electrically connected with the processor;

the memory access controller is configured to execute the method for determining the number of accesses to a memory page according to any one of claims 1 to 9.