CN117033050A - Method, system, storage medium and electronic device for sending state information - Google Patents

Abstract

The embodiment of the application provides a method, a system, a storage medium and electronic equipment for sending state information, wherein the method comprises the following steps: receiving a first detection signal sent by an integrated circuit, wherein the integrated circuit and a programmable logic device are positioned on the same external plug-in card; sampling the first detection signal to obtain a first sampling signal; under the condition that waveforms of the first sampling signal and a preset detection signal are inconsistent, a fault signal is sent to the multiplexer, wherein the fault signal is used for indicating that the integrated circuit breaks down; in the case that the multiplexer establishes a connection of the programmable logic device with the server according to the fault signal, the status information of the add-in card is transmitted to the server through the connection. The application solves the problem that the state of the external card and the reporting of data are affected due to the abnormal occurrence of the integrated signal when the information interaction is carried out between the current external card and the server in the prior art.

Description

Status information sending method, system, storage medium and electronic device

Technical field

Embodiments of the present application relate to the field of communications, specifically, to a method, system, storage medium and electronic device for sending status information.

Background technique

As the requirements for bandwidth, flexibility and performance of network equipment gradually increase, the PCIe standard (PeripheralComponent Interconnect Express, a high-speed serial computer expansion bus standard) came into being. PCIe has developed rapidly since its advent in 2001 and is widely used in various network devices. PCIe card (PCI Express card) is one of the main devices.

A PCIe card refers to a board with a PCIe interface that can implement specific functions. Usually used to expand the performance and functionality of computers, such as PCIe slots installed in the motherboards of devices such as hosts, servers, and network switches. PCIe cards can provide computers with faster data transfer speeds and higher performance through the high bandwidth and low latency characteristics of PCIe slots.

Specifically, when a PCIe plug-in card is inserted into a device such as a server, the server needs to monitor the operating status of the PCIe plug-in card and information such as board temperature and voltage, so that the server can sense the status of the PCIe plug-in card in a timely manner. Therefore, the management mechanism for PCIe plug-in cards is very important for the entire server system.

Currently, PCIe plug-in cards mainly interact with server information in two ways, one is PCIe in-band transmission, and the other is transmission through the I2C interface. Generally, these two interfaces are output by the ASIC (Application Specific Integrated Circuit, chip technology for application specific integrated circuit) on the card. When the ASIC is abnormal, the server will be unable to monitor or transmit information through these two methods.

The above solution has the following disadvantages: Currently, the main way for servers to obtain PCIe plug-in card data information is through the BMC (Baseboard Management Controller) through the I2C interface on the PCIe card slot. When the plug-in card ASIC appears, When the problem occurs, the I2C interface connected to the BMC may cause communication interruption or bus hangup due to ASIC abnormalities, and the server BMC cannot obtain the board status.

Therefore, in the prior art, when the external plug-in card interacts with the server, the problem of affecting the status of the plug-in card and the reporting of data due to abnormalities in the integrated circuit has not been effectively solved.

Contents of the invention

Embodiments of the present application provide a method, system, storage medium and electronic device for sending status information, so as to at least solve the problem in related technologies that the external plug-in card is affected by anomalies in the integrated circuit when the plug-in card interacts with the server. Status and data reporting issues.

According to an embodiment of the present application, a method for sending status information is provided, including: receiving a first detection signal sent by an integrated circuit, wherein the integrated circuit and the programmable logic device are located on the same plug-in card; The first detection signal is sampled to obtain a first sampling signal; when the waveform of the first sampling signal is inconsistent with the preset detection signal, a fault signal is sent to the multiplexer, wherein: The fault signal is used to indicate that the integrated circuit has failed; when the multiplexer establishes a connection between the programmable logic device and the server according to the fault signal, the plug-in card is connected to the plug-in card through the connection. Status information is sent to the server.

In an exemplary embodiment, sampling the first detection signal to obtain a first sampling signal includes: determining a first frequency of the first detection signal, and determining a second frequency according to the first frequency; The second frequency samples the first detection signal to obtain the first sampling signal.

In an exemplary embodiment, before receiving the first detection signal sent by the integrated circuit, the method further includes: determining whether the first detection signal sent by the integrated circuit is received within a first preset time period; If the first detection signal sent by the integrated circuit is not received within the first preset time period, send a second detection signal to the integrated circuit; according to whether the first detection signal is received within the second preset time period. The first response signal sent by the integrated circuit determines whether the integrated circuit has failed.

In an exemplary embodiment, determining whether the integrated circuit fails based on whether the first response signal sent by the integrated circuit is received within the second preset time period includes: within the second preset time If the first response signal sent by the integrated circuit is not received within the period, it is determined that the integrated circuit is faulty; if the first response signal sent by the integrated circuit is received within the second preset time period, In this case, the first response signal is sampled to obtain a second sampling signal; it is determined whether the waveforms of the second sampling signal and the preset response signal are consistent; when the second sampling signal and the preset response signal are If the waveforms of the signals are consistent, it is determined that the integrated circuit is not faulty.

In an exemplary embodiment, after sampling the first detection signal to obtain the first sampling signal, the method further includes: determining whether the waveforms of the preset detection signal and the first sampling signal are consistent. ; When the waveforms of the preset detection signal and the first sampling signal are inconsistent, it is determined that the integrated circuit has failed; a reset instruction is sent to the integrated circuit through the reset interface of the integrated circuit, so that the integrated circuit The integrated circuit performs a reset operation according to the reset instruction.

In an exemplary embodiment, after sending a fault signal to the multiplexer, the method further includes: obtaining abnormal data of the integrated circuit through a debugging interface of the integrated circuit; The abnormal data is sent to the server, so that the server parses the abnormal data and debugs the integrated circuit according to the parsed abnormal data.

In an exemplary embodiment, after sending the status information of the plug-in card to the server through the connection, the method further includes: sending a third detection signal to the integrated circuit; determining whether Suppose whether the second response signal sent by the integrated circuit is received within the time period, wherein the second response signal is a signal in response to the third detection signal; whether the second response signal is received within the second preset time period In the case of a second response signal sent by the integrated circuit, the second response signal is sampled to obtain a third sampling signal; it is determined whether the waveform of the third sampling signal is consistent with the preset response signal; in the When the third sampling signal is consistent with the waveform of the preset response signal, it is determined that the integrated circuit has recovered from the fault; a fault recovery signal is sent to the multiplexer so that the multiplexer can The fault recovery signal establishes a connection between the integrated circuit and the server, wherein the fault recovery signal is used to indicate that the integrated circuit has failed.

According to another embodiment of the present application, a system for sending status information is provided, including: an integrated circuit, a programmable logic device connected to the integrated circuit, and a system connected to the integrated circuit and the programmable logic device. Multiplexer, wherein the integrated circuit is used to send a first detection signal to the programmable logic device; the programmable logic device is used to sample the first detection signal to obtain the first detection signal. a sampling signal; when the waveforms of the first sampling signal and the first detection signal are inconsistent, sending a fault signal to the multiplexer; the multiplexer is configured to receive In the case of the fault signal, establish a connection between the programmable logic device and the server; the programmable logic device is also used to send the status information of the external plug-in card to the server through the connection, wherein the The integrated circuit and the programmable logic device are both located on the plug-in card.

According to yet another embodiment of the present application, a computer-readable storage medium is also provided. A computer program is stored in the computer-readable storage medium, wherein the computer program is configured to execute any of the above methods when running. Steps in Examples.

According to yet another embodiment of the present application, an electronic device is also provided, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to perform any of the above. Steps in method embodiments.

Through this application, since the editable logic device receives the first detection signal sent by the integrated circuit located on the same plug-in card, it samples the first detection signal to obtain the first sampling signal; when the first sampling signal and When the waveforms of the preset detection signals are inconsistent, a fault signal indicating a fault in the integrated circuit is sent to the multiplexer; after the multiplexer establishes the relationship between the programmable logic device and the programmable logic device based on the fault signal, In the case of a server connection, the status information of the external plug-in card is sent to the server through the connection. Therefore, it is possible to solve the problem in the prior art that the status of the external plug-in card and the reporting of data are affected due to abnormalities in the integrated circuit when the external plug-in card interacts with the server.

Description of the drawings

Figure 1 is a hardware structure block diagram of a computer terminal of a method for sending status information according to an embodiment of the present application;

Figure 2 is a flow chart of a method for sending status information according to an embodiment of the present application;

Figure 3 is a schematic diagram of the signal waveform of the first detection signal and the input analysis first detection signal according to an embodiment of the present application;

Figure 4 is a schematic diagram of the signal waveform of the first response signal and the input analysis first response signal according to an embodiment of the present application;

Figure 5 is a structural block diagram of a general data monitoring method for a PCIe plug-in card in the prior art;

Figure 6 is an overall scheme design diagram of a method for sending status information according to an exemplary embodiment of the present application;

Figure 7 is a schematic diagram of the GPIO interconnection between ASIC and CPLD dual-active status detection according to an exemplary embodiment of the present application;

Figure 8 is a waveform diagram of ASIC and CPLD dual-active state detection and analysis according to an exemplary embodiment of the present application;

Figure 9 is a circuit design diagram of a server and a PCIe add-in card according to an exemplary embodiment of the present application;

Figure 10 is a structural block diagram of a status information sending system according to an embodiment of the present application.

Detailed ways

The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

The method embodiments provided in the embodiments of this application can be executed in a mobile terminal, a computer terminal, or a similar computing system. Taking running on a computer terminal as an example, FIG. 1 is a hardware structure block diagram of a computer terminal for a method of sending status information according to an embodiment of the present application. As shown in Figure 1, the computer terminal may include one or more (only one is shown in Figure 1) processors 102 (the processor 102 may include but is not limited to a processing system such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned computer terminal may also include a transmission device 206 for communication functions and an input and output device 108. Persons of ordinary skill in the art can understand that the structure shown in Figure 1 is only illustrative, and it does not limit the structure of the above-mentioned computer terminal. For example, the computer terminal may also include more or fewer components than shown in FIG. 1 , or have a different configuration than shown in FIG. 1 .

The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the status information sending method in the embodiment of the present application. The processor 102 runs the computer program stored in the memory 104, thereby Execute various functional applications and data processing, that is, implement the above methods. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage systems, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely relative to the processor 102, and these remote memories may be connected to the computer terminal through a network. Examples of the above-mentioned networks include but are not limited to the Internet, intranets, local area networks, mobile communication networks and combinations thereof.

Transmission device 106 is used to receive or send data via a network. Specific examples of the above-mentioned network may include a wireless network provided by a communication provider of the computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC for short), which can be connected to other network devices through a base station to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (Radio Frequency, RF for short) module, which is used to communicate with the Internet wirelessly.

Figure 2 is a flow chart of a method for sending status information according to an embodiment of the present application. As shown in Figure 2, the process includes the following steps:

Step S202: Receive the first detection signal sent by the integrated circuit, wherein the integrated circuit and the programmable logic device are located on the same plug-in card;

Step S204, sample the first detection signal to obtain a first sampling signal;

Step S206: If the waveforms of the first sampling signal and the preset detection signal are inconsistent, send a fault signal to the multiplexer, where the fault signal is used to indicate that the integrated circuit is faulty;

It should be noted that when the integrated circuit does not malfunction, the detection signal is consistent with the preset detection signal. For example, when the level of the preset detection signal jumps to 10101, if the integrated circuit does not malfunction, the level of the detection signal sent by the integrated circuit jumps to 10101. Furthermore, if the level of the sampling signal If it jumps to 11001 and is inconsistent with the preset detection signal, it is determined that the integrated circuit is faulty.

Step S208: When the multiplexer establishes a connection between the programmable logic device and the server according to the fault signal, send the status information of the plug-in card to the server through the connection.

Through the above steps, since the editable logic device receives the first detection signal sent by the integrated circuit located on the same plug-in card, it samples the first detection signal to obtain the first sampling signal; between the first sampling signal and When the waveforms of the preset detection signals are inconsistent, a fault signal indicating a fault in the integrated circuit is sent to the multiplexer; after the multiplexer establishes the relationship between the programmable logic device and the programmable logic device based on the fault signal, In the case of a server connection, the status information of the external plug-in card is sent to the server through the connection. This solves the problem in the prior art that when the current plug-in card interacts with the server, the status of the plug-in card and the reporting of data are affected due to anomalies in the integrated signal. Optionally, the above step S204 can be implemented in the following manner: determining the first frequency of the first detection signal, and determining the second frequency according to the first frequency; sampling the first detection signal at the second frequency , to obtain the first sampling signal.

It can be understood that to sample the first detection signal sent by the integrated circuit, it is necessary to determine the first frequency corresponding to the first detection signal, and further, to determine the second frequency used to sample the first detection signal, and determining the analysis signal corresponding to the second frequency, performing rising edge sampling on the first detection signal according to the analysis signal, and obtaining the first sampling signal. Among them, sampling according to the rising edge of the waveform effectively reduces the amount of sampled data, thereby reducing the cost of storing and transmitting signals, while improving the sampling accuracy and system response speed.

For example, if the waveform of the first detection signal is set to a level of 10101 and the first frequency is 2Hz, then the second frequency of the first sampling signal is 1Hz. Figure 3 shows the first detection signal and Input and analyze the signal waveform diagram of the first detection signal, as shown in Figure 3. Waveform 1 is the signal waveform diagram of the ASIC (which can be understood as an integrated circuit) outputting the DSTSCT signal (equivalent to the first detection signal), which is performed by waveform 2. It is sampled on the rising edge, and the level is 10101. Waveform 2 is a schematic diagram of the signal waveform of the CPLD (which can be understood as a programmable logic circuit) input and analyzed DETECT signal.

Further, when the first sampling signal is consistent with the preset detection signal, it is determined that the integrated circuit has not failed. For example: if the preset detection signal is 10101 and CPLD parses out 10101, then the preset detection signal is consistent with the signal parsed by CPLD, confirming that the integrated circuit has not failed; if the ASIC outputs 10101 under normal circumstances, the preset detection signal is 10101 , and the CPLD parses out 11010, the first sampling signal is inconsistent with the preset detection signal. This situation may be caused by an abnormality in the ASIC itself, causing its output to be inconsistent with the preset detection signal. Therefore, when the data analyzed by the CPLD is inconsistent with the preset detection signal, If the detection signals are inconsistent, it can be determined that the ASIC chip is faulty.

Optionally, before receiving the first detection signal sent by the integrated circuit, the method further includes: determining whether the first detection signal sent by the integrated circuit is received within a first preset time period; If the first detection signal sent by the integrated circuit is not received within the second preset time period, a second detection signal is sent to the integrated circuit; according to whether the first response sent by the integrated circuit is received within the second preset time period. signal to determine whether the integrated circuit has failed.

It can be understood that within a time period, the integrated circuit sends a first detection signal to the programmable logic device every time interval passes. Therefore, the programmable logic device receives a first detection signal sent by the integrated circuit every time interval passes. detection signal. If the programmable logic device does not receive the first detection signal sent by the integrated circuit after a time interval (which can be understood as the first preset time period), it needs to detect whether the integrated circuit has failed. Specifically: the programmable logic device sends a signal to the integrated circuit. The device sends a second detection signal to determine whether a response signal from the integrated circuit is received within a preset time period, and then determines whether the integrated circuit is faulty.

Optionally, if the first response signal sent by the integrated circuit is not received within the second preset time period, it is determined that the integrated circuit is faulty; if the first response signal sent by the integrated circuit is not received within the second preset time period, When receiving the first response signal sent by the integrated circuit, sampling the first response signal to obtain a second sampling signal; determining whether the waveform of the second sampling signal is consistent with the preset response signal; When the waveform of the second sampling signal is consistent with the preset response signal, it is determined that the integrated circuit has not failed.

It can be understood that, when the first response signal sent by the integrated circuit is received within the second preset time period, the first response signal needs to be sampled. Specifically: when the frequency of the first response signal is the first frequency, the first response signal is sampled on the rising edge at the second frequency to obtain the second sampling signal. Among them, rising edge sampling based on the waveform effectively reduces the amount of sampled data, thereby reducing the cost of storing and transmitting signals, while improving the accuracy and precision of sampling.

For example, if the waveform of the first response signal is set to a level of 10101 and the first frequency is 1Hz, then the second frequency of the analytical signal is 0.5Hz. Figure 4 shows the first response signal and input according to an embodiment of the present application. Analyze the signal waveform diagram of the first response signal, as shown in Figure 4. Waveform 1 is the signal waveform diagram of the ASIC output ACK signal (which can be understood as the first response signal). The rising edge of waveform 1 is sampled by waveform 2 to obtain the second Sampling signal, the level of the second sampling signal is 10101, where waveform 2 is a schematic diagram of the signal waveform of the CPLD input and analysis ACK signal.

Further, when the second sampling signal obtained by the CPLD is consistent with the preset response signal (when the integrated circuit does not malfunction, the preset response signal is consistent with the first response signal), it is determined that the integrated circuit does not malfunction.

For example: if ASIC outputs 10101 and CPLD parses out 10101, then the signal output by ASIC is consistent with the preset response signal, confirming that the integrated circuit has not failed; if ASIC outputs 10101 under normal circumstances, the preset response signal is 10101, and CPLD parses If 11010 is output, the signal output by the ASIC is inconsistent with the preset response signal, and it is determined that the ASIC chip is abnormal.

Optionally, after sampling the first detection signal to obtain the first sampling signal, the method further includes: determining whether the waveforms of the preset detection signal and the first sampling signal are consistent; When the waveform of the signal is inconsistent with the first sampling signal, it is determined that the integrated circuit is faulty; a reset instruction is sent to the integrated circuit through the reset interface of the integrated circuit, so that the integrated circuit can be reset according to the reset interface of the integrated circuit. The instruction performs a reset operation.

It can be understood that there is a reset interface in the integrated circuit, and the interface forms include but are not limited to: I2C/UART/SPI/JTAG and other interface forms. When it is determined that the integrated circuit has failed, the programmable logic device can send data through the above reset interface. Reset command to perform a reset operation in an attempt to resolve issues that may cause the device to become unstable or malfunction. Furthermore, performing a reset operation through the reset interface can protect system security and prevent greater damage or security risks that may result from continued operation of the system.

Optionally, after sending a fault signal to the multiplexer, the method further includes: obtaining abnormal data of the integrated circuit through a debugging interface of the integrated circuit; sending the abnormal data to the integrated circuit through the connection. A server, so that the server parses the abnormal data and debugs the integrated circuit according to the parsed abnormal data.

It can be understood that there is a debugging interface connected between the integrated circuit and the programmable logic device, such as: Debug debugging interface. The interface forms include but are not limited to: I2C/UART/SPI/JTAG and other interface forms. When it is determined that the integrated circuit is faulty, In this case, the programmable logic device can try to access the faulty integrated circuit through the above-mentioned debugging interface and obtain the abnormal data of the integrated circuit to achieve a certain debugging purpose.

The above-mentioned debugging interface may be an interface used for debugging and diagnosing software or hardware problems. It provides tools and features that enable developers to view and analyze program execution to identify errors and problems. Through the above debugging interface, developers can monitor the values of variables, track function calls, capture and analyze exceptions, etc. while the program is running. The debugging interface can include: debugger, breakpoint setting, single-step execution, viewing memory and register status and other functions to help developers locate and fix problems.

Optionally, after sending the status information of the plug-in card to the server through the connection, the method further includes: sending a third detection signal to the integrated circuit; determining whether it is received within a second preset time period. The second response signal sent by the integrated circuit, wherein the second response signal is a signal in response to the third detection signal; the second response signal sent by the integrated circuit is received within the second preset time period. In the case of a response signal, the second response signal is sampled to obtain a third sampling signal; it is determined whether the waveform of the third sampling signal is consistent with the preset response signal; when the third sampling signal is consistent with the waveform of the preset response signal, When the waveforms of the preset response signals are consistent, it is determined that the integrated circuit has recovered from the fault; a fault recovery signal is sent to the multiplexer, so that the multiplexer establishes the fault recovery signal based on the fault recovery signal. The connection between the integrated circuit and the server, wherein the fault recovery signal is used to indicate that the integrated circuit has failed.

It can be understood that when an integrated circuit fails, a connection between the programmable logic device and the server is established based on the failure signal, and the connection is used to send status information of the plug-in card to the server. The programmable logic device can send a detection signal to the integrated circuit after an interval to determine whether the response signal sent by the integrated circuit is received within an interval. If the response signal sent by the integrated circuit is received, the response signal Sampling is performed to obtain a sampled signal. The method of sampling the response signal is consistent with the above-mentioned sampling method. When the sampling signal is consistent with the preset response signal, it is determined that the integrated circuit fault has been recovered. At this time, the signal that the fault has been recovered is sent. To the multiplexer, establish a connection between the integrated circuit and the server, and be used to send the status information of the plug-in card to the server through the integrated circuit. Furthermore, the method of indicating the failure of the integrated circuit through a fault recovery signal can improve the efficiency of fault diagnosis and improve the reliability of the system.

Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus the necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is Better implementation. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product in essence or that contributes to the existing technology. The computer software product is stored in a storage medium (such as ROM/RAM, disk, CD), including several instructions to cause a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in various embodiments of this application.

In order to better understand the process of the above method for sending status information, the implementation process of the above method for sending status information will be described below with reference to optional embodiments, but this is not intended to limit the technical solutions of the embodiments of the present application.

Figure 5 is a structural block diagram of a general data monitoring method for a PCIe plug-in card in the prior art; as shown in Figure 5, the main implementation method is an integrated circuit ASIC chip (Application Specific Integrated Circuit, chip technology for application specific integrated circuit) I2C The interface directly connects temperature sensor, ADC (Analog to Digital Converter, A/D converter) and EEPROM (Electrically Erasable Programmable Read-Only Memory) and other chips for detection. Board temperature, voltage data and FRU information. After the ASIC obtains the data, the server's BMC (Baseboard Management Controller) can report this part of the data through the I2C interface between the ASIC and the server. However, this solution has a drawback, that is, when the ASIC is abnormal, the I2C that interacts with the BMC will not work properly, which will affect the reporting of board status and data. That is to say, the common data monitoring methods for PCIe plug-in cards in the prior art cannot solve the problem of affecting the status of the plug-in card and the reporting of data due to abnormalities in the integrated circuit when the plug-in card currently interacts with the server.

Embodiments of the present application provide a method, system, storage medium and electronic device for sending status information, so as to at least solve the problem in related technologies that the external plug-in card is affected by anomalies in the integrated circuit when the plug-in card interacts with the server. Status and data reporting issues. Figure 6 is an overall scheme design diagram of a method for sending status information according to an exemplary embodiment of the present application. As shown in Figure 6, the PCIe plug-in card and the I2C interface connected to the server BMC are composed of on-board CPLD and ASIC Each has one channel, and is connected to the BMC of the server after selection by the MUX multiplexing switch. When there is a problem with any chip of the PCIe external card CPLD or ASIC, the server can still communicate with the PCIe external card and obtain the board temperature. , voltage and other basic data.

ASIC and CPLD are interconnected through GPIO (input and output pins), and a dual-active detection mechanism is designed to detect the working status between the two chips. When a failure of the ASIC chip is detected, the I2C chip is controlled by controlling the MUX chip. The interface is switched to the CPLD side, and the CPLD communicates with the BMC of the server to ensure that the communication between the server and the PCIe plug-in card will not be completely interrupted.

Figure 7 is a schematic diagram of GPIO interconnection between ASIC and CPLD dual-active status detection according to an exemplary embodiment of the present application. As shown in Figure 7, on the PCIe plug-in card, two sets of interconnections are designed on the hardware path between ASIC and CPLD. The GPIO line is used to detect the working status between ASIC and CPLD in real time, so that ASIC and CPLD can detect whether the other party is working abnormally in time. The specific implementation is as follows:

There are two GPIO pins between ASIC and CPLD for interconnection, and the interconnection signals are defined as DETECT and ACK respectively. The DETECT signal is the signal output by the ASIC to the CPLD. The ASIC serves as the output terminal and the CPLD serves as the input terminal.

For the output ASIC, Figure 8 is a waveform diagram of the ASIC and CPLD dual-active status detection analysis according to an exemplary embodiment of the present application. The waveform shown in waveform 1 in Figure 8 is output through the GPIO_0_ASIC pin, which can be set to 101010, and the frequency can be is x Hz (the actual frequency can be set according to different application scenarios). For the input CPLD, the x Hz waveform output by the ASIC is sampled on the rising edge at the x/2Hz frequency through the GPIO_0_CPLD pin, and the sampling is as shown in Figure 8 For such a level transition state of 101010, if the sampling result is consistent with the 101010 sent by the preset ASIC, it is considered that the ASIC is working normally; otherwise, it is abnormal.

The time interval between ASIC sending the DETECT signal twice is set to T1, and ASIC will send a DETECT signal every T1 time.

When the CPLD detects that the ASIC is working normally, it will reply the ASIC chip ACK response signal within the interval T2, the CPLD outputs a 1010 level transition, and the GPIO_1_ASIC pin of the ASIC outputs an ACK of x Hz to the GPIO_1_CPLD of the CPLD at a sampling frequency of x/2Hz. The signal is sampled on the rising edge.

At the same time, ASIC sets a detection time T3 to detect whether the CPLD's reply ACK has timed out. If the CPLD does not send an ACK response signal beyond the T3 time, it is determined that the CPLD is abnormal.

In addition, connect the GPIO_2 pins of ASIC and CPLD to the RESET pin of the other chip respectively. When ASIC and CPLD detect a status abnormality on either side, the reset function of the abnormal chip can be realized through GPIO 2.

Figure 9 is a circuit design diagram of a server and a PCIe plug-in card according to an exemplary embodiment of the present application. The specific implementation is as follows:

For PCIe plug-in cards, temperature sensors, ADC chips, EEPROM chips and other devices will be placed on the board to monitor the temperature, voltage, FRU and other information on the board. Usually, these devices will be mounted on ASIC chips, and the server BMC will obtain board monitoring data through the I2C interface on the PCIe plug-in card. However, in the above scheme, when the ASIC works abnormally, the server will be unable to access the data. Therefore, in the embodiment of this application, an I2C interface from the ASIC and the CPLD is connected to the MUX multiplexing multi-selection switch, and the MUX multiplexing multi-selection switch is switched. Determine whether the Host side of I2C comes from ASIC or PCLD.

For devices such as temperature sensors, ADC chips, and EEPROM chips, they will be connected to ASIC and CPLD chips at the same time. Under normal circumstances, ASIC serves as the host. MUX defaults to the path from ASIC to the server, and ASIC implements on-board data monitoring, reporting, and transmission. Give the server BMC. However, when the ASIC chip is working abnormally and CPLD detects that the ASIC chip is abnormal through the dual-active detection mechanism, it will control the MUX multiplexing switch to switch to the CPLD terminal through the MXU_EN signal. The Host terminal of the I2C interface will switch to CPLD, and CPLD will continue. Realize monitoring and reporting of board temperature, voltage and other information. Ensure that the server's acquisition of PCIe plug-in card information will not be interrupted.

In addition, ASIC and CPLD reserve Debug interfaces. The interface form can be any form such as I2C, UART, SPI or JTAG. It depends on which method the ASIC chip supports. When the ASIC is abnormal, the server BMC can be connected to the I2C interface through the I2C interface. CPLD implements debugging of ASIC through the internal logic of CPLD, providing a path for daily debugging and facilitating operation and maintenance.

ASIC and CPLD are connected to a Debug debugging interface. The interface form can be I2C/UART/SPI/JTAG and other interface forms. The details are determined according to the Debug interface supported by the ASIC. This design can realize that when there is a problem with the ASIC, the CPLD can use the Debug interface. Try to access the ASIC to see if you can capture some data when the ASIC is abnormal, and pass it to the server BMC for analysis through the I2C interface of the CPLD to achieve a certain debugging purpose.

The Debug interface is an interface used to debug and diagnose software or hardware problems. It provides tools and features that enable developers to view and analyze program execution to identify errors and problems. Through the Debug interface, developers can monitor the values of variables, track function calls, capture and analyze exceptions, etc. while the program is running. Debug interfaces usually include functions such as debuggers, breakpoint settings, single-step execution, and viewing memory and register status to help developers locate and fix problems.

This embodiment also provides a system for sending status information, which is used to implement the above embodiments and preferred implementations. What has already been described will not be described again. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the systems described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

Figure 10 is a structural block diagram of a status information sending system according to an embodiment of the present application. As shown in Figure 10, the system includes:

Integrated circuit 1002, a programmable logic device 1004 connected to the integrated circuit 1002, a multiplexer 1006 connected to the integrated circuit 1002 and the programmable logic device 1004, wherein,

The integrated circuit 1002 is used to send a first detection signal to the programmable logic device;

The programmable logic device 1004 is configured to sample the first detection signal to obtain a first sampling signal; when the waveforms of the first sampling signal and the first detection signal are inconsistent, The multiplexer sends a fault signal;

The multiplexer 1006 is used to establish a connection between the programmable logic device and the server when the fault signal is received;

The programmable logic device 1004 is also configured to send the status information of the plug-in card to the server through the connection, wherein the integrated circuit and the programmable logic device are both located on the plug-in card.

Through the above system, due to receiving the first detection signal sent by the integrated circuit, wherein the integrated circuit and the programmable logic device are located on the same plug-in card; the first detection signal is sampled to obtain the first sample signal; when the waveform of the first sampling signal is inconsistent with the preset detection signal, sending a fault signal to the multiplexer, wherein the fault signal is used to indicate that the integrated circuit is faulty; in the When the multiplexer establishes a connection between the programmable logic device and the server according to the fault signal, the multiplexer sends the status information of the plug-in card to the server through the connection. This application solves the existing problem in the prior art that when an external plug-in card interacts with a server, the status of the plug-in card and the reporting of data are affected due to anomalies in the integrated signal.

In an optional embodiment, the programmable logic device is further configured to: determine a first frequency of the first detection signal, and determine a second frequency based on the first frequency; The first detection signal is sampled to obtain the first sampling signal.

In an optional embodiment, the programmable logic device is further configured to: determine whether a first detection signal sent by the integrated circuit is received within a first preset time period; If the first detection signal sent by the integrated circuit is not received within the time period, a second detection signal is sent to the integrated circuit; according to whether the first detection signal sent by the integrated circuit is received within the second preset time period. A response signal to determine whether the integrated circuit has failed.

In an optional embodiment, the programmable logic device is further configured to: determine that the first response signal sent by the integrated circuit is not received within the second preset time period. The integrated circuit fails; when receiving the first response signal sent by the integrated circuit within the second preset time period, sampling the first response signal to obtain a second sampling signal; determining the Whether the waveforms of the second sampling signal and the preset response signal are consistent; if the waveforms of the second sampling signal and the preset response signal are consistent, it is determined that the integrated circuit has not failed.

In an optional embodiment, the programmable logic device is further configured to: determine whether the waveforms of the preset detection signal and the first sampling signal are consistent; When the waveforms of the sampling signals are inconsistent, it is determined that the integrated circuit is faulty; a reset instruction is sent to the integrated circuit through the reset interface of the integrated circuit.

Wherein, the integrated circuit is further configured to: receive a reset instruction sent by the programmable logic device, and perform a reset operation according to the reset instruction.

In an optional embodiment, the programmable logic device is further configured to: obtain abnormal data of the integrated circuit through a debugging interface of the integrated circuit; send the abnormal data to the integrated circuit through the connection. server.

Wherein, the system further includes: a server, configured to receive the abnormal data sent by the programmable logic device, parse the abnormal data, and debug the integrated circuit according to the parsed abnormal data.

In an optional embodiment, the programmable logic device is further configured to: send a third detection signal to the integrated circuit; determine whether a third detection signal sent by the integrated circuit is received within a second preset time period. Two response signals, wherein the second response signal is a signal in response to the third detection signal; when the second response signal sent by the integrated circuit is received within the second preset time period, the Sampling the second response signal to obtain a third sampling signal; determining whether the waveform of the third sampling signal is consistent with the preset response signal; when the waveform of the third sampling signal is consistent with the preset response signal In the case of , it is determined that the integrated circuit has recovered from the fault; and a fault recovery signal is sent to the multiplexer.

Wherein, the multiplexer is further configured to: receive a fault recovery signal sent by the programmable logic device, and establish a connection between the integrated circuit and the server according to the fault recovery signal, wherein the fault The recovery signal is used to indicate that the integrated circuit has failed.

It should be noted that each of the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but is not limited to this: the above modules are all located in the same processor; or the above modules can be implemented in any combination. The forms are located in different processors.

Embodiments of the present application also provide a computer-readable storage medium that stores a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.

In an exemplary embodiment, the computer-readable storage medium may include but is not limited to: USB flash drive, read-only memory (ROM), random access memory (Random Access Memory, RAM) , mobile hard disk, magnetic disk or optical disk and other media that can store computer programs.

An embodiment of the present application also provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

In an exemplary embodiment, the above-mentioned electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the above-mentioned processor, and the input-output device is connected to the above-mentioned processor.

For specific examples in this embodiment, reference may be made to the examples described in the above-mentioned embodiments and exemplary implementations, and details will not be described again in this embodiment.

Obviously, those skilled in the art should understand that the above-mentioned modules or steps of the present application can be implemented using a general computing system. They can be concentrated on a single computing system, or distributed across a network composed of multiple computing systems. , they may be implemented in program code executable by a computing system, whereby they may be stored in a storage system for execution by the computing system, and, in some cases, may be executed in a sequence different from that shown here or the described steps, or they are respectively made into individual integrated circuit modules, or multiple modules or steps among them are made into a single integrated circuit module. As such, the application is not limited to any specific combination of hardware and software.

The above descriptions are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the principles of this application shall be included in the protection scope of this application.

Claims (10)

1. The method for sending the state information is characterized by being applied to a programmable logic device and comprising the following steps of:

receiving a first detection signal sent by an integrated circuit, wherein the integrated circuit and the programmable logic device are positioned on the same external plug-in card;

sampling the first detection signal to obtain a first sampling signal;

transmitting a fault signal to a multiplexer under the condition that waveforms of the first sampling signal and a preset detection signal are inconsistent, wherein the fault signal is used for indicating that the integrated circuit breaks down;

and under the condition that the multiplexer establishes connection between the programmable logic device and a server according to the fault signal, the state information of the plug-in card is sent to the server through the connection.

2. The method of claim 1, wherein sampling the first detection signal to obtain a first sampled signal comprises:

Determining a first frequency of the first detection signal and determining a second frequency according to the first frequency;

and sampling the first detection signal at the second frequency to acquire the first sampling signal.

3. The method of claim 1, wherein prior to receiving the first detection signal sent by the integrated circuit, the method further comprises:

determining whether a first detection signal sent by the integrated circuit is received within a first preset time period;

transmitting a second detection signal to the integrated circuit under the condition that a first detection signal transmitted by the integrated circuit is not received within the first preset time period;

and determining whether the integrated circuit fails according to whether the first response signal sent by the integrated circuit is received within a second preset time period.

4. The method of claim 3, wherein determining whether the integrated circuit has failed based on whether the first response signal sent by the integrated circuit is received within a second predetermined period of time comprises:

under the condition that a first response signal sent by the integrated circuit is not received within the second preset time period, determining that the integrated circuit fails;

Under the condition that a first response signal sent by the integrated circuit is received in the second preset time period, sampling the first response signal to obtain a second sampling signal; determining whether the waveforms of the second sampling signal and a preset response signal are consistent; and under the condition that the second sampling signal is consistent with the waveform of the preset response signal, determining that the integrated circuit does not fail.

5. The method of claim 1, wherein after sampling the first detection signal to obtain a first sampled signal, the method further comprises:

determining whether waveforms of the preset detection signal and the first sampling signal are consistent;

determining that the integrated circuit has a fault under the condition that waveforms of the preset detection signal and the first sampling signal are inconsistent;

and sending a reset instruction to the integrated circuit through a reset interface of the integrated circuit so that the integrated circuit executes reset operation according to the reset instruction.

6. The method of claim 1, wherein after sending a fault signal to the multiplexer, the method further comprises:

Acquiring abnormal data of the integrated circuit through a debugging interface of the integrated circuit;

and sending the abnormal data to the server through the connection so that the server analyzes the abnormal data and debugs the integrated circuit according to the analyzed abnormal data.

7. The method of claim 1, wherein after sending the status information of the add-in card to the server over the connection, the method further comprises:

transmitting a third detection signal to the integrated circuit;

determining whether a second response signal sent by the integrated circuit is received within a second preset time period, wherein the second response signal is a signal responding to the third detection signal;

under the condition that a second response signal sent by the integrated circuit is received in the second preset time period, sampling the second response signal to obtain a third sampling signal;

determining whether the waveforms of the third sampling signal and a preset response signal are consistent;

determining that the integrated circuit has recovered from a fault if the third sampling signal is consistent with the waveform of the preset response signal;

And sending a fault recovery signal to the multiplexer so that the multiplexer establishes connection between the integrated circuit and the server according to the fault recovery signal, wherein the fault recovery signal is used for indicating that the integrated circuit breaks down.

8. A system for transmitting status information, comprising:

an integrated circuit, a programmable logic device coupled to the integrated circuit, a multiplexer coupled to the integrated circuit and the programmable logic device, wherein,

the integrated circuit is used for sending a first detection signal to the programmable logic device;

the programmable logic device is configured to sample the first detection signal to obtain a first sampling signal; transmitting a fault signal to the multiplexer in case the waveforms of the first sampling signal and the first detection signal are not identical;

the multiplexer is used for establishing connection between the programmable logic device and a server under the condition of receiving the fault signal;

the programmable logic device is further configured to send status information of an add-in card to the server through the connection, where the integrated circuit and the programmable logic device are both located on the add-in card.

9. A computer readable storage medium, characterized in that a computer program is stored in the computer readable storage medium, wherein the computer program, when being executed by a processor, implements the steps of the method according to any of the claims 1 to 7.

10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method of any one of claims 1 to 7 when the computer program is executed.