CN1170265C - Pulse width modulation device for adjusting brightness contrast of liquid crystal display - Google Patents

Abstract

A pulse width modulation device for adjusting the brightness contrast of a liquid crystal display achieves the purpose of adjusting the brightness contrast by adjusting the on-off period of the scanning waveform of the liquid crystal display. The circuit comprises a counter, a comparator, a T flip-flop, a plurality of inverters and a plurality of AND gates. The circuit is simple, so the occupied circuit area is very small, and the power consumption is very small because the circuit is combined by a digital circuit.

Description

Pulse Width Modulation Device for Bright Contrast Adjustment of Liquid Crystal Displays

Technical field

The present invention relates to a liquid crystal display (LCD), and in particular to an adjustment circuit for adjusting the brightness contrast (Constrast) of the liquid crystal display by means of pulse width modulation, which utilizes a digital control circuit to adjust the on-off of LCD scanning On-Off duty, to achieve bright contrast adjustment, has the advantages of low power consumption, small area and high adjustment rate.

Background technique

In the current electrical system, there are many LCD liquid crystal displays as the interface between man and machine, and due to the needs of use, there is a trend of more and more LCD points. However, the LCD has characteristics related to viewing angle and high voltage, so that the brightness of the LCD cannot be kept constant for users. Therefore, it becomes an important issue for all LCD drivers to adjust the brightness contrast of LCD by the user.

In order to save the number of output ports, high-dot LCDs use more scanning drive circuits, which further reduces the contrast and deteriorates the display effect. General current LCD driving waveforms can be seen in Figure 1. Figure 1 shows a variety of driving waveforms, except for the static type, the rest are scanning types including 1/2 cycle, 1/2 bias voltage; 1/3 cycle, 1/3 bias voltage...etc. How it works can be seen at the bottom of Figure 1. The real voltage felt on the LCD is SEG-COM. It can be found in the figure that except for the static driving method, the other driving methods are not zero voltage when the LCD is off. Angle of view, high voltage level dependence. To solve this problem, an adjustable brightness contrast circuit must be built on the LCD driver to adjust the brightness contrast error caused by voltage drift and user viewing angle changes.

The current bright contrast adjustment circuit is mostly completed by adjusting the operating voltage. The main principle is that the operating voltage (Driving Voltage) in Figure 2 makes the LCD characteristic curve increase the difference in brightness Bns/Bs. It also makes Cr larger (Cr is the bright contrast ratio), and the contrast is enhanced. However, in order to change the operating voltage, it is usually accomplished by a regulator or a resistor divider circuit. However, using a voltage rectifier circuit or a resistor divider circuit will face three problems:

1 Excessive power consumption - due to the existence of a DC path in the voltage adjustment circuit and the power supply, it is impossible to design the DC resistance too small, so the power consumption is very considerable, about 10μA series of power consumption, very Not good for standby use.

2. Circuit difficulty and circuit area are too large.

3. Unable to make fine adjustments - it is difficult to make fine adjustments due to the complexity of the voltage adjustment circuit.

Contents of the invention

Therefore, the present invention proposes a device for adjusting the brightness contrast of a liquid crystal display by modulating the pulse width, which uses the on-off period of the scanning waveform to achieve the purpose of adjusting the brightness contrast. Since the present invention is composed of digital circuits, it not only occupies a very small circuit area, but also consumes very small power, and has a high adjustment rate that cannot be achieved by a voltage rectifier circuit or a resistor divider circuit.

The invention provides a pulse width modulation device for adjusting the bright contrast of a liquid crystal display, which is composed of a counter, a comparator, multiple inverters, multiple "AND" gates, T flip-flops and a node output gate.

Wherein, after receiving a fundamental frequency, the counter generates a first clock, a second clock, a third clock, a fourth clock, a fifth clock, a sixth clock, a seventh clock, and an eighth clock and a ninth clock. The comparator, after receiving the first clock, the second clock, the third clock, the fourth clock, the fifth clock and the sixth clock, respectively compares with the first control signal, the second control signal, the third control signal and the fourth control signal , the fifth control signal and the sixth control signal are compared, and a comparison signal is sent out. The six inverters respectively receive the first clock, the second clock, the third clock, the fourth clock, the fifth clock and the sixth clock, and then respectively send an inverted first clock, an inverted second clock, An inverted third clock, an inverted fourth clock, an inverted fifth clock, and an inverted sixth clock.

In addition, the first AND gate sends out a first output signal after receiving the inverted first clock, the inverted second clock, and the inverted third clock. The second "AND" gate sends out a second output signal after receiving the inverted fourth clock, the inverted fifth clock, and the inverted sixth clock. The third "AND" gate sends out a third output signal after receiving the first output signal and the second output signal. The T flip-flop sends out a pulse width modulation signal after receiving the comparison signal, the third output signal and an input voltage. The first inverter receives the eighth clock and sends out an inverted eighth clock. The second inverter receives the seventh clock and sends out an inverted seventh clock. The third inverter receives the eighth clock and sends out an inverted eighth clock. The fourth inverter receives the seventh clock and sends out an inverted seventh clock.

And the fourth "AND" gate sends out a first common-point output signal after receiving the inverted eighth clock and the inverted seventh clock. The fifth "AND" gate sends out a second common point output signal after receiving the inverted eighth clock and the seventh clock. The sixth "AND" gate sends out a third common-point output signal after receiving the eighth clock and the inverted seventh clock. The seventh "AND" gate sends out a fourth common-point output signal after receiving the eighth clock and the inverted seventh clock. After receiving the pulse width modulation signal and the first common point output signal, the eighth "AND" gate sends out a first modulated common point output signal. After receiving the pulse width modulation signal and the first common point output signal, the ninth "AND" gate sends out a second modulated common point output signal. After receiving the pulse width modulation signal and the first common point output signal, the tenth "AND" gate sends out a third modulated common point output signal. After receiving the pulse width modulation signal and the first common point output signal, the eleventh "AND" gate sends out a fourth modulated common point output signal. and a node output gate, which sends out a node signal.

The above circuit modulates the common point output signal, and can also modulate the node signal. The pulse width modulation device for adjusting the bright contrast of the liquid crystal display can be modified as follows:

After the counter receives a fundamental frequency, it generates a first clock, a second clock, a third clock, a fourth clock, a fifth clock, a sixth clock, a seventh clock, an eighth clock, and a first clock. Nine clocks. The comparator, after receiving the first clock, the second clock, the third clock, the fourth clock, the fifth clock and the sixth clock, respectively compares with a first control signal, a second control signal, a third control signal, a After the fourth control signal, a fifth control signal and a sixth control signal are compared, a comparison signal is sent out. After receiving the first clock, the second clock, the third clock, the fourth clock, the fifth clock and the sixth clock respectively, the six inverters respectively send out an inverted first clock, an inverted second clock, and an inverted second clock. An inverted third clock, an inverted fourth clock, an inverted fifth clock, and an inverted sixth clock.

As for, the first "AND" gate sends out a first output signal after receiving the inverted first clock, the inverted second clock, and the inverted third clock. The second "AND" gate sends out a second output signal after receiving the inverted fourth clock, the inverted fifth clock, and the inverted sixth clock. The third "AND" gate sends out a third output signal after receiving the first output signal and the second output signal. After receiving the comparison signal, the third output signal and the input voltage, the T flip-flop sends out a pulse width modulation signal.

The first inverter receives the eighth clock and sends out an inverted eighth clock. The second inverter receives the seventh clock and sends out an inverted seventh clock. The third inverter receives the eighth clock and sends out an inverted eighth clock. The fourth inverter receives the seventh clock and sends out an inverted seventh clock. The fourth "AND" gate sends out a first common-point output signal after receiving the inverted eighth clock and the inverted seventh clock. The fifth "AND" gate sends out a second common point output signal after receiving the inverted eighth clock and the seventh clock. The sixth "AND" gate sends out a third common-point output signal after receiving the eighth clock and the inverted seventh clock. The seventh "AND" gate sends out a fourth common point output signal after receiving the eighth clock and the seventh clock. The node output gate sends out a node signal. And the nineteenth "AND" gate, after receiving the node signal and the PWM signal, sends out a modulated node signal.

In addition, the above two circuits can also be combined, that is, the common point output signal and the node signal are simultaneously modulated, and the corresponding pulse width modulation device for adjusting the brightness contrast of the liquid crystal display is as follows:

After the counter receives a fundamental frequency, it generates a first clock, a second clock, a third clock, a fourth clock, a fifth clock, a sixth clock, a seventh clock, an eighth clock, and a first clock. Nine clocks. After receiving the first clock, the second clock, the third clock, the fourth clock, the fifth clock and the sixth clock, the comparator respectively compares with a first control signal, a second control signal, a third control signal, a first After comparing the four control signals, the fifth control signal and the sixth control signal, a comparison signal is sent out. The six inverters respectively receive the first clock, the second clock, the third clock, the fourth clock, the fifth clock and the sixth clock, and then respectively send an inverted first clock, an inverted second clock, An inverted third clock, an inverted fourth clock, an inverted fifth clock, and an inverted sixth clock.

As for, the first "AND" gate sends out a first output signal after receiving the inverted first clock, the inverted second clock, and the inverted third clock. The second "AND" gate sends out a second output signal after receiving the inverted fourth clock, the inverted fifth clock, and the inverted sixth clock. The third "AND" gate sends out a third output signal after receiving the first output signal and the second output signal. The T flip-flop sends out a pulse width modulation signal after receiving the comparison signal, the third output signal and an input voltage. The first inverter receives the eighth clock and sends out an inverted eighth clock. The second inverter receives the seventh clock and sends out an inverted seventh clock; the third inverter receives the eighth clock and sends out an inverted eighth clock. The fourth inverter receives the seventh clock and sends out the inverted seventh clock.

And the fourth "AND" gate sends out a first common-point output signal after receiving the inverted eighth clock and the inverted seventh clock. The fifth "AND" gate sends out a second common point output signal after receiving the inverted eighth clock and the seventh clock. The sixth "AND" gate sends out a third common-point output signal after receiving the eighth clock and the inverted seventh clock. The seventh "AND" gate sends out a fourth common point output signal after receiving the eighth clock and the seventh clock. After receiving the pulse width modulation signal and the first common point output signal, the eighth "AND" gate sends out a first modulated common point output signal. After receiving the pulse width modulation signal and the first common point output signal, the ninth "AND" gate sends out a second modulated common point output signal. After receiving the pulse width modulation signal and the first common point output signal, the tenth "AND" gate sends out a third modulated common point output signal. After receiving the pulse width modulation signal and the first common point output signal, the eleventh "AND" gate sends out a fourth modulated common point output signal. In addition, the node output gate sends out a node signal. And the nineteenth "AND" gate sends out a modulated node signal after receiving the node signal and the PWM signal.

In addition, the present invention is modified slightly to output a voltage at the same level as the control node signal and the common point signal output, so that the contrast can be further improved. The pulse width modulation device for adjusting the bright contrast of a liquid crystal display has the following structure:

After the counter receives a fundamental frequency, it generates a first clock, a second clock, a third clock, a fourth clock, a fifth clock, a sixth clock, a seventh clock, an eighth clock, and a first clock. Nine clocks. After receiving the first clock, the second clock, the third clock, the fourth clock, the fifth clock and the sixth clock, the comparator respectively compares with a first control signal, a second control signal, a third control signal, a first After comparing the four control signals, the fifth control signal and the sixth control signal, a comparison signal is sent out. After receiving the first clock, the second clock, the third clock, the fourth clock, the fifth clock and the sixth clock respectively, the six inverters respectively send out an inverted first clock, an inverted second clock, and an inverted second clock. An inverted third clock, an inverted fourth clock, an inverted fifth clock, and an inverted sixth clock.

As for, the first "AND" gate sends out a first output signal after receiving the inverted first clock, the inverted second clock, and the inverted third clock. The second "AND" gate sends out a second output signal after receiving the inverted fourth clock, the inverted fifth clock, and the inverted sixth clock. The third "AND" gate sends out a third output signal after receiving the first output signal and the second output signal. The T flip-flop sends out a pulse width modulation signal after receiving the comparison signal, the third output signal and an input voltage. The first inverter receives the eighth clock and sends out an inverted eighth clock. The second inverter receives the seventh clock and sends out an inverted seventh clock. The third inverter receives the eighth clock and sends out an inverted eighth clock. The fourth inverter receives the seventh clock and sends out an inverted seventh clock. The fourth "AND" gate sends out a first common-point output signal after receiving the inverted eighth clock and the inverted seventh clock. The fifth "AND" gate sends out a second common point output signal after receiving the inverted eighth clock and the seventh clock. The sixth "AND" gate sends out a third common-point output signal after receiving the eighth clock and the inverted seventh clock. The seventh "AND" gate sends out a fourth common point output signal after receiving the eighth clock and the seventh clock. The node output gate sends out a node signal. And the fifth inverter sends out an inverted pulse width modulation signal after receiving the pulse width modulation signal to control the node signal and the common point signal to output the same level voltage.

The above four different types all have the same counter, the internal structure of which is sent out the first clock after the first T flip-flop receives the base frequency and the input voltage. After receiving the fundamental frequency and the first clock, the second T flip-flop sends out the second clock. The twelfth "AND" gate sends out a first control output signal after receiving the first clock and the second clock. After receiving the fundamental frequency and the first control output signal, the third T flip-flop sends out the third clock. The thirteenth "AND" gate sends out a second control output signal after receiving the first control output signal and the third clock. The fourth T flip-flop sends out a fourth clock after receiving the base frequency and the second control output signal. The fourteenth "AND" gate sends out a third control output signal after receiving the second control output signal and the fourth clock. The fifth T flip-flop sends out the fifth clock after receiving the base frequency and the third control output signal. After receiving the third control output signal and the fifth clock, the fifteenth "AND" gate sends out the fourth control output signal. The sixth T flip-flop sends out the sixth clock after receiving the base frequency and the fourth control output signal. The sixteenth "AND" gate sends out a fifth control output signal after receiving the fourth control output signal and the sixth clock. The seventh T flip-flop sends out the seventh clock after receiving the base frequency and the fifth control output signal. The seventeenth "AND" gate sends out a sixth control output signal after receiving the fifth control output signal and the seventh clock. The eighth T flip-flop sends out the eighth clock after receiving the fundamental frequency and the sixth control output signal. The eighteenth "AND" gate sends out a seventh control output signal after receiving the sixth control output signal and the eighth clock. And the ninth T flip-flop sends out the ninth clock after receiving the fundamental frequency and the seventh control output signal.

In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, the preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows:

            

Figure 1 shows the waveform output by the LCD driver;

Fig. 2 shows the graph of Bns and Bs curves of luminance under the coordinates of operating voltage and luminance;

Figure 3 shows the off waveform of the LCD display at com0 scanning time in the scan mode of 1/3 bias (bias) and 1/4 cycle (duty);

Figure 4 shows the waveform of the LCD displaying on in the scan time of com1 with 1/3 bias voltage and 1/4 cycle scan mode;

FIG. 5 shows a pulse width modulation device for adjusting the brightness contrast of a liquid crystal display according to a preferred embodiment of the present invention;

Figure 6 shows the off waveform displayed on the LCD during the scan time of COM0 after adjusting the pulse width of the output common;

Figure 7 shows the waveform of the LCD displaying on during COM1 scan time after adjusting the pulse width of the output common;

FIG. 8 shows a second type pulse width modulation device for adjusting the bright contrast of a liquid crystal display according to the present invention;

Figure 9 shows the waveform of LCD display off during COM0 scan time after adjusting the pulse width of the output segment;

Figure 10 shows the waveform of the LCD displaying on during COM1 scan time after adjusting the pulse width of the output segment;

FIG. 11 shows a third type pulse width modulation device for adjusting the bright contrast of a liquid crystal display according to the present invention;

Figure 12 shows the off waveform displayed on the LCD during the scan time of COM0 after adjusting the output pulse widths of common and segment at the same time;

Figure 13 shows the waveform of the LCD displaying on during COM1 scan time after adjusting the pulse width of the output common and segment at the same time;

FIG. 14 shows a fourth pulse width modulation device for adjusting the brightness contrast of a liquid crystal display according to the present invention;

Fig. 15 shows the waveform of LCD display off during COM0 scan time; and

Figure 16 shows the waveform of LCD display on during COM1 scan time.

Detailed ways

Generally speaking, the waveform output by the LCD driver is shown in Figure 1, which can be divided into two categories - static type and scanning type (or multiplexing type). The static output is a relatively simple single-point control, and its Vrms value is as follows:

$\mathrm{Vrms}-\mathrm{on}=\sqrt{1/2}\mathrm{Vops}$ Vrms-off=0 (Vop is the maximum output voltage)

The scanning Vrms value is related to the number of bias voltages and the number of cycles. The scanning method is that the commonpin (com) outputs a scanning waveform, and performs time-sharing scanning on the segment (seg) output signal. As for the voltage sensed by the LCD panel (panel), it is actually the voltage difference of seg-com, so as long as the voltage difference of seg-com can be made large enough within the common scan time, the LCD panel can be reversed immediately, resulting in Light cannot pass through to show. As for its Vrms is affected by the common number (duty number) and the bias voltage (Bias number), for example, a 1/4 cycle, 1/3 bias LCD driver (Driver) waveform is shown in Figure 3 and Figure 4 . Figure 3 shows the waveform of LCD display off during com0 scan time. Figure 4 shows the waveform of LCD display display on during com1 scan time. Its Vrms value is as follows:

Vrms-on＝(1/4*(1/2Vop) ² +1/4(1/6Vop) ² +1/4(-1/6Vop) ² +1/4(1/2Vop) ² ) ^1/2 ＝√1/12Vop

Vrms-off＝(1/4*(1/6Vop) ² +1/4(1/6Vop) ² +1/4(-1/6Vop) ² +1/4(-1/6Vop) ² ) ^{1/ 2} ＝√1/36Vop (Vop maximum output voltage)

Vrms-on/Vrms-off＝√3＝1.7321

Since the brightness of the LCD panel depends on the Vrms value of the panel's perceived voltage difference, different Vrms correspond to a measured brightness value. Generally, we define the contrast ratio (Contrast Ratio) as the brightness value at the time of on-off (On-Off)

Cr=Bon/Boff

while contrast is defined as 1 minus the reciprocal of the contrast ratio

C=1-1/Cr

So if the Bon value is bigger, Cr goes up and C goes up. The smaller the Boff value, the higher the Cr value and the higher the C. And the value of Bon and Boff is proportional to Vrms, so to adjust the brightness, it is necessary to increase the value of Vrms-on, so that Bon rises. To adjust the contrast, it is necessary to find a way to increase Vrms-on, decrease Vrms-off, increase Bon, and decrease Boff.

In addition to being affected by Vrms, the characteristics of the LCD panel are also affected by the viewing angle, that is, under the same Vrms, different viewing angles will result in different brightness values.

Due to the above-mentioned characteristics, the current liquid crystal display faces the problem of changing brightness value and contrast value. Mainly due to changes in supply voltage and viewing angle. Because the change of supply voltage will cause the change of Vrms, so the brightness and contrast will change accordingly. And the user's viewing angle cannot be determined, so an optimal LCD driver should include a circuit for the user to set the brightness by himself, and the user can set it according to the current situation. So a LCD driver with adjustable brightness comes into being.

The current adjustable brightness LCD driver processing principle is mostly handled from the value of controlling the Vop voltage. The practices can be divided into two categories. The first type uses a resistor divider network to attenuate and adjust the Vop value. That is, a string of resistors is built inside, and the electrical signal is used to control the value of the string of resistors. Because of the effect of resistor voltage division, the Vop value will be adjusted. As for the method, some are added to the position of the internal power supply, and some are added to the output of Common and Segment. The second type uses a voltage regulator (Regulator), and a voltage regulator with adjustable voltage output value is designed at the position of the internal power supply, and the Vop value is adjusted by adjusting the voltage output value. Regardless of the above-mentioned circuit design, there will be disadvantages of high power consumption, high circuit complexity, and difficulty in designing multi-stage adjustable circuits. Therefore, the present invention proposes a digital rectifying circuit to adjust the brightness and contrast, and uses the low power consumption, low complexity, low area and high adjustability of the CMOS digital circuit to overcome the problems of the current method.

The method proposed by the present invention is not to adjust Vop, but to adjust the pulse width of its output waveform. Therefore, in Figure 1, the width of the waveform on is corrected from 100% to n%, causing Vrms to change accordingly, just like adjusting Vop, so that the brightness changes accordingly.

Next, a pulse width modulation device for adjusting the brightness contrast of a liquid crystal display according to a preferred embodiment of the present invention is shown in FIG. 5 . Including a counter 10, a comparator 12, six inverters 14-24, the first "AND" gate 25, the second "AND" gate 26, the third "AND" gate 28, T flip-flop 30, multiple Inverters 32-38, a plurality of "AND" gates 40-54, node output gate 56 constitute.

Among them, after the counter receives a base frequency (for example, a clock CLK 32768 (frequency is 32768Hz)) and an input voltage (Vcc), it uses a plurality of T flip-flops 58-74 and a plurality of "AND" gates 76-88 to generate the first The first clock CLK 16384, the second clock CLK 8192, the third clock CLK 4096, the fourth clock CLK 2048, the fifth clock CLK 1024, the sixth clock CLK 512, the seventh clock CLK256, the eighth clock CLK 128 and the ninth clock FR .

Its structure is that the first T flip-flop 58 sends out the first clock CLK 16384 after receiving the base frequency CLK 32768 and the input voltage Vcc. After receiving the base frequency CLK 32768 and the first clock CLK 16384, the second T flip-flop 60 sends out the second clock CLK 8192. The twelfth "AND" gate 76 sends out the first control output signal 100 after receiving the first clock CLK 16384 and the second clock CLK 8192. The third T flip-flop 62 sends out the third clock CLK 4096 after receiving the base frequency CLK 32768 and the first control output signal 100. The thirteenth "AND" gate 78 sends out the second control output signal 102 after receiving the first control output signal 100 and the third clock CLK 4096. The fourth T flip-flop 66 sends out the fourth clock CLK 2048 after receiving the base frequency CLK32768 and the second control output signal 102 . The fourteenth "AND" gate 80 sends out the third control output signal 104 after receiving the second control output signal 102 and the fourth clock CLK 2048. The fifth T flip-flop 66 sends out the fifth clock CLK 1024 after receiving the base frequency CLK 32768 and the third control output signal 104. The fifteenth "AND" gate 82 sends out the fourth control output signal 106 after receiving the third control output signal 104 and the fifth clock CLK 1024. The sixth T flip-flop 68 sends out the sixth clock CLK 512 after receiving the base frequency CLK 32768 and the fourth control output signal 106 . The sixteenth "AND" gate 84 sends out the fifth control output signal 108 after receiving the fourth control output signal 106 and the sixth clock CLK 512. The seventh T flip-flop 70 sends out the seventh clock CLK 256 after receiving the base frequency CLK 32768 and the fifth control output signal 108. The seventeenth "AND" gate 86 sends out the sixth control output signal 110 after receiving the fifth control output signal 108 and the seventh clock CLK 256. The eighth T flip-flop 72 sends out the eighth clock CLK 128 after receiving the base frequency CLK 32768 and the sixth control output signal 110. The eighteenth AND gate 88 sends out the seventh control output signal 112 after receiving the sixth control output signal 110 and the eighth clock CLK128 . After receiving the base frequency CLK 32768 and the seventh control output signal 112, the ninth T flip-flop 74 sends out the ninth clock FR.

The comparator CMP6 receives the first clock CLK 16348, the second clock CLK 8192, the third clock CLK 4096, the fourth clock CLK 2048, the fifth clock CLK 1024 and the sixth clock CLK 512, respectively, and the first control signal TUNE0 , a second control signal TUNE1 , a third control signal TUNE2 , a fourth control signal TUNE3 , a fifth control signal TUNE4 , and a sixth control signal TUNE5 are compared, and a comparison signal EQ is sent out.

As for the six inverters 16-22, after respectively receiving the first clock CLK 16348, the second clock CLK 8192, the third clock CLK 4096, the fourth clock CLK 2048, the fifth clock CLK 1024 and the sixth clock CLK 512, Then send an inverted first clock, an inverted second clock, and an inverted third clock to the first "AND" gate 25, and send an inverted fourth clock, an inverted fifth clock, and an inverted clock. phase the sixth clock to the second AND gate 26 . And the first output signal 114 sent by the first "AND" gate 25 and the second output signal 116 sent by the second "AND" gate 26 are input to the third "AND" gate 28, and then a third output signal 118 is sent out . Next, the T flip-flop 30 sends out a pulse width modulation signal 120 after receiving the comparison signal EQ, the third output signal 118 and the input voltage Vcc.

In addition, after receiving the eighth clock CLK 128, the first inverter 32 sends out an inverted eighth clock. The second inverter receives the seventh clock CLK 256 and sends out an inverted seventh clock. The third inverter receives the eighth clock CLK 128 and sends out an inverted eighth clock. The fourth inverter receives the seventh clock CLK 256 and sends out an inverted seventh clock. The fourth "AND" gate 40 sends out a first common point output signal NM-COM0 after receiving the inverted eighth clock and the inverted seventh clock. The fifth AND gate 42 sends out the second common point output signal NM-COM1 after receiving the inverted eighth clock and the seventh clock. The sixth AND gate 44 sends out the third common point output signal NM-COM2 after receiving the eighth clock and the inverted seventh clock. The seventh "AND" gate 46 sends out the fourth common point output signal NM-COM3 after receiving the eighth clock and the seventh clock. Next, in the next stage, the eighth AND gate 48 sends out the first modulated common output signal COM0 after receiving the pulse width modulation signal 120 and the first common output signal NM-COM0 . The ninth AND gate 50 sends out the second modulated common output signal COM1 after receiving the pulse width modulation signal 120 and the second common output signal NM-COM1 . The tenth AND gate 52 sends out the third modulated common output signal COM2 after receiving the pulse width modulation signal 120 and the third common output signal NM-COM2 . The eleventh AND gate 54 sends out the fourth modulated common output signal COM3 after receiving the PWM signal 120 and the fourth common output signal NM-COM3 . And the node output gate 56 sends out a node signal SEG.

Under the operation of the above circuit, to adjust the pulse width of the output common, we can use the waveform of the LCD displaying off at the scanning time of COM0 in Figure 3 and Figure 6 to show that after adjusting the pulse width of the output common, the LCD displaying off at the scanning time of COM0 For comparison, the waveform of COM0 changes, so that the waveform output by COM-SEG also changes. Similarly, the original figure 4 shows the waveform of the LCD displaying on during the scan time of com1, and Figure 7 shows the waveform of the LCD displaying on during the scan time of COM1 after adjusting the pulse width of the output common. By comparison, the waveform of COM0 changes , so that the waveform output by COM-SEG also changes.

In order to further clarify the impact of adjusting the pulse width, we adjust the width of common on when on, and reduce it from 100% to n%, then Vrms is corrected as follows: Static: $\mathrm{Vrms}-\mathrm{on}=\sqrt{1/2\mathrm{no}/100}\mathrm{Vops}$ Vrms-off=0 and 1/4 cycle, 1/3 bias graph is corrected in Figure 6 and Figure 7

$\mathrm{<span\; class="notranslate">\; Vrms</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; on</span>}<span\; class="notranslate">\; =</span>$

$<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 100</span>}<span\; class="notranslate">\; *</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; Vops</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; *</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 100</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 100</span>}<span\; class="notranslate">\; *</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 6</span>}\mathrm{<span\; class="notranslate">\; Vops</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; *</span>{<span\; class="notranslate">\; (</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 6</span>}\mathrm{<span\; class="notranslate">\; Vops</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

$<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; *</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 6</span>}\mathrm{<span\; class="notranslate">\; Vops</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; *</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 6</span>}\mathrm{<span\; class="notranslate">\; Vops</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}}$

$<span\; class="notranslate">\; =</span>\sqrt{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 8</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 100</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 144</span>}}\mathrm{<span\; class="notranslate">\; Vops</span>}$

$\mathrm{<span\; class="notranslate">\; Vrms</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; off</span>}<span\; class="notranslate">\; =</span>\sqrt{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 36</span>}}\mathrm{<span\; class="notranslate">\; Vops</span>}$

Therefore, by adjusting the width of the common output waveform, the voltage difference of Vrms-on can be adjusted, that is, the brightness is adjusted. Figure 5 and Figure 6 are the result of adjusting the pulse width to 50% to adjust the driving circuit of 1/3 bias voltage 1/4 cycle. as a result

$\mathrm{<span\; class="notranslate">\; Vrms</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; on</span>}<span\; class="notranslate">\; =</span>\sqrt{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 18</span>}}\mathrm{<span\; class="notranslate">\; Vops</span>}$

$\mathrm{<span\; class="notranslate">\; Vrms</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; off</span>}<span\; class="notranslate">\; =</span>\sqrt{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 36</span>}}\mathrm{<span\; class="notranslate">\; Vops</span>}$

In addition, we can also perform width modulation on the power-saving signal output by the segment to form the second type of pulse width modulation device for adjusting the bright contrast of the liquid crystal display of the present invention, as shown in Figure 8, which is the same as Figure 5 The constituent parts include a counter 10, a comparator 12, six inverters 14-24, a first "AND" gate 25, a second "AND" gate 26, a third "AND" gate 28, a T flip-flop 30, It is composed of a plurality of inverters 32-38, a plurality of "AND" gates 40-46, and a node output gate 56. The difference part is removing the original multiple "AND" gates 48-54, and adding a nineteenth "AND" gate 90.

Since there are many similarities in the above-mentioned structures, the description of the connection relationship will not be repeated here, and further description will be given for the different places. Because the second type of pulse width modulation device for adjusting the bright contrast of the liquid crystal display is to adjust the waveform width of the output segment, the pulse width modulation signal 120 originally output by the T flip-flop 30 will be sent to a node by the AND node output gate 56. The signal SEG is simultaneously input to the nineteenth "AND" gate 90 to generate a modulation node signal SEG', instead of using the pulse width modulation signal 120 in FIG. 5 to adjust the width of the common output waveform.

The above circuit adjusts the width of the segment output when it is on. As shown in Figure 9 and Figure 10, after adjusting the pulse width of the output segment, the LCD displays the off waveform during the scanning time of COM0, and after adjusting the pulse width of the output segment, COM1 scans In time, the LCD displays the on waveform. Comparing with Figures 3 and 4 respectively, we can find that the waveform of SEG changes, which makes the waveform output by COM-SEG also change.

In order to further clarify the impact of adjusting the pulse width, we adjust the width of segment on when on, for example, from 100% to n%, then Vrms is corrected as follows:

$\mathrm{<span\; class="notranslate">\; Vrms</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; on</span>}<span\; class="notranslate">\; =</span>$

$<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 100</span>}<span\; class="notranslate">\; *</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; Vops</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; *</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 100</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 100</span>}<span\; class="notranslate">\; *</span>{<span\; class="notranslate">\; (</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 6</span>}\mathrm{<span\; class="notranslate">\; Vops</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 4</span>}{<span\; class="notranslate">\; (</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 6</span>}\mathrm{<span\; class="notranslate">\; Vops</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

$<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 4</span>}{<span\; class="notranslate">\; (</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 6</span>}\mathrm{<span\; class="notranslate">\; Vops</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 4</span>}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 6</span>}\mathrm{<span\; class="notranslate">\; Vops</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}}$

$<span\; class="notranslate">\; =</span>\sqrt{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 8</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 100</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 144</span>}}\mathrm{<span\; class="notranslate">\; Vops</span>}$

$\mathrm{<span\; class="notranslate">\; Vrms</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; off</span>}<span\; class="notranslate">\; =</span>\sqrt{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 36</span>}}\mathrm{<span\; class="notranslate">\; Vops</span>}$

We can obtain the same effect as the pulse width modulation device of the above-mentioned invention for adjusting the bright contrast of the liquid crystal display, thereby achieving the purpose of adjusting the brightness.

Similarly, we can use the above two in combination, that is, adjust the common and the segment at the same time, as shown in FIG. 11 , which is the third type of pulse width modulation device for adjusting the bright contrast of the liquid crystal display of the present invention. We can see that the third type pulse width modulation device for adjusting the bright contrast of a liquid crystal display of the present invention is a combination of the pulse width modulation device for adjusting the bright contrast of a liquid crystal display of FIG. 5 and FIG. The pulse width modulation signal 120 is not only output to the "AND" gates 48-54 as shown in Fig. The modulated signal 120 sends a node signal SEG from the AND node output gate 56, which is input to the nineteenth "AND" gate 90 at the same time to generate a modulated node signal SEG'. As for other similar structural parts, since they have the same effect as the above two, the description of the connection relationship will not be repeated here.

The above circuit adjusts the width of the segment and common outputs when they are on. As shown in Figure 12 and Figure 13, after adjusting the pulse width of the output segment and common, the LCD displays the off waveform during the scan time of COM0, and adjusts the output segment and common. After the pulse width, the LCD displays the on waveform on the COM1 scan time. Comparing with Figures 3 and 4 respectively, we can find that the waveforms of COM and SEG change, which makes the waveform generated by COM-SEG also change.

In order to further clarify the impact of adjusting the pulse width, we adjust the width of segment and common on when on, for example, from 100% to n%, then Vrms is corrected as follows:

$\mathrm{<span\; class="notranslate">\; Vrms</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; on</span>}<span\; class="notranslate">\; =</span>\sqrt{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 8</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 100</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 144</span>}}\mathrm{<span\; class="notranslate">\; Vops</span>}$

$\mathrm{<span\; class="notranslate">\; Vrms</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; off</span>}<span\; class="notranslate">\; =</span>\sqrt{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 36</span>}}\mathrm{<span\; class="notranslate">\; Vops</span>}$

The same result is obtained in the above three ways, that is, the Vrms-on is attenuated, causing the brightness to be attenuated, and the contrast is also attenuated. The brightness can be compensated by the Vop, although the loss of contrast cannot be remedied. That is, increase the fixed Vop voltage, or reduce the initial voltage value of the LCD panel. For example, such as an application using a battery as a power source. The battery voltage value varies by ±10%, so Vop also varies by ±10%. We take the lowest voltage 0.9Vop as the center of the design. That is to design a condition of n=100 to adapt to the power supply of 0.9Vop, and to design an LCD panel $\mathrm{Vrms}-\mathrm{on}=0.9\mathrm{Vops}\sqrt{1/12}.$ To get the same brightness when the power supply is normal (Vop), then n must be determined by

$\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 0.9</span>}<span\; class="notranslate">\; *</span>\sqrt{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; 144</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; 100</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 71.5</span>}$

And when the power supply is increased to 1.1Vop, n is

$\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 1.1</span>}<span\; class="notranslate">\; =</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 10.9</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 1.1</span>}<span\; class="notranslate">\; *</span>\sqrt{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 12</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; 144</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; 100</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 50.4134</span>}$

Of course, in this method, Vrms-off cannot be changed by adjusting the pulse width n%, so Von/Voff will decrease, resulting in a decrease in brightness contrast, because the relationship between brightness and voltage difference is nonlinear. So we can sacrifice a small part of the brightness contrast drop to obtain a high degree of brightness adjustment. As for the design of the circuit, it is composed of the above three circuits. Wherein the basic frequency is oscillating at 32768, for example, and the formed circuit with a frame ratio of 64 Hz is shown in FIG. 5 , FIG. 8 , and FIG. 11 . We can see that it is controlled by a whole digital circuit, so the power consumption and circuit area are very small. In Fig. 5 , Fig. 8 , and Fig. 11 above, the pulse width can be adjusted by 2 ⁶ =64 steps in total, which cannot be achieved by the current adjustment circuit.

The above-mentioned three types of circuits all have a common feature, that is, Vrms-off is a certain value, which cannot be changed by the pulse width ratio, so the contrast will decrease accordingly. Therefore, the present invention proposes a fourth pulse width modulation device for adjusting the brightness contrast of a liquid crystal display to improve the above situation.

FIG. 14 shows a fourth type of pulse width modulation device for adjusting the brightness contrast of a liquid crystal display according to the present invention. We can find that the difference from the above-mentioned Fig. 5, Fig. 8, and Fig. 11 is that the pulse width modulation signal 120 output by the T flip-flop 30 is sent to the fifth inverter, and then an inverted pulse width modulation signal 120 is generated. The variable signal DISLCD is used to control the node signal and the common point signal to output the same level voltage. That is, the DISLCD signal controls the multiplier (Multiplier) of the external 4 channels (Channel), so that both the common and the segment output the same voltage, so the voltage difference is 0.

Next, in FIGS. 15 and 16, it can be seen that the output waveform of the fourth type pulse width modulation device for adjusting the bright contrast of the liquid crystal display. The basic idea is that when we adjust the waveform width to off, all points are actually off, so we can pull all common and segment outputs to the same potential. That is to output a Disable signal, output the multiplexing voltage of the Driver LCD part to a fixed voltage or turn off the bias circuit. Its detailed Vrms are as follows:

$\mathrm{<span\; class="notranslate">\; Vrms</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; on</span>}<span\; class="notranslate">\; =</span>$

$<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 100</span>}<span\; class="notranslate">\; *</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; Vops</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 100</span>}<span\; class="notranslate">\; *</span>{<span\; class="notranslate">\; (</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 6</span>}\mathrm{<span\; class="notranslate">\; Vops</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 4</span>}{<span\; class="notranslate">\; (</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 6</span>}\mathrm{<span\; class="notranslate">\; Vops</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

$<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 4</span>}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 6</span>}\mathrm{<span\; class="notranslate">\; Vops</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}}\sqrt{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 100</span>}}\mathrm{<span\; class="notranslate">\; Vops</span>}$

$\mathrm{<span\; class="notranslate">\; Vrms</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; off</span>}<span\; class="notranslate">\; =</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 100</span>}<span\; class="notranslate">\; *</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; Vops</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 2</span>}}$

$<span\; class="notranslate">\; =</span>\sqrt{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 36</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 100</span>}}\mathrm{<span\; class="notranslate">\; Vops</span>}$

It can be found from the above formula that when the value of n becomes smaller, Vrms-on becomes smaller, and Vrms-off also becomes smaller. That $\mathrm{Vrms}-\mathrm{on}/\mathrm{Vrms}-\mathrm{off}=\sqrt{3}=1.7321,$ Equal to the original unadjusted value. That is to say, Vrms-on/Vrms-off will not be changed by adjusting the brightness at all. This makes the performance of Type Fours very advantageous. Compared with the current method of adjusting Vop, the fourth type can be equivalent to an adjustment voltage value Vequ-op

$\mathrm{<span\; class="notranslate">\; Vequ</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; op</span>}<span\; class="notranslate">\; =</span>\sqrt{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; 100</span>}}\mathrm{<span\; class="notranslate">\; Vops</span>}$

Utilizing this Vequ-op, an optimal bright contrast ratio can be matched by the driving (Drive) voltage in FIG. 2 .

For example, the variable power of ±10% in the above example can be compensated by the variation of n value. The result is as follows:

n0.9=100

n1=81

n1.1=66.94

That is to say, the adjustment of n value can be used to match the change of power without changing any performance. And the contrast (Contrast) does not change, and the same change in viewing angle becomes a change in brightness contrast, which can also be compensated by this method. The fourth type of adjustment circuit not only has the benefits of the first three types, but also overcomes the ghost effect that may be caused by the failure of Vrms-off to decrease. Compared with the current methods, it has the advantages of low power consumption, low circuit complexity, low cost and high adjustable rate.

In summary, the present invention adjusts the bright contrast device of the liquid crystal display by modulating the pulse width, and constitutes a digital circuit with a counter, a comparator, a T flip-flop, a plurality of inverters and a plurality of "AND" gates, not only The circuit area is very small, and the power consumption is also very small, and it has a high adjustment rate that cannot be achieved by a voltage regulator circuit or a resistor divider circuit. And in the fourth type, by adjusting the output voltage, not only the bright contrast can be increased, but also the ghost phenomenon can be eliminated.

Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make various modifications and modifications without departing from the spirit and scope of the present invention. , so the protection scope of the present invention should be defined by the claims.

Claims (8)

1. adjust the bright pulse width modulation device that contrasts of LCD for one kind, comprising:

One counter, receive a fundamental frequency after, produce one first clock, a second clock, one the 3rd clock, one the 4th clock, one the 5th clock, one the 6th clock, one the 7th clock, one the 8th clock and one the 9th clock;

One comparer, after receiving this first clock, this second clock, the 3rd clock, the 4th clock, the 5th clock and the 6th clock, respectively with one first control signal, one second control signal, one the 3rd control signal, one the 4th control signal, one the 5th control signal and one the 6th control signal relatively after, send a comparison signal;

Six phase inverters, after receiving this first clock, this second clock, the 3rd clock, the 4th clock, the 5th clock and the 6th clock respectively, send anti-phase first clock, an anti-phase second clock, anti-phase the 3rd clock, anti-phase the 4th clock, anti-phase the 5th clock and anti-phase the 6th clock more respectively;

One first AND gate, receive this anti-phase first clock, this anti-phase second clock and anti-phase the 3rd clock after, send one first output signal;

One second AND gate, receive this anti-phase the 4th clock, this anti-phase the 5th clock and this anti-phase the 6th clock after, send one second output signal;

One the 3rd AND gate, receive this first output signal and this second output signal after, send one the 3rd output signal;

One T trigger, receive this comparison signal, the 3rd output signal and an input voltage after, send a pulse width modulation signal;

One first phase inverter receives the 8th clock, sends anti-phase the 8th clock;

One second phase inverter receives the 7th clock, sends anti-phase the 7th clock;

One the 3rd phase inverter receives the 8th clock, sends this anti-phase the 8th clock;

One the 4th phase inverter receives the 7th clock, sends this anti-phase the 7th clock;

One the 4th AND gate, receive this anti-phase the 8th clock and this anti-phase the 7th clock after, send one first concurrent output signal;

One the 5th AND gate, receive this anti-phase the 8th clock and the 7th clock after, send one second concurrent output signal;

One the 6th AND gate, receive the 8th clock and this anti-phase the 7th clock after, send one the 3rd concurrent output signal;

One the 7th AND gate, receive the 8th clock and the 7th clock after, send one the 4th concurrent output signal;

One the 8th AND gate, receive this pulse width modulation signal and this first concurrent output signal after, send one first modulation concurrent output signal;

One the 9th AND gate, receive this pulse width modulation signal and this second concurrent output signal after, send one second modulation concurrent output signal;

The tenth AND gate, receive this pulse width modulation signal and the 3rd concurrent output signal after, send one the 3rd modulation concurrent output signal;

The 11 AND gate, receive this pulse width modulation signal and the 4th concurrent output signal after, send one the 4th modulation concurrent output signal; And

One node out gate is sent a node signal.

2. the pulse width modulation device of the bright contrast of adjustment LCD as claimed in claim 1, wherein this counter comprises:

One the one T trigger, receive this fundamental frequency and this input voltage after, send this first clock;

One the 2nd T trigger, receive this fundamental frequency and this first clock after, send this second clock;

The 12 AND gate, receive this first clock and this second clock after, send one first control output signal;

One the 3rd T trigger, receive this fundamental frequency and this first control output signal after, send the 3rd clock;

The 13 AND gate, receive this first control output signal and the 3rd clock after, send one second and control output signal;

One the 4th T trigger, receive this fundamental frequency and this second control output signal after, send the 4th clock;

The 14 AND gate, receive this second control output signal and the 4th clock after, send one the 3rd and control output signal;

One the 5th T trigger, receive this fundamental frequency and the 3rd control output signal after, send the 5th clock;

The 15 AND gate, receive the 3rd control output signal and the 5th clock after, send one the 4th and control output signal;

One the 6th T trigger, receive this fundamental frequency and the 4th control output signal after, send the 6th clock;

The 16 AND gate, receive the 4th control output signal and the 6th clock after, send one the 5th and control output signal;

One the 7th T trigger, receive this fundamental frequency and the 5th control output signal after, send the 7th clock;

The 17 AND gate, receive the 5th control output signal and the 7th clock after, send one the 6th and control output signal;

One the 8th T trigger, receive this fundamental frequency and the 6th control output signal after, send the 8th clock;

The 18 AND gate, receive the 6th control output signal and the 8th clock after, send one the 7th and control output signal; And

One the 9th T trigger, receive this fundamental frequency and the 7th control output signal after, send the 9th clock.

3. adjust the bright pulse width modulation device that contrasts of LCD for one kind, comprising:

One counter, receive a fundamental frequency after, produce one first clock, a second clock, one the 3rd clock, one the 4th clock, one the 5th clock, one the 6th clock, one the 7th clock, one the 8th clock and one the 9th clock;

One comparer, after receiving this first clock, this second clock, the 3rd clock, the 4th clock, the 5th clock and the 6th clock, respectively with one first control signal, one second control signal, one the 3rd control signal, one the 4th control signal, one the 5th control signal and one the 6th control signal relatively after, send a comparison signal;

Six phase inverters, after receiving this first clock, this second clock, the 3rd clock, the 4th clock, the 5th clock and the 6th clock respectively, send anti-phase first clock, an anti-phase second clock, anti-phase the 3rd clock, anti-phase the 4th clock, anti-phase the 5th clock and anti-phase the 6th clock more respectively;

One first AND gate, receive this anti-phase first clock, this anti-phase second clock and anti-phase the 3rd clock after, send one first output signal;

One second AND gate, receive this anti-phase the 4th clock, this anti-phase the 5th clock and this anti-phase the 6th clock after, send one second output signal;

One the 3rd AND gate, receive this first output signal and this second output signal after, send one the 3rd output signal;

One T trigger, receive this comparison signal, the 3rd output signal and an input voltage after, send a pulse width modulation signal;

One first phase inverter receives the 8th clock, sends anti-phase the 8th clock;

One second phase inverter receives the 7th clock, sends anti-phase the 7th clock;

One the 3rd phase inverter receives the 8th clock, sends this anti-phase the 8th clock;

One the 4th phase inverter receives the 7th clock, sends this anti-phase the 7th clock;

One the 4th AND gate, receive this anti-phase the 8th clock and this anti-phase the 7th clock after, send one first concurrent output signal;

One the 5th AND gate, receive this anti-phase the 8th clock and the 7th clock after, send one second concurrent output signal;

One the 6th AND gate, receive the 8th clock and this anti-phase the 7th clock after, send one the 3rd concurrent output signal;

One the 7th AND gate, receive the 8th clock and the 7th clock after, send one the 4th concurrent output signal;

One node out gate is sent a node signal; And

The 19 AND gate, receive this node signal and this pulse width modulation signal after, send a modulation node signal.

4. the pulse width modulation device of the bright contrast of adjustment LCD as claimed in claim 3, wherein this counter comprises:

One the one T trigger, receive this fundamental frequency and this input voltage after, send this first clock;

One the 2nd T trigger, receive this fundamental frequency and this first clock after, send this second clock;

The 12 AND gate, receive this first clock and this second clock after, send one first control output signal;

One the 3rd T trigger, receive this fundamental frequency and this first control output signal after, send the 3rd clock;

The 13 AND gate, receive this first control output signal and the 3rd clock after, send one second and control output signal;

One the 4th T trigger, receive this fundamental frequency and this second control output signal after, send the 4th clock;

The 14 AND gate, receive this second control output signal and the 4th clock after, send one the 3rd and control output signal;

One the 5th T trigger, receive this fundamental frequency and the 3rd control output signal after, send the 5th clock;

The 15 AND gate, receive the 3rd control output signal and the 5th clock after, send one the 4th and control output signal;

One the 6th T trigger, receive this fundamental frequency and the 4th control output signal after, send the 6th clock;

The 16 AND gate, receive the 4th control output signal and the 6th clock after, send one the 5th and control output signal;

One the 7th T trigger, receive this fundamental frequency and the 5th control output signal after, send the 7th clock;

The 17 AND gate, receive the 5th control output signal and the 7th clock after, send one the 6th and control output signal;

One the 8th T trigger, receive this fundamental frequency and the 6th control output signal after, send the 8th clock;

The 18 AND gate, receive the 6th control output signal and the 8th clock after, send one the 7th and control output signal; And

One the 9th T trigger, receive this fundamental frequency and the 7th control output signal after, send the 9th clock.

5. adjust the bright pulse width modulation device that contrasts of LCD for one kind, comprising:

One counter, receive a fundamental frequency after, produce one first clock, a second clock, one the 3rd clock, one the 4th clock, one the 5th clock, one the 6th clock, one the 7th clock, one the 8th clock and one the 9th clock;

One comparer, after receiving this first clock, this second clock, the 3rd clock, the 4th clock, the 5th clock and the 6th clock, respectively with one first control signal, one second control signal, one the 3rd control signal, one the 4th control signal, one the 5th control signal and one the 6th control signal relatively after, send a comparison signal;

Six phase inverters, after receiving this first clock, this second clock, the 3rd clock, the 4th clock, the 5th clock and the 6th clock respectively, send anti-phase first clock, an anti-phase second clock, anti-phase the 3rd clock, anti-phase the 4th clock, anti-phase the 5th clock and anti-phase the 6th clock more respectively;

One first AND gate, receive this anti-phase first clock, this anti-phase second clock and anti-phase the 3rd clock after, send one first output signal;

One second AND gate, receive this anti-phase the 4th clock, this anti-phase the 5th clock and this anti-phase the 6th clock after, send one second output signal;

One the 3rd AND gate, receive this first output signal and this second output signal after, send one the 3rd output signal;

One T trigger, receive this comparison signal, the 3rd output signal and an input voltage after, send a pulse width modulation signal;

One first phase inverter receives the 8th clock, sends anti-phase the 8th clock;

One second phase inverter receives the 7th clock, sends anti-phase the 7th clock;

One the 3rd phase inverter receives the 8th clock, sends this anti-phase the 8th clock;

One the 4th phase inverter receives the 7th clock, sends this anti-phase the 7th clock;

One the 4th AND gate, receive this anti-phase the 8th clock and this anti-phase the 7th clock after, send one first concurrent output signal;

One the 5th AND gate, receive this anti-phase the 8th clock and the 7th clock after, send one second concurrent output signal;

One the 6th AND gate, receive the 8th clock and this anti-phase the 7th clock after, send one the 3rd concurrent output signal;

One the 7th AND gate, receive the 8th clock and the 7th clock after, send one the 4th concurrent output signal;

One the 8th AND gate, receive this pulse width modulation signal and this first concurrent output signal after, send one first modulation concurrent output signal;

One the 9th AND gate, receive this pulse width modulation signal and this second concurrent output signal after, send one second modulation concurrent output signal;

The tenth AND gate, receive this pulse width modulation signal and the 3rd concurrent output signal after, send one the 3rd modulation concurrent output signal;

The 11 AND gate, receive this pulse width modulation signal and the 4th concurrent output signal after, send one the 4th modulation concurrent output signal;

One node out gate is sent a node signal; And

The 19 AND gate, receive this node signal and this pulse width modulation signal after, send a modulation node signal.

6. the pulse width modulation device of the bright contrast of adjustment LCD as claimed in claim 5, wherein this counter comprises:

One the one T trigger, receive this fundamental frequency and this input voltage after, send this first clock;

One the 2nd T trigger, receive this fundamental frequency and this first clock after, send this second clock;

The 12 AND gate, receive this first clock and this second clock after, send one first control output signal;

One the 3rd T trigger, receive this fundamental frequency and this first control output signal after, send the 3rd clock;

The 13 AND gate, receive this first control output signal and the 3rd clock after, send one second and control output signal;

One the 4th T trigger, receive this fundamental frequency and this second control output signal after, send the 4th clock;

The 14 AND gate, receive this second control output signal and the 4th clock after, send one the 3rd and control output signal;

One the 5th T trigger, receive this fundamental frequency and the 3rd control output signal after, send the 5th clock;

The 15 AND gate, receive the 3rd control output signal and the 5th clock after, send one the 4th and control output signal;

One the 6th T trigger, receive this fundamental frequency and the 4th control output signal after, send the 6th clock;

The 16 AND gate, receive the 4th control output signal and the 6th clock after, send one the 5th and control output signal;

One the 7th T trigger, receive this fundamental frequency and the 5th control output signal after, send the 7th clock;

The 17 AND gate, receive the 5th control output signal and the 7th clock after, send one the 6th and control output signal;

One the 8th T trigger, receive this fundamental frequency and the 6th control output signal after, send the 8th clock;

The 18 AND gate, receive the 6th control output signal and the 8th clock after, send one the 7th and control output signal; And

One the 9th T trigger, receive this fundamental frequency and the 7th control output signal after, send the 9th clock.

7. adjust the bright pulse width modulation device that contrasts of LCD for one kind, comprising:

One counter, receive a fundamental frequency after, produce one first clock, a second clock, one the 3rd clock, one the 4th clock, one the 5th clock, one the 6th clock, one the 7th clock, one the 8th clock and one the 9th clock;

One comparer, after receiving this first clock, this second clock, the 3rd clock, the 4th clock, the 5th clock and the 6th clock, respectively with one first control signal, one second control signal, one the 3rd control signal, one the 4th control signal, one the 5th control signal and one the 6th control signal relatively after, send a comparison signal;

Six phase inverters, after receiving this first clock, this second clock, the 3rd clock, the 4th clock, the 5th clock and the 6th clock respectively, send anti-phase first clock, an anti-phase second clock, anti-phase the 3rd clock, anti-phase the 4th clock, anti-phase the 5th clock and anti-phase the 6th clock more respectively;

One first AND gate, receive this anti-phase first clock, this anti-phase second clock and anti-phase the 3rd clock after, send one first output signal;

One second AND gate, receive this anti-phase the 4th clock, this anti-phase the 5th clock and this anti-phase the 6th clock after, send one second output signal;

One the 3rd AND gate, receive this first output signal and this second output signal after, send one the 3rd output signal;

One T trigger, receive this comparison signal, the 3rd output signal and an input voltage after, send a pulse width modulation signal;

One first phase inverter receives the 8th clock, sends anti-phase the 8th clock;

One second phase inverter receives the 7th clock, sends anti-phase the 7th clock;

One the 3rd phase inverter receives the 8th clock, sends this anti-phase the 8th clock;

One the 4th phase inverter receives the 7th clock, sends this anti-phase the 7th clock;

One the 4th AND gate, receive this anti-phase the 8th clock and this anti-phase the 7th clock after, send one first concurrent output signal;

One the 5th AND gate, receive this anti-phase the 8th clock and the 7th clock after, send one second concurrent output signal;

One the 6th AND gate, receive the 8th clock and this anti-phase the 7th clock after, send one the 3rd concurrent output signal;

One the 7th AND gate, receive the 8th clock and the 7th clock after, send one the 4th concurrent output signal;

One node out gate is sent a node signal; And

One the 5th phase inverter, receive this pulse width modulation signal after, send a rp pulse width modulation signal, in order to the voltage of Control Node signal and concurrent signal output same level.

8. the pulse width modulation device of the bright contrast of adjustment LCD as claimed in claim 7, wherein this counter comprises:

One the one T trigger, receive this fundamental frequency and this input voltage after, send this first clock;

One the 2nd T trigger, receive this fundamental frequency and this first clock after, send this second clock;

The 12 AND gate, receive this first clock and this second clock after, send one first control output signal;

One the 3rd T trigger, receive this fundamental frequency and this first control output signal after, send the 3rd clock;

The 13 AND gate, receive this first control output signal and the 3rd clock after, send one second and control output signal;

One the 4th T trigger, receive this fundamental frequency and this second control output signal after, send the 4th clock;

The 14 AND gate, receive this second control output signal and the 4th clock after, send one the 3rd and control output signal;

One the 5th T trigger, receive this fundamental frequency and the 3rd control output signal after, send the 5th clock;

The 15 AND gate, receive the 3rd control output signal and the 5th clock after, send one the 4th and control output signal;

One the 6th T trigger, receive this fundamental frequency and the 4th control output signal after, send the 6th clock;

The 16 AND gate, receive the 4th control output signal and the 6th clock after, send one the 5th and control output signal;

One the 7th T trigger, receive this fundamental frequency and the 5th control output signal after, send the 7th clock;

The 17 AND gate, receive the 5th control output signal and the 7th clock after, send one the 6th and control output signal;

One the 8th T trigger, receive this fundamental frequency and the 6th control output signal after, send the 8th clock;

The 18 AND gate, receive the 6th control output signal and the 8th clock after, send one the 7th and control output signal; And

One the 9th T trigger, receive this fundamental frequency and the 7th control output signal after, send the 9th clock.

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