CN117013834A

CN117013834A - Power converter, control circuit and control method thereof

Info

Publication number: CN117013834A
Application number: CN202310627830.6A
Authority: CN
Inventors: 温海涛; 陈驰南; 俞杨威
Original assignee: Joulwatt Technology Co Ltd
Current assignee: Joulwatt Technology Co Ltd
Priority date: 2023-05-30
Filing date: 2023-05-30
Publication date: 2023-11-07

Abstract

The application provides a power converter, a control circuit and a control method thereof, wherein the control circuit comprises: a mode control circuit for controlling the power converter to switch between a bypass mode, a transition mode and a normal switch operation mode according to the input voltage and/or the output voltage; a control signal generating circuit for generating a second control signal in accordance with the mode switching command and a current reference signal defined by the clamp compensation signal in the transition mode and by the compensation signal in the normal switching mode; and/or the second control signal is controlled by the mode switching instruction and has a first frequency in the normal switching working mode, and has a second frequency larger than the first frequency in the transition mode, so that the deviation amplitude of the output voltage relative to the output set voltage when the input voltage fluctuates is greatly reduced, the stability of the output voltage of the power converter when the mode is switched is improved, and the reliable operation of the load is ensured.

Description

Power converter, control circuit and control method thereof

Technical Field

The application relates to the technical field of power supplies, in particular to a power converter, a control circuit and a control method thereof.

Background

With the development of power electronics and semiconductor technology, power management chips are widely used in the fields of communication, consumption, computing, and the like. Taking a DC-DC converter as an example, which is one of the most common types in power management chips, typically comprises one or more switches selectively actuated to provide a controlled DC output voltage or current based on a received DC input, by controlling the output power of a duty cycle adjustable circuit of a signal provided to one or more switching transistors of the converter.

In order to ensure normal operation and high efficiency when the input voltage Vin provided by the input power supply 11 and the output voltage Vout of the converter are close or equal, as shown in fig. 1 and 2, a bypass unit (such as a bypass switch) 12 is usually disposed between the input and the output of the converter, and when the bypass switch is turned on, a current path of the power inductor L1 is bypassed to realize a low-impedance pass-through (bypass) operation mode of the input and the output. When the voltage difference between the input voltage Vin and the output voltage Vout is large, it is necessary to switch from the bypass operation mode to the switch operation mode and turn off the bypass switch 12, but a large drop occurs in the output voltage Vout during the transient process of switching, which affects the operation performance of the load 13 and the system.

Accordingly, there is a need to provide an improved solution to overcome the above technical problems in the prior art.

Disclosure of Invention

In order to solve the technical problems, the application provides a power converter, a control circuit and a control method thereof, which can solve the problem that the deviation amplitude of output voltage relative to output set voltage is large in the switching process of a bypass working mode and a switch working mode of a DC-DC converter, and ensure the reliable operation of a load.

According to a first aspect of the present application, there is provided a control circuit for a power converter, the power converter further comprising a power unit and a bypass unit coupled to each other, the control circuit being adapted to generate a first control signal and a second control signal for controlling on and off of switching transistors in the bypass unit and the power unit, respectively, the control circuit comprising:

the mode control circuit is used for generating a mode switching instruction according to the input voltage and/or the output voltage of the power converter and controlling the power converter to switch among a bypass mode, a transition mode and a normal switch working mode;

the control signal generation circuit is used for generating the first control signal according to the mode switching instruction, wherein the first control signal is in an effective state in the bypass mode and is in an ineffective state in the transition mode and the normal switch working mode;

When the power converter is a boost power converter, the power converter is controlled to work in the transition mode when the input voltage and/or the output voltage is detected to drop to be smaller than a second voltage threshold value and the drop slope of the input voltage and/or the output voltage is larger than a preset threshold value or the drop slope of the input voltage and/or the output voltage is smaller than a preset threshold value, and when the input voltage and/or the output voltage is detected to drop to be a first voltage threshold value, the first voltage threshold value is set according to an expected value of the output voltage and is smaller than the second voltage threshold value.

Optionally, the control signal generating circuit generates the second control signal according to the mode switching instruction and a current reference signal, wherein the current reference signal is defined by a compensation signal in the normal switching operation mode, and the compensation signal is obtained by compensating an error amplification signal representing difference information of the output voltage and a reference voltage.

Optionally, in the transition mode, the current reference signal is defined by a clamp compensation signal obtained after clamping the compensation signal via a clamp voltage acquired in advance.

Optionally, the clamp voltage is obtained in response to sampling, summing and sample-and-hold of currents flowing through the power cell and the bypass cell in the bypass mode prior to the transition mode; or alternatively

The clamp voltage is obtained in response to sample-and-hold of a current flowing through the bypass cell in the bypass mode prior to the transition mode.

Optionally, the second control signal has a first frequency in the normal switching mode of operation,

in the transition mode, the second control signal has a second frequency that is greater than the first frequency.

Optionally, the control signal generating circuit is configured to: generating the second control signal according to a clock pulse signal and the current reference signal, wherein the clock pulse signal is used for limiting the frequency of the second control signal, and the current reference signal is used for limiting the duty ratio of the second control signal;

the clock pulse signal has the first frequency in the normal switch working mode and the second frequency in the transition mode under the control of the mode switching instruction.

Optionally, the control signal generating circuit includes:

The feedback control circuit receives the reference voltage and a feedback signal, outputs the compensation signal, and obtains the feedback signal according to the output voltage;

a current comparator circuit for comparing a sampling signal with the current reference signal, outputting a comparison signal, the sampling signal characterizing current information flowing through a switching transistor in the power cell;

a signal generator circuit for outputting the clock pulse signal having the first frequency or the second frequency according to the mode switching instruction;

the controller circuit and the driving circuit are used for generating the second control signal according to the clock pulse signal and the comparison signal.

Optionally, the control signal generating circuit is configured to: generating the second control signal according to a preset time threshold and the current reference signal, wherein the time threshold is inversely related to the frequency of the second control signal;

the time threshold has a first value in the normal switch working mode, has a second value in the transition mode and is larger than the second value under the control of the mode switching instruction.

Optionally, the control signal generating circuit includes:

a timer circuit for outputting a trigger signal corresponding to the first value or the second value according to the mode switching instruction and the comparison signal;

a controller circuit and a driving circuit for generating the second control signal based on the trigger signal and the comparison signal,

wherein the timer circuit is configured to:

when the mode switching instruction has a second instruction state, starting timing according to the comparison signal, and outputting the trigger signal when the timing value reaches a timing threshold corresponding to the second numerical value; or after the mode switching instruction is in the second instruction state for a preset time, starting timing according to the comparison signal, and outputting the trigger signal when the timing value reaches the timing threshold corresponding to the first value.

Optionally, the mode control circuit is configured to:

when the input voltage and/or the output voltage is detected to be greater than a preset second voltage threshold value, generating the mode switching instruction with a first instruction state, and controlling the power converter to work in the bypass mode;

when the input voltage and/or the output voltage is detected to be reduced to be smaller than the second voltage threshold value and the falling slope of the input voltage and/or the output voltage is larger than a preset threshold value, generating the mode switching instruction with a second instruction state, and controlling the power converter to switch from a bypass mode to the transition mode;

and after the power converter works in the transition mode for a preset time, controlling the power converter to switch from the transition mode to the normal switch working mode.

Optionally, the mode control circuit is configured to:

when the input voltage and/or the output voltage is detected to be reduced to be smaller than the second voltage threshold value and the reduction slope of the input voltage and/or the output voltage is detected to be smaller than a preset threshold value, generating the mode switching instruction with a first instruction state, and controlling the power converter to work in the bypass mode;

When the input voltage and/or the output voltage are/is detected to be smaller than a preset first voltage threshold value, the power converter is controlled to be switched from the bypass mode to the transition mode, and the first voltage threshold value is smaller than the second voltage threshold value;

According to a second aspect of the present invention, there is provided a control circuit of a power converter, the power converter further comprising a power unit and a bypass unit coupled to each other, the control circuit being adapted to generate a first control signal and a second control signal for controlling on and off of switching transistors in the bypass unit and the power unit, respectively, the control circuit comprising:

When the power converter is a buck power converter, the power converter is controlled to work in the transition mode when the input voltage and/or the output voltage is detected to rise to be greater than a third voltage threshold value, and the rising slope of the input voltage and/or the output voltage is greater than a preset threshold value, or the rising slope of the input voltage and/or the output voltage is smaller than the preset threshold value, and when the input voltage and/or the output voltage is detected to rise to a fourth voltage threshold value, the fourth voltage threshold value is set according to the expected value of the output voltage, and the fourth voltage threshold value is greater than the third voltage threshold value.

According to a third aspect of the present invention, there is provided a power converter, comprising:

a power unit and a bypass unit coupled to each other, the power unit including an inductor and a switching transistor coupled to the inductor;

including a control circuit as described above for providing control signals to control the switching transistors in the power cells and the bypass cells to turn on and off.

According to a fourth aspect of the present invention, there is provided a control method of a power converter including a power unit and a bypass unit coupled to each other, the control method comprising:

Generating a mode switching instruction according to the input voltage and/or the output voltage of the power converter, and controlling the power converter to switch among a bypass mode, a transition mode and a normal switch working mode;

generating a first control signal according to the mode switching instruction, wherein the first control signal is used for controlling the on and off of a switching transistor in the bypass unit; the first control signal is in an effective state in the bypass mode, and is in an ineffective state in the transition mode and the normal switch working mode;

when the power converter is a boost power converter, when the input voltage and/or the output voltage is detected to drop to be smaller than a second voltage threshold value and the drop slope of the input voltage and/or the output voltage is larger than a preset threshold value, or the drop slope of the input voltage and/or the output voltage is smaller than the preset threshold value, the power converter is controlled to work in the transition mode when the input voltage and/or the output voltage is detected to drop to a first voltage threshold value, wherein the first voltage threshold value is set according to an expected value of the output voltage, and the first voltage threshold value is smaller than the second voltage threshold value.

Optionally, a second control signal is generated according to the mode switching command and a current reference signal, where the second control signal is used to control on and off of a switching transistor in the power unit, the current reference signal is defined by a compensation signal in the normal switching operation mode, and the compensation signal is obtained by compensating an error amplification signal representing difference information between the output voltage and the reference voltage.

Optionally, the second control signal has a first frequency in the normal switching mode of operation;

Optionally, generating the second control signal according to the mode switching instruction and a current reference signal includes:

providing a clock pulse signal with the first frequency in the normal switch working mode and providing a clock pulse signal with the second frequency in the transition mode under the control of the mode switching instruction;

the second control signal is generated according to the clock pulse signal and the current reference signal, wherein the clock pulse signal is used for limiting the frequency of the second control signal, and the current reference signal is used for limiting the duty ratio of the second control signal.

providing a time threshold value having a first value in the normal switching operation mode and providing a time threshold value having a second value in the transition mode under the control of the mode switching instruction;

generating the second control signal according to the time threshold and the current reference signal, wherein the time threshold is inversely related to the frequency of the second control signal;

Wherein the first value is greater than the second value.

The beneficial effects of the application at least comprise:

according to the control circuit provided by the embodiment of the application, on one hand, the compensation signal is clamped by the clamping voltage and then is used as a reference signal for generating the second control signal, so that in the process of generating the second control signal after the bypass mode is exited, the output information of the power converter such as the load current can be subjected to quicker feedback response, the inductance current of the converter can reach the value corresponding to the load current in a very short time, and compared with the prior art, the deviation amplitude of the output voltage relative to the output set voltage when the input voltage rapidly jumps is greatly reduced, the stability of the output voltage of the power converter when the mode is switched is improved, and the reliable operation of the load is ensured.

On the other hand, when the power converter is a boost converter, the embodiment of the application controls the power converter to exit the bypass mode when detecting that the falling slope of the input voltage and/or the output voltage is greater than the preset threshold value and the input voltage and/or the output voltage is reduced to be less than the preset second voltage threshold value, which is equivalent to that before the output voltage is not reduced to the preset output set voltage (namely the first voltage threshold value), the mode switching instruction of the second instruction state is generated in advance to control the power converter to exit the bypass mode in advance, so that the minimum value which can be reached in the process of quickly jumping the output voltage along with the input voltage is higher; when the power converter is a buck converter, the embodiment of the application controls the power converter to exit the bypass mode when detecting that the rising slope of the input voltage and/or the output voltage is greater than the preset threshold value and the input voltage and/or the output voltage is raised to be greater than the preset third voltage threshold value, which is equivalent to that before the output voltage is not raised to the preset output set voltage (namely, the fourth voltage threshold value), the mode switching instruction in the second instruction state is generated in advance to control the power converter to exit the bypass mode in advance, so that the highest value which can be reached in the process of quickly jumping the output voltage along with the input voltage is lower, the stability of the output voltage of the power converter in the mode switching process is further improved, and the reliable operation of a load is ensured.

On the other hand, even when the change slope of the input voltage and/or the output voltage is not detected to be larger than a certain preset threshold value, a transition mode is also arranged between the bypass mode and the normal switch working mode, so that the transition between the bypass mode and the normal switch working mode is more stable, and the response speed of the system can be improved.

In still another aspect, the power converter is driven at a higher control frequency in a transition mode before the bypass mode is exited and the normal switching mode is entered, so that the transient response of the system is further improved, the time for the inductor current of the converter to reach the corresponding value of the load current is shortened, the deviation amplitude of the output voltage relative to the output set voltage when the input voltage is rapidly hopped is further reduced, the stability of the output voltage of the power converter is higher when the mode is switched, and the reliability of the load operation is stronger.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

FIG. 1 shows a schematic diagram of a prior art power converter;

FIG. 2 shows a schematic diagram of another prior art power converter;

FIG. 3 illustrates a schematic diagram of a power converter provided in some embodiments according to the application;

FIG. 4 illustrates a schematic diagram of a power converter provided in accordance with further embodiments of the application;

fig. 5 shows a flowchart of a control method of a power converter according to an embodiment of the present application.

Detailed Description

In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. The application may, however, be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

The power converter provided by the embodiment of the present application, among various exemplary examples illustrated and described hereinafter, is merely exemplary of an example of a power converter system of a boost type, which is a DC-DC converter, and the control circuit provided by the embodiment of the present application is used for PWM control of the DC-DC converter. The application is not limited in this regard and the various concepts disclosed herein may be used in connection with any type of DC-DC converter architecture, including Buck-Boost (Buck) converters, boost-Boost (Boost) converters, flyback (Flyback) converters, buck-Boost (Buck-Boost) converters, etc., for example, depending on the topology classification of the power circuit. Furthermore, while complementary PWM control of the high-side switching devices and the low-side switching devices is utilized in the illustration of an embodiment of the present application, the concepts described herein can be implemented in power converters that use only a single switching device and/or in power converters that employ more than two pulse width modulations.

Referring to fig. 3 and 4, a power converter 20 according to various embodiments of the present application includes: a power unit 23, a bypass unit 22, and a control circuit 24 coupled to the power unit 23 and the bypass unit 22, respectively. The power unit 23 is coupled between the input power source 21 and the output, and the bypass unit 22 is connected between the input power source 21 and the output, receives an input voltage Vin provided by the input power source 21, and provides an output voltage Vout to the load 25. The control circuit 24 is configured to generate control signals Vgs1, vgs2, and Vgs3 to control on and off of each of the switching transistors in the bypass unit 22 and the power unit 23. It should be noted that the first control signal described herein corresponds to the control signal Vgs3. The second control signal described herein corresponds to the complementary control signal Vgs1 and Vgs2 in complementary PWM control using a high-side switching device and a low-side switching device (as in the embodiments shown in fig. 3 and 4) and corresponds to the control signal Vgs1 in a power converter embodiment using a single switching device (as in the replacement of switching transistor Q2 in fig. 3 and 4 with a diode).

In the example shown in fig. 3 and 4, the bypass unit 22 includes a switching transistor Q3, the power unit 23 includes an inductor L1, and a switching transistor Q1 and a switching transistor Q2 coupled to the inductor L1, the switching transistor Q3 is coupled between the input power source 21 and the output, the inductor L1 and the switching transistor Q2 are sequentially coupled in series between the input power source 21 and the output, and the switching transistor Q1 is coupled between a connection node of the inductor L1 and the switching transistor Q2 and the reference ground. The control signal Vgs1 is used for controlling the on and off of the switching transistor Q1, the control signal Vgs2 is used for controlling the on and off of the switching transistor Q2, the control signal Vgs3 is used for controlling the on and off of the switching transistor Q3, and the control signal Vgs1 and the control signal Vgs2 correspond to a group of complementary PWM signals, and the two have the same frequency. Wherein the switching transistors Q1, Q2 and Q3 are NMOS devices, but the application is not limited thereto, and other embodiments are possible in which different types of switching transistors are used, such as at least one of the switching transistors Q1, Q2 and Q3 may also be selected as PMOS devices, etc.

The power converter 20 further comprises other components, such as a capacitor Ci connected in parallel across the input power source 21 and a capacitor Co connected in parallel across the output.

It will be appreciated that the power converter 20 shown in fig. 3 and 4 is of an input-output common-negative structure, for example, the inductor L1, the switching transistor Q2 and the bypass unit 22 in the power converter 20 are coupled between the positive input terminal and the output of the input power source 21, but other examples are possible, and the power converter 20 may also be of an input-output common-positive structure, for example, the inductor L1, the switching transistor Q2 and the bypass unit 22 in the power converter 20 are coupled between the negative input terminal and the output of the input power source 21. At least one of the switching transistors, the inductance L1, the capacitance Ci, and the capacitance Co components included in the power converter 20 shown in fig. 3 and 4 may be integrated in the control circuit 24 or may be provided outside the control circuit 24. Furthermore, fig. 3 and 4 only show examples of a single-phase power converter 20 in which the control circuit 24 is coupled with one power cell 23 and one bypass cell 22, but other examples are possible, and the control circuit scheme provided by the present application is also applicable to multiphase control of multiphase power converters.

The system shown in fig. 3 implements a constant frequency control mode boost DC-DC converter operated by the control circuit 24, and the system shown in fig. 4 implements a constant time (constant on-time or constant off-time) control mode boost DC-DC converter operated by the control circuit 24, wherein the control circuit 24 implements feedback control in accordance with a closed loop of an output voltage Vout, which is supplied to a load 25 in parallel with a capacitor Co. Furthermore, in this embodiment, the control circuit 24 regulates the output voltage Vout in accordance with the reference voltage Vref, but other embodiments are possible in which the control circuit 24 can regulate the output voltage Vout in accordance with an externally supplied setpoint signal. In addition, the control circuit 24 may also receive an enable signal, allowing the operation of the control circuit 24 and the DC-DC converter 20 to be selectively enabled or disabled.

As further shown in connection with fig. 3 and 4, the control circuit 24 comprises: a mode control circuit 241, a clamp voltage generation circuit 242, and a control signal generation circuit 243.

The mode control circuit 241 is configured to generate a mode switching command EN according to the input voltage Vin and/or the output voltage Vout of the power converter 20, where the mode switching command EN is used to control the power converter 20 to switch among a bypass mode, a transition mode and a normal switching operation mode. The transition mode defined in the embodiment of the application is equivalent to a short-term intermediate transition state in the switching process of the power converter from the bypass mode to the normal switch working mode. It should be noted that, the transition mode and the normal switching mode may be defined and understood in a combined manner, that is, the transition mode corresponds to a previous process of the power converter exiting the bypass mode to enter the boost operation, and the normal switching mode corresponds to a later process of the power converter exiting the bypass mode to enter the boost operation.

Specifically, in an exemplary embodiment, during switching from the bypass mode to the normal switching operation mode, the mode control circuit 241 generates the mode switching command EN having the first command state (e.g., one of the high level state and the low level state) upon detecting that the input voltage Vin and/or the output voltage Vout is greater than the preset second voltage threshold value, thereby controlling the power converter 20 to operate in the bypass mode. When the power converter 20 is operating in the bypass mode, the bypass unit 22 is enabled, the power unit 23 is disabled, i.e. the switching transistor Q3 is turned on, the switching transistor Q1 is turned off, the switching transistor Q2 is turned on, or both the switching transistor Q1 and the switching transistor Q2 are turned off. The second voltage threshold is higher than the first voltage threshold, and as one embodiment of the present invention, the second voltage threshold may be obtained by adding the first voltage threshold to a bias voltage value. The first voltage threshold is an output set voltage preset by the power converter 20, and corresponds to the reference voltage Vref. The mode control circuit 241 generates a mode switching command EN having a second command state (e.g., the other of the high-level state and the low-level state) when detecting that the falling slope of the input voltage Vin and/or the output voltage Vout is greater than a preset threshold value and that the input voltage Vin and/or the output voltage Vout falls below a preset second voltage threshold value and is greater than a preset first voltage threshold value, thereby controlling the power converter 20 to switch from the bypass mode to the transition mode. When the power converter 20 is operating in the transitional mode, the bypass unit 22 is disabled, the power unit 23 is enabled, i.e. the switching transistor Q3 is turned off, and the switching transistors Q1 and Q2 are complementarily turned on according to the control signals Vgs1 and Vgs 2. In the bypass mode, since the input power source and the output are connected through the bypass unit (e.g., the switching transistor Q3), the operation state thereof may be determined based on the input voltage, the output voltage, or both, and the setting may be selected according to the actual situation by changing the corresponding voltage determination threshold value.

In another exemplary embodiment, if the input voltage Vin and/or the output voltage Vout drops between the first voltage threshold and the second voltage threshold, and no falling slope of the input voltage Vin and/or the output voltage Vout is detected to be greater than the preset threshold between the first voltage threshold and the second voltage threshold, the power converter 20 continues to remain in the bypass mode. Thereafter, the mode control circuit 241 generates a mode switching command EN having a second command state (e.g., the other of the high-level state and the low-level state) upon detecting that the input voltage Vin and/or the output voltage Vout is less than a preset first voltage threshold, thereby controlling the power converter 20 to switch from the bypass mode to the transition mode. When the power converter 20 is operating in the transitional mode, the bypass unit 22 is disabled, the power unit 23 is enabled, i.e. the switching transistor Q3 is turned off, and the switching transistors Q1 and Q2 are complementarily turned on according to the control signals Vgs1 and Vgs 2. Further, after the power converter 20 is operated in the transition mode for a predetermined time (denoted as t 1), the power converter 20 is controlled to switch from the transition mode to the normal switching operation mode. When the power converter 20 is operating in the normal switching mode, the bypass unit 22 is disabled, the power unit 23 is enabled, i.e. the switching transistor Q3 is turned off, and the switching transistors Q1 and Q2 are complementarily turned on according to the control signals Vgs1 and Vgs 2. The predetermined time t1 may be set differently according to different application scenarios. When the falling slope of the input voltage Vin and/or the output voltage Vout is detected to be larger than a preset threshold value and the input voltage Vin and/or the output voltage Vout is detected to fall to be smaller than a preset second voltage threshold value, the power converter is controlled to exit the bypass mode. In addition, even when the change slope of the input voltage and/or the output voltage is not detected to be larger than a certain preset threshold value, a transition mode is also arranged between the bypass mode and the normal switch working mode, so that the transition between the bypass mode and the normal switch working mode is more stable, and the response speed of the system can be improved.

In some preferred embodiments, the signal controlling the complementary conduction of Vgs1 and Vgs2 has a second frequency in the transitional mode, and the signal controlling the complementary conduction of Vgs1 and Vgs2 has a first frequency in the normal switching operation mode, and the second frequency is set to be greater than the first frequency, wherein the second frequency can be set to be more than twice the first frequency as one of the embodiments of the present application. That is, after the power converter 20 exits the bypass mode, the control circuit 24 drives the power converter 20 at a high frequency by the control signals Vgs1 and Vgs2 having a higher frequency, and then resumes the normal driving frequency, so that the system has a faster transient response in the process of recovering the output voltage Vout after exiting the bypass mode, thereby shortening the time for the inductor current in the power converter 20 to reach the corresponding value of the load current, equivalently reducing the deviation amplitude of the output voltage Vout relative to the output set voltage when the input voltage Vin jumps in a fast pull-down mode, and further improving the stability of the output voltage and the reliability of the load operation.

The clamp voltage generating circuit 242 is used for generating a clamp voltage V according to current (denoted as I2) flowing through the bypass unit (denoted as I3) and/or the switching transistor Q2 in the bypass mode _CLAMP The clamp voltage V _CLAMP Compensation signal V for a system _COMP Clamping is performed. Wherein the compensation signal V _COMP Is obtained by compensating an error amplification signal representing difference information between the output voltage Vout and the reference voltage Vref.

The clamp voltage generation circuit 242 is specifically configured to: the current I2 flowing through the power cell and the current I3 flowing through the bypass cell are sampled, summed and sample-and-hold in the bypass mode, thereby generating a clamp voltage V _CLAMP . In these embodiments, the clamp voltage generating circuit 242 includes a sampling and summing circuit 2421 and a sampling and holding circuit 2422, where the sampling and summing circuit 2421 is utilized by the clamp voltage generating circuit 242 to sample and sum the current I2 flowing through the power unit and the current I3 flowing through the bypass unit, respectively, and output a sampling and summing signal; the sample and sum signal output from the sample and sum circuit 2421 is sample and held by the sample and hold circuit 2422, and the clamp voltage V is output _CLAMP . As one embodiment of the invention, after the sampling summation of I3 and I2, the sampling summation can be output to a sampling hold circuit after a certain delay to generate a clamping voltage V _CLAMP The clamping effect is better. Whether or not to set the delay is selectable by those skilled in the art according to the actual situation. The sample-and-hold circuit 2422 is enabled in the bypass mode and disabled in the normal switching mode under the control of the mode switch command EN. The clamp voltage generating circuit 242 is provided in the power converter 2 0 to the clamping voltage V after exiting the bypass mode _CLAMP Corresponds to the predetermined time t1 set as described above. Other implementations are possible, however, and the clamp voltage generation circuit 242 may be configured to: by sampling and holding the current I3 flowing through the bypass unit in the bypass mode, the clamp voltage V is generated _CLAMP . At this time, the clamp voltage generating circuit 242 may sample and hold the current I3 flowing through the bypass unit by using a sample and hold circuit to output the clamp voltage V _CLAMP 。

It will be appreciated that although the compensation signal V _COMP The output information of the power converter can be characterized, but during transients of the mode switch (corresponding to the transition mode), the compensation signal V _COMP A certain time is required for the establishment of the response of the system, and the recovery speed of the system to the output voltage Vout or the output current in the transient process is influenced, so that the output voltage Vout is easy to deviate greatly. And due to the clamp voltage V generated by the clamp voltage generating circuit 242 _CLAMP Can also be used to characterize the load current information required for steady operation of the load 25, and therefore, during transients in mode switching, the present embodiment uses this clamp voltage V _CLAMP For compensation signal V _COMP The clamping is carried out, and the voltage signals obtained after the clamping are used as reference signals for generating control signals Vgs1 and Vgs2, so that the system can still carry out quick and even faster feedback response on the output information of the power converter 20 in the transient process, the recovery speed of the output voltage Vout or the output current is improved, the inductance current of the converter can reach the value corresponding to the load current in a very short time, the deviation amplitude of the output voltage Vout relative to the output set voltage in the mode switching is greatly reduced, and the stability of the output voltage and the reliability of the load operation of the power converter in the mode switching are further improved.

The control signal generating circuit 243 is configured to generate the control signal Vgs3 according to the mode switching command EN and generate the control signals Vgs1 and Vgs2 according to the mode switching command EN and the current reference signal, thereby controlling the switching transistors Q1 and Q2 to be complementarily turned on, or in the bypass mode, controlling the switching transistor Q1 to be kept turned off, and the switching transistor Q2 to be kept on or turned off, which is selectively set by a person skilled in the art according to the actual situation, and will not be described in detail in the embodiment of the present invention.

The control signal generation circuit 243 includes a logic circuit 2431, and the logic circuit 2431 receives the mode switching instruction EN and outputs the control signal Vgs3. The logic circuit 2431 may be implemented as a logic gate circuit, and the specific configuration of the logic circuit 2431 is not limited, so long as the control signal Vgs3 in an active state (e.g., high level) can be output when the mode switching command EN in the first command state is received, the switching transistor Q3 is controlled to be turned on, and the control signal Vgs3 in an inactive state (e.g., low level) can be output when the mode switching command EN in the second command state is received, and the switching transistor Q3 is controlled to be turned off. That is, the control signal Vgs3 is in an active state in the bypass mode, and is in an inactive state in the transition mode and the normal switching operation mode.

In some embodiments, the control signal generation circuit 243 is configured to generate the control signals Vgs1 and Vgs2 from the clock pulse signal CLK and the current reference signal. Wherein the clock pulse signal CLK is used to define the frequency of the control signals Vgs1 and Vgs2, and the current reference signal is used to define the duty cycle of the control signals Vgs1 and Vgs2. The clock pulse signal CLK has a second frequency and the current reference signal is obtained according to the clamp compensation signal in the transition mode; in the normal switching mode, the clock signal CLK has a first frequency and the current reference signal is according to the compensation signal V _COMP Obtained. In these embodiments, referring to fig. 3, the control signal generating circuit 243 further includes: feedback control circuit 2432, sampling circuit 2433, current comparator circuit 2434, signal generator circuit 2435, controller circuit 2436, and drive circuit 2437.

In these embodiments, the feedback control circuit 2432 receives the reference voltage Vref and the feedback signal FB and outputs the compensation signal V _COMP The feedback signal FB is obtained according to the output voltage Vout, and represents the sampling result of the output voltage Vout, and the specific acquisition mode of the feedback signal FB can refer to the prior art The procedure is understood. The output of feedback control circuit 2432 also receives a clamp voltage V _CLAMP The clamp voltage V _CLAMP The compensation signal V will be in bypass mode and transition mode _COMP Clamping is performed.

The sampling circuit 2433 is configured to sample the inductor current in the power unit 23 and output a sampling signal Vs, where the sampling circuit 2433 may sample the current I1 flowing through the switching transistor Q1 to obtain the sampling signal Vs, or may sample the current I2 flowing through the switching transistor Q2 to obtain the sampling signal Vs, and may specifically be selected according to practical application requirements.

The input end of the current comparator circuit 2434 is coupled to the output end of the feedback control circuit 2432 and the output end of the sampling circuit 2433, respectively, and the current comparator circuit 2434 is configured to compare the sampling signal Vs with the current reference signal (i.e., the output end signal of the feedback control circuit 2432) and output a comparison signal. As can be seen from the foregoing description, in the transition mode, the output signal of the feedback control circuit 2432 is via the clamp voltage V _CLAMP Clamping compensation signal V _COMP In the normal switching mode, the output signal of the feedback control circuit 2432 is the compensation signal V _COMP 。

The signal generator circuit 2435 receives a mode switching instruction EN for outputting the clock signal CLK having the first frequency or the second frequency according to the mode switching instruction EN. In the transition mode, the signal generator circuit 2435 outputs the clock signal CLK having the second frequency, and in the normal switching operation mode, the signal generator circuit 2435 outputs the clock signal CLK having the first frequency.

The controller circuit 2436 receives the comparison signal output from the current comparator circuit 2434 and the clock signal CLK output from the signal generator circuit 2435, and generates complementary control signals Vgs1 and Vgs2 to the switching transistors Q1 and Q2, respectively, via the driving circuit 2437 under the triggering of the clock signal CLK and the comparison signal. In some embodiments, controller circuit 2436 may implement the corresponding functionality using, for example, an RS flip-flop, although the application is not limited in this regard.

From the aboveAs can be seen, the control signal generating circuit 243 in this embodiment can control the power converter 20 to exit the bypass mode in advance based on the mode switching instruction EN provided by the mode control circuit 241 when the rapid jump of the input voltage Vin is detected in the bypass mode, and enter the transition mode before the normal switch operation mode, or switch from the bypass mode to the normal switch operation mode, and switch to the transition mode when the rapid pull-down jump of the Vin is not detected in the process of switching from the bypass mode, and in the transition mode, switch to the transition mode based on the clamp voltage V generated by the clamp voltage generating circuit 242 in the bypass mode _CLAMP Compensation signal V output from feedback control circuit 2432 _COMP And/or obtains a faster system response based on the clock signal CLK output by the signal generator circuit 2435 having a higher frequency (e.g., the second frequency), so that the inductor current of the power converter 20 can reach a value corresponding to the load current in a short time, thereby greatly reducing the deviation amplitude of the output voltage Vout from the output set voltage when switching from the bypass mode to the normal switching operation mode, and improving the stability of the output voltage Vout and the reliability of the load operation of the power converter during the transient state of the mode switching.

It will be appreciated that in the embodiment shown in fig. 3, the control signal generating circuit 243 is capable of performing fixed frequency control on the power converter 20 based on the clock signal CLK, and by adjusting the correspondence between the signal received by the current comparator circuit 2434 and the positive/negative input terminal thereof (e.g., the current comparator circuit 2434 may receive the sampling signal Vs from the positive input terminal thereof and the current reference signal from the negative input terminal thereof, or the current comparator circuit 2434 may also receive the current reference signal from the positive input terminal thereof and the sampling signal Vs from the negative input terminal thereof), and/or by adjusting the correspondence between the signal received by the controller circuit 2436 and the set/reset terminal thereof (e.g., the controller circuit 2436 may receive the comparison signal from the set terminal thereof and the clock signal CLK from the reset terminal thereof), the application may also perform expansion of various embodiments, for example, in some embodiments, the peak current may be controlled by performing fixed frequency control on the power converter 20 based on the current flowing through the switching transistor Q1, peak current may perform fixed frequency control on the peak current converter 20 or valley current value Q2, or the like, and the like. It should be noted that, since the signal receiving relationships corresponding to the respective extended embodiments do not affect the understanding of the technical solution of the present application, the detailed description thereof is omitted herein, but these should not be construed as limiting the scope of the present application.

In other embodiments, the control signal generation circuit 243 is configured to generate the control signals Vgs1 and Vgs2 based on a preset time threshold (denoted as T) and a current reference signal. Wherein the time threshold T is inversely related to the frequency of the control signals Vgs1 and Vgs2. Wherein, controlled by the mode switching command EN, in the transition mode, the time threshold T has a second value (e.g., T2), and the current reference signal is obtained according to the clamp compensation signal; in the normal switching mode, the time threshold T has a first value (e.g., T1), and the current reference signal is based on the compensation signal V _COMP Obtained. Wherein the first value T1 is greater than the second value T2, for example, as one embodiment of the present invention, the first value T1 and the second value T2 may be set such that the frequency of the control signals Vgs1 and Vgs2 in the transition mode is more than twice the frequency of the control signals Vgs1 and Vgs2 in the normal switching operation mode. In these embodiments, referring to fig. 4, the control signal generating circuit 243 further includes: feedback control circuit 2432, sampling circuit 2433, current comparator circuit 2434, timer circuit 2438, controller circuit 2436, and drive circuit 2437.

In these embodiments, the feedback control circuit 2432 receives the reference voltage Vref and the feedback signal FB and outputs the compensation signal V _COMP The feedback signal FB is derived from the output voltage Vout. The output of feedback control circuit 2432 also receives a clamp voltage V _CLAMP The clamp voltage V _CLAMP The compensation signal V will be in bypass mode and transition mode _COMP Clamping is performed.

The input end of the current comparator circuit 2434 is coupled to the output end of the feedback control circuit 2432 and the output end of the sampling circuit 2433, respectively, and the current comparator circuit 2434 is configured to compare the sampling signal Vs with the current reference signal (i.e., the output end signal of the feedback control circuit 2432) and output a comparison signal. As can be seen from the foregoing description, in the transition mode, the output signal of the feedback control circuit 2432 is via the clamp voltage V _CLAMP Clamping the compensated signal, while in normal switching mode, the output signal of the feedback control circuit 2432 is the compensation signal V _COMP 。

The timer circuit 2438 receives a mode switch command EN, and outputs a trigger signal corresponding to the first value T1 or the second value T2 according to the mode switch command EN. The timer circuit 2438 starts timing according to the comparison signal output from the current comparator circuit 2434 when the mode switch command EN has the second command state, and outputs a trigger signal corresponding to the second value T2 in the transition mode and a trigger signal corresponding to the first value T1 in the normal switching mode. In operation, the timer circuit 2438 starts timing when it receives a rising or falling edge of the comparison signal output from the current comparator circuit 2434 when the mode switch command EN has the second command state, and outputs a trigger signal when the timing value reaches the second value T2; or after the mode switching command EN is in the second command state for a predetermined time, the timing is started when the rising edge or the falling edge of the comparison signal output from the current comparator circuit 2434 is received, and the trigger signal is output when the timing value reaches the first value T1. Timer circuit 2438 also clears the timing value when the trigger signal is output.

The controller circuit 2436 receives the comparison signal output from the current comparator circuit 2434 and the trigger signal output from the timer circuit 2438, and generates complementary control signals Vgs1 and Vgs2 through the switching transistors Q1 and Q2, respectively, via the driving circuit 2437 under the triggering of the trigger signal and the comparison signal. In some embodiments, controller circuit 2436 may implement the corresponding functionality using, for example, an RS flip-flop, although the application is not limited in this regard.

As can be seen from the above description, the control signal generating circuit 243 in this embodiment can control the power converter 20 to exit the bypass mode in advance based on the mode switching command EN provided by the mode control circuit 241 when the rapid jump of the input voltage Vin is detected in the bypass mode, or enter the transition mode before the normal switching operation mode when the rapid jump of the input voltage Vin is not detected, and in this transition mode, the control signal generating circuit 242 generates the clamp voltage V in the bypass mode based on the clamp voltage V _CLAMP Compensation signal V output from feedback control circuit 2432 _COMP And/or a trigger signal based on a corresponding smaller time threshold (e.g., the second value T2) output by the timer circuit 2438, so that the inductor current of the power converter 20 can reach a value corresponding to the load current in a short time, thereby greatly reducing the deviation amplitude of the output voltage Vout relative to the output set voltage during mode switching, and improving the stability of the output voltage Vout and the reliability of load operation of the power converter during transient state of mode switching.

It will be appreciated that in the embodiment shown in fig. 4, the control signal generating circuit 243 is capable of controlling the constant time (including constant on-time or constant off-time) of the power converter 20 based on the timing of the time threshold T by the timer circuit 2438, and by adjusting the correspondence between the signal received by the current comparator circuit 2434 and the positive/negative input terminal thereof (for example, the current comparator circuit 2434 may receive the sampling signal Vs at the positive input terminal thereof and the current reference signal at the negative input terminal thereof; or the current comparator circuit 2434 may also receive the current reference signal Vs at the positive input terminal thereof and the sampling signal Vs at the negative input terminal thereof), and/or the correspondence between the signal received by the controller circuit 2436 and the set/reset terminal thereof (for example, the controller circuit 2436 may receive the comparison signal at the set terminal thereof and the reset terminal thereof), the application may also implement an expansion of various embodiments, for example, the constant on-time control of the current Q1 through the current converter 20 may be controlled by the constant on-time Q2 based on the constant on-time of the current converter 20 based on the constant input terminal thereof, or the constant on-time control of the current Q1 through the current converter 20 may be implemented in some embodiments. It should be noted that, since the signal receiving relationships corresponding to the respective extended embodiments do not affect the understanding of the technical solution of the present application, the detailed description thereof is omitted herein, but these should not be construed as limiting the scope of the present application.

The above description is made only by taking the boost type power converter as an example, and the mode control circuit 241 controls the switching process of the power converter 20 between the bypass mode, the transition mode, and the normal switching operation mode. It will be appreciated that for a buck power transformer, the trigger condition for mode switching is different from that of a boost power transformer: in some examples, the step-down power transformer may generate a mode switching command EN having a first command state when detecting that the input voltage VIN and/or the output voltage VOUT is less than a preset third voltage threshold, and control the converter to operate in the bypass mode; when the input voltage VIN and/or the output voltage VOUT are detected to rise to be larger than a third voltage threshold value, and the rising slope of the input voltage VIN and/or the output voltage VOUT is larger than a preset threshold value, generating a mode switching instruction EN with a second instruction state, and controlling the converter to switch from a bypass mode to a transition mode; after the converter works in the transition mode for a preset time, the converter is controlled to be switched to a normal switch working mode from the transition mode, and the fourth voltage threshold is larger than the third voltage threshold. The fourth voltage threshold may be a preset output set voltage of the power converter 20. In other examples, the step-down power transformer generates a mode switching command EN having a first command state when detecting that the input voltage VIN and/or the output voltage VOUT rise to be greater than a third voltage threshold and the rising slope of the input voltage VIN and/or the output voltage VOUT is less than a preset threshold, so as to control the converter to operate in the bypass mode; when the input voltage VIN and/or the output voltage VOUT are/is detected to be larger than a preset fourth voltage threshold value, the converter is controlled to be switched from a bypass mode to a transition mode; after the converter is operated in the transition mode for a predetermined time, the converter is controlled to switch from the transition mode to the normal switching mode. Furthermore, in the buck mode, when the rapid jump of the input voltage Vin is detected in the bypass mode, the converter is controlled to exit the bypass mode in advance based on the mode switching instruction, or when the rapid jump (such as the rapid pull-up jump) of the input voltage Vin is not detected, the transition mode before the normal switching operation mode is first entered, and in the transition mode, a faster system response is obtained based on the clamping of the compensation signal by the clamping voltage generated in the bypass mode and/or based on the second control signal with a higher frequency in the bypass mode, so that the inductance current of the buck converter can reach a value corresponding to the load current in a short time, thereby greatly reducing the deviation amplitude (the overshoot amplitude of the output voltage) of the output voltage relative to the output set voltage during the transient state process of the mode switching of the power converter, and improving the stability of the output voltage and the reliability of the load operation.

Further, the embodiment of the present application also provides a control method of the power converter, which can be applied to the power converter 20 shown in fig. 3 and 4. Specifically, as shown in fig. 5, the control method includes performing the steps of:

in step S01, a mode switching command is generated according to an input voltage and/or an output voltage of the power converter, and the power converter is controlled to switch among a bypass mode, a transition mode and a normal switching operation mode.

When the power converter is a boost power converter, in some examples, step S01 includes: when the input voltage and/or the output voltage is detected to be larger than a preset second voltage threshold value, generating a mode switching instruction with a first instruction state, and controlling the power converter to work in the bypass mode; when the input voltage and/or the output voltage is detected to be reduced to be smaller than a second voltage threshold value and the falling slope of the input voltage and/or the output voltage is larger than a preset threshold value, a mode switching instruction with a second instruction state is generated, and the power converter is controlled to be switched from a bypass mode to a transition mode; when the input voltage and/or the output voltage is detected to be smaller than a preset first voltage threshold, the power converter is controlled to be switched to a normal switch working mode from a transition mode, and the first voltage threshold is smaller than a second voltage threshold. In other examples, step S01 includes: when the input voltage and/or the output voltage is detected to be reduced to be smaller than a second voltage threshold value and the reduction slope of the input voltage and/or the output voltage is smaller than a preset threshold value, a mode switching instruction with a first instruction state is generated, and the power converter is controlled to work in a bypass mode; when the input voltage and/or the output voltage is detected to be smaller than a preset first voltage threshold value, controlling the power converter to switch from a bypass mode to a transition mode; after the power converter operates in the transition mode for a predetermined time, the power converter is controlled to switch from the transition mode to the normal switching mode.

When the power converter is a buck power converter, in some examples, step S01 includes: when the input voltage and/or the output voltage is detected to be smaller than a preset third voltage threshold value, generating a mode switching instruction with a first instruction state, and controlling the power converter to work in a bypass mode; when the input voltage and/or the output voltage is detected to rise to be larger than a third voltage threshold value and the rising slope of the input voltage and/or the output voltage is larger than a preset threshold value, generating a mode switching instruction with a second instruction state, and controlling the power converter to switch from a bypass mode to a transition mode; and when the input voltage and/or the output voltage is detected to be larger than a preset fourth voltage threshold, controlling the power converter to switch from the transition mode to the normal switch working mode, wherein the fourth voltage threshold is larger than the third voltage threshold. In other examples, step S01 includes: when the input voltage and/or the output voltage is detected to rise to be larger than a third voltage threshold value and the rising slope of the input voltage and/or the output voltage is smaller than a preset threshold value, a mode switching instruction with a first instruction state is generated, and the power converter is controlled to work in a bypass mode; when the input voltage and/or the output voltage are/is detected to be larger than a preset fourth voltage threshold value, the power converter is controlled to be switched to a transition mode from a bypass mode, and the fourth voltage threshold value is larger than the third voltage threshold value; after the power converter operates in the transition mode for a predetermined time, the power converter is controlled to switch from the transition mode to the normal switching mode.

In step S02, a first control signal is generated according to the mode switching command, where the first control signal is used to control on and off of the switching transistor in the bypass unit.

In this embodiment, the first control signal is in an active state in the bypass mode, and is in an inactive state in the transition mode and the normal switching mode.

In step S03, a second control signal is generated according to the mode switching command and the current reference signal, where the second control signal is used to control on and off of the switching transistor in the power unit.

In this embodiment, in the transition mode, the second control signal has a second frequency, and/or the current reference signal is defined according to a clamp compensation signal obtained by clamping the compensation signal via a clamp voltage obtained in advance; in the normal switching mode of operation, the second control signal has a first frequency and the current reference signal is derived from the compensation signal. The second frequency is greater than the first frequency, for example, the second frequency may be more than twice the first frequency, and the compensation signal is obtained by compensating an error amplification signal representing difference information between the output voltage and the reference voltage. And the clamp voltage is obtained in response to sampling, summing and sample-and-hold of the currents flowing through the power cell and the bypass cell in the bypass mode prior to the transition mode; or the clamp voltage is obtained in response to sample-and-hold of the current flowing through the bypass cell in the bypass mode preceding the transition mode.

Specifically, in some embodiments, step S03 further comprises: providing a clock pulse signal with a first frequency in a normal switching operation mode and providing a clock pulse signal with a second frequency in a transition mode under the control of a mode switching instruction; the second control signal is generated from a clock pulse signal defining a frequency of the second control signal and a current reference signal defining a duty cycle of the second control signal.

In other embodiments, step S03 further comprises: providing a time threshold value with a first value in a normal switch operation mode and providing a time threshold value with a second value in a transition mode under the control of a mode switching instruction; the second control signal is generated from a time threshold and a current reference signal, the time threshold being inversely related to the frequency of the second control signal. Wherein the first value is greater than the second value, as one embodiment of the present invention, the first value is at least twice the second value.

In specific implementation, the specific implementation of each step in the control method of the power converter described above may be referred to the foregoing embodiment of the power converter, which is not described herein again.

In summary, the control circuit provided by the embodiment of the application can control the power converter to exit the bypass mode in advance when the rapid jump of the input voltage of the power converter is detected in the bypass mode, or control the power converter to exit the bypass mode in advance when the rapid jump of the input voltage is not detected, and enable the inductance current of the power converter to reach the value corresponding to the load current in a short time in the transition mode by a rapid system response in the transition mode, thereby greatly reducing the deviation amplitude of the output voltage relative to the output set voltage when the power converter is switched in the mode, and improving the stability of the output voltage and the reliability of the load operation of the power converter in the transient process of the mode switching.

Finally, it should be noted that: it is apparent that the above examples are only illustrative of the present application and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present application.

Claims

1. A control circuit of a power converter, the power converter further comprising a power unit and a bypass unit coupled to each other, the control circuit for generating a first control signal and a second control signal for controlling on and off of switching transistors in the bypass unit and the power unit, respectively, the control circuit comprising:

2. The control circuit of claim 1, wherein,

the control signal generating circuit generates the second control signal according to the mode switching instruction and a current reference signal, wherein the current reference signal is limited by a compensation signal in the normal switch working mode, and the compensation signal is obtained after compensating an error amplification signal representing difference information of the output voltage and the reference voltage.

3. The control circuit of claim 2, wherein,

in the transient mode, the current reference signal is defined by a clamp compensation signal obtained after clamping the compensation signal via a clamp voltage acquired in advance.

4. The control circuit of claim 3, wherein the clamp voltage is obtained in response to sampling, summing, and sample-and-hold of current flowing through the power cell and the bypass cell in the bypass mode prior to the transition mode; or alternatively

5. A control circuit according to claim 2 or 3, wherein,

The second control signal has a first frequency in the normal switching mode of operation,

6. The control circuit of claim 5, wherein the control signal generation circuit is configured to: generating the second control signal according to a clock pulse signal and the current reference signal, wherein the clock pulse signal is used for limiting the frequency of the second control signal, and the current reference signal is used for limiting the duty ratio of the second control signal;

7. The control circuit of claim 6, wherein the control signal generation circuit comprises:

8. The control circuit of claim 5, wherein the control signal generation circuit is configured to: generating the second control signal according to a preset time threshold and the current reference signal, wherein the time threshold is inversely related to the frequency of the second control signal;

9. The control circuit of claim 8, wherein the control signal generation circuit comprises:

wherein the timer circuit is configured to:

10. The control circuit of claim 1, wherein the mode control circuit is configured to:

11. The control circuit of claim 1, wherein the mode control circuit is configured to:

12. A control circuit of a power converter, the power converter further comprising a power unit and a bypass unit coupled to each other, the control circuit for generating a first control signal and a second control signal for controlling on and off of switching transistors in the bypass unit and the power unit, respectively, the control circuit comprising:

13. A power converter, comprising:

a control circuit as claimed in any one of claims 1 to 11, or claim 12, for providing control signals to control switching transistors in the power cell and the bypass cell to be turned on and off.

14. A control method of a power converter including a power unit and a bypass unit coupled to each other, the control method comprising:

15. The control method according to claim 14, wherein,

and generating a second control signal according to the mode switching instruction and a current reference signal, wherein the second control signal is used for controlling the on and off of a switching transistor in the power unit, the current reference signal is limited by a compensation signal in the normal switching working mode, and the compensation signal is obtained after compensating an error amplification signal representing difference information of the output voltage and the reference voltage.

16. The control method according to claim 15, wherein,

17. The control method of claim 16, wherein the clamp voltage is obtained in response to sampling, summing, and sample-and-hold of current flowing through the power cell and the bypass cell in the bypass mode prior to the transition mode; or alternatively

18. The control method according to claim 15 or 16, wherein,

the second control signal has a first frequency in the normal switching mode of operation;

19. The control method of claim 18, wherein generating the second control signal from the mode switching command and a current reference signal comprises:

20. The control method of claim 18, wherein generating the second control signal from the mode switching command and a current reference signal comprises:

wherein the first value is greater than the second value.