CN117010321B - EM and IR analysis method for multi-finger MOS device layout - Google Patents

Abstract

A method for EM and IR analysis of a multi-finger MOS device layout includes the following steps: obtaining original layout information; rectangularizing the geometric figures of the gate layer; filtering the rectangle of the gate layer using the geometric figures of the source layer and the drain layer; determining the direction of the processed MOS device according to the width-to-length ratio of the gate layer figure; calculating the width of the processed MOS device and the number of rows and columns of the corresponding array to obtain the coordinate position information of the MOS device array; deleting the original multi-finger MOS device area, generating a new MOS device array according to the coordinate position information of the MOS device array; extracting parasitic parameter information from the layout containing the new MOS device array; performing EM and IR analysis according to the parasitic parameter information, and outputting the analysis results. The method of the present invention greatly simplifies the process of performing accurate EM and IR analysis on the multi-finger MOS device layout, and can complete accurate EM and IR analysis of the multi-finger MOS device layout without manually correcting the layout.

Description

A method for EM and IR analysis of multi-finger MOS device layout

Technical Field

The present invention relates to the technical field of integrated circuit simulation analysis, and in particular to an EM and IR analysis method for a multi-finger MOS device layout.

Background technique

The purpose of the integrated circuit power distribution system is to provide the voltage and current required by the transistors to perform the chip's logical functions. A detailed analysis is required to confirm whether the power distribution method of the chip design is robust. The voltage drop (IR) on the VDD (power supply voltage) network and the ground bounce on the VSS (ground or negative power supply) network will affect the entire timing and function of the design. If their existence is ignored, it is likely to cause the chip design to fail. The high current in the power grid will also cause electromigration (EM) effects, which will cause the metal line performance of the power grid to degrade during the normal life of the chip. These adverse effects will eventually cause circuit failures and serious reliability problems. Therefore, EM and IR analysis must be performed on the chip to optimize the chip's power network design.

Since Multi-finger MOS (multi-finger field effect transistor) devices often occupy a large area in the layout, existing electromigration and current resistance voltage drop analysis technologies (EM and IR) analyze the multi-finger MOS device as a whole. Therefore, it is impossible to accurately simulate the EM and IR conditions inside the multi-finger MOS device and between different fingers, and thus it is impossible to obtain accurate analysis results.

Summary of the invention

In order to solve the defects of the prior art, the purpose of the present invention is to provide an EM and IR analysis method for a multi-finger MOS device layout, which divides the multi-finger MOS devices in the layout pattern to form a MOS device array, so that accurate EM and IR analysis of the layout can be performed to help designers effectively find problems.

In order to achieve the above object, the present invention provides an EM and IR analysis method for a multi-finger MOS device layout, comprising the following steps:

Get the original layout information;

Rectify the geometry of the grid layer;

Filter the rectangle of the gate layer using the geometry of the source and drain layers;

Determine the direction of the processed MOS device according to the width-to-length ratio of the gate layer pattern;

Calculating the width of the processed MOS device and the number of rows and columns of the corresponding array to obtain coordinate position information of the MOS device array;

Deleting the original multi-finger MOS device area, and generating a new MOS device array according to the coordinate position information of the MOS device array;

Extracting parasitic parameter information from a layout containing the new MOS device array;

According to the parasitic parameter information, EM and IR analysis are performed and the analysis results are output.

Furthermore, the original layout information includes: geometric information of the gate layer, geometric information of the drain layer, geometric information of the gate layer, and finger attribute information corresponding to the multi-finger MOS device area.

Furthermore, the step of filtering the rectangle of the gate layer using the geometric figures of the source layer and the drain layer further includes: if there are no source figures and drain figures intersecting or adjacent to the gate layer geometric figures on both sides, the gate figures are filtered out, otherwise they are retained.

Furthermore, the step of determining the direction of the processed MOS device according to the width-to-length ratio of the gate layer pattern further includes: determining the direction of the processed MOS device according to the length ratio of the X direction to the Y direction of the rectangle in the gate layer, when the length ratio of the X direction to the Y direction is less than 1, the direction of the MOS device is the Y direction, otherwise the direction of the MOS device is the X direction.

Furthermore, the step of calculating the width of the MOS device after processing and the number of rows and columns of the corresponding array to obtain the coordinate position information of the MOS device array further includes:

The width of the processed MOS device is equal to the ratio of the total width of the MOS device to the number of fingers;

The number of columns of the MOS device array is equal to the number of gate patterns after filtering;

The number of rows of the MOS device array is equal to the ratio of the number of fingers to the number of columns of the MOS device array.

Furthermore, the step of extracting parasitic parameter information from the layout containing the new MOS device array includes extracting parasitic resistance and coordinate information.

In order to achieve the above-mentioned purpose, the present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a program running on the processor, and when the processor runs the program, the steps of the EM and IR analysis method of the multi-finger MOS device layout as described above are executed.

In order to achieve the above object, the present invention further provides a computer-readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the EM and IR analysis method of the multi-finger MOS device layout as described above.

The EM and IR analysis method of the multi-finger MOS device layout provided by the present invention has the following beneficial effects compared with the prior art:

The multi-finger MOS device area is segmented based on the original layout to generate a MOS device array, and then the layout containing the MOS device array is subjected to EM and IR analysis, which greatly simplifies the process of accurate EM and IR analysis of the multi-finger MOS device layout. Accurate EM and IR analysis of the multi-finger MOS device layout can be completed without manual layout correction.

Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

FIG1 is a flow chart of an EM and IR analysis method for a multi-finger MOS device layout according to the present invention;

FIG2 is a schematic diagram of an original multi-finger MOS layout according to the present invention;

FIG3 is a schematic diagram of rectangularization of a geometric figure of a gate layer according to the present invention;

FIG4 is a schematic diagram of a filter grid pattern according to the present invention;

FIG5 is a schematic diagram of a MOS device array generated according to the present invention;

FIG. 6 is a schematic diagram of the structure of an electronic device according to the present invention.

Detailed ways

The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are only for exemplary purposes and are not intended to limit the scope of protection of the present invention.

The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more". "Plurality" should be understood as two or more.

The EM and IR analysis method of the multi-finger MOS device layout of the present invention pre-processes the multi-finger MOS device area based on the geometric information of the source layer, the geometric information of the drain layer, the geometric information of the gate layer of the original layout and the finger attribute information corresponding to the multi-finger MOS device area, generates a MOS device array, and then performs EM and IR analysis on the layout containing the MOS device array.

FIG. 1 is a flow chart of the EM and IR analysis method of the multi-finger MOS device layout according to the present invention. The EM and IR analysis method of the multi-finger MOS device layout according to the present invention will be described in detail below with reference to FIG. 1 .

In step 101, original layout information is obtained.

In the embodiment of the present invention, the geometric figures of the source layer, the drain layer, and the gate layer of the original layout are respectively obtained, and the attribute information of the total width and the number of fingers of the corresponding multi-finger MOS device area is obtained, as shown in FIG2 , wherein FIG2 (b) is the figure of the gate layer, FIG2 (c) is the figure of the source layer, and FIG2 (d) is the figure of the drain layer. The total width value of the corresponding MOS device is w_total, and the corresponding number of fingers nf=6.

At step 102, the gate layer geometry is rectangularized.

In the embodiment of the present invention, the geometric figures of the gate layer are rectangularized to ensure that the geometric figures of the gate layer are all rectangles, as shown in FIG. 3 , in which the corresponding rectangles are numbered.

In step 103, the rectangle of the gate layer is filtered using the geometry of the source layer and the drain layer.

In an embodiment of the present invention, if the source and drain patterns are not distributed on both sides of the gate pattern and intersect or are adjacent to it, a MOS device cannot be formed and the gate pattern needs to be deleted. Refer to the gate pattern numbered 1 in FIG3 to illustrate this process. Since the pattern only has a drain pattern on the right side and no source pattern on the left side, a MOS device cannot be formed under the pattern, so it will be filtered out. Therefore, the gate patterns numbered 2 to 22 in FIG3 are judged in a similar manner, and the gate patterns that cannot form MOS devices are filtered out. Finally, only the gate patterns numbered 2 to 7 are retained, and the result of the multi-finger MOS device area is obtained as shown in FIG4.

In step 104, the orientation of the processed MOS device is determined according to the width-to-length ratio of the gate layer pattern.

In the embodiment of the present invention, the direction of the processed MOS device is determined according to the length ratio of the X direction to the Y direction of the rectangular figure in the gate layer. If the length ratio of the X direction to the Y direction is less than 1, then the direction of the MOS device is the Y direction. Otherwise, the direction of the MOS device is the X direction. As shown in FIG. 4 , the MOS device in this example is in the Y direction.

In step 105, the width of the processed MOS device and the number of rows and columns of the corresponding array are calculated to obtain the coordinate position information of the source, drain and gate of each device in the MOS device array.

In the embodiment of the present invention, the width of the processed MOS device is equal to the ratio of the total width of the MOS device to the number of fingers; the number of columns of the MOS device array is equal to the number of gate patterns after filtering; the number of rows of the MOS device array is equal to the ratio of the number of fingers to the number of columns of the MOS device array.

As shown in FIG. 4 , the number of columns of the MOS device array is equal to the number of gate patterns 6 after the filtering process in step 103 , the number of fingers is 6, and the number of rows of the MOS device array is 1.

In step 106, a new MOS device array is generated according to the calculated MOS device array coordinate position information.

In the embodiment of the present invention, the original multi-finger MOS device region is first deleted, and then a new MOS device array is generated according to the calculated coordinate positions in the MOS device array.

As shown in FIG5 , the multi-finger MOS device region in FIG4 is first deleted, and then a new MOS device array shown by the thick black frame in FIG5 is generated according to the coordinate position information of the MOS device array. There is a certain interval between the new MOS device regions, and the area occupied by the new MOS device regions is also significantly reduced.

In step 107, parasitic parameter information is extracted from the layout containing the new MOS device region.

Parasitic devices are prone to appear in integrated circuits, and are even widely distributed throughout the chip. These parasitic devices are usually unavoidable, so integrated circuit designers need to fully consider these factors and leave some margin to minimize the impact of parasitic parameters. Parasitic parameters include parasitic resistance, parasitic capacitance, and parasitic inductance.

In the embodiment of the present invention, the extracted parasitic parameter information includes information such as parasitic resistance and coordinates.

In step 108, EM and IR analysis are performed based on the parasitic parameter information, and the analysis results are output.

The method of the present invention divides the multi-finger MOS device area based on the original layout to generate a MOS device array, then extracts parasitic parameters of the layout containing the MOS device array, builds a matrix based on the parasitic resistance network and solves it, and finally generates EM and IR analysis results, which greatly simplifies the process of performing accurate EM and IR analysis on the multi-finger MOS device layout. This method can accurately analyze the EM and IR of the multi-finger MOS device layout without manually correcting the layout.

In an embodiment of the present invention, an electronic device is further provided. FIG. 6 is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. As shown in FIG. 6 , the electronic device of the present invention includes a processor 601 and a memory 602, wherein:

The memory 602 stores a computer program. When the computer program is read and executed by the processor 601 , the computer program executes the steps in the embodiment of the EM and IR analysis method for the multi-finger MOS device layout as described above.

In an embodiment of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored, wherein the computer program is configured to execute the steps in the embodiment of the EM and IR analysis method of the multi-finger MOS device layout as described above when running.

In this embodiment, the above-mentioned computer-readable storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

Those skilled in the art can understand that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention is described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions recorded in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims (7)

1. An EM and IR analysis method for a multi-finger MOS device layout, comprising the following steps: Get the original layout information; Rectify the geometry of the grid layer; Filter the rectangle of the gate layer using the geometry of the source and drain layers; Determine the direction of the processed MOS device according to the width-to-length ratio of the gate layer pattern; Calculating the width of the processed MOS device and the number of rows and columns of the corresponding array to obtain coordinate position information of the MOS device array; Deleting the original multi-finger MOS device area, and generating a new MOS device array according to the coordinate position information of the MOS device array; Extracting parasitic parameter information from a layout containing the new MOS device array; Perform EM and IR analysis according to the parasitic parameter information and output the analysis results; The step of filtering the rectangle of the gate layer using the geometric figures of the source layer and the drain layer further includes: if there are no source figures and drain figures intersecting or adjacent to the geometric figures of the gate layer on both sides, the geometric figures of the gate layer are filtered out, otherwise they are retained. 2. The EM and IR analysis method of the multi-finger MOS device layout according to claim 1, characterized in that the original layout information includes: geometric information of the gate layer, geometric information of the drain layer, geometric information of the gate layer, and finger attribute information corresponding to the multi-finger MOS device area. 3. The EM and IR analysis method of the multi-finger MOS device layout according to claim 1 is characterized in that the step of determining the direction of the processed MOS device according to the width-to-length ratio of the gate layer pattern further comprises: determining the direction of the processed MOS device according to the length ratio of the X direction to the Y direction of the rectangle in the gate layer, when the length ratio of the X direction to the Y direction is less than 1, the direction of the MOS device is the Y direction, otherwise the direction of the MOS device is the X direction. 4. The EM and IR analysis method of the multi-finger MOS device layout according to claim 1, wherein the step of calculating the width of the MOS device after processing and the number of rows and columns of the corresponding array to obtain the coordinate position information of the MOS device array further comprises: The width of the processed MOS device is equal to the ratio of the total width of the MOS device to the number of fingers; The number of columns of the MOS device array is equal to the number of gate patterns after filtering; The number of rows of the MOS device array is equal to the ratio of the number of fingers to the number of columns of the MOS device array. 5. The EM and IR analysis method of a multi-finger MOS device layout according to claim 1, wherein the step of extracting parasitic parameter information of the layout containing the new MOS device array comprises extracting parasitic resistance and coordinate information. 6. An electronic device, characterized in that it comprises a memory and a processor, wherein the memory stores a program running on the processor, and when the processor runs the program, the steps of the EM and IR analysis method of the multi-finger MOS device layout according to any one of claims 1 to 5 are executed. 7. A computer-readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the EM and IR analysis method of the multi-finger MOS device layout according to any one of claims 1 to 5 is implemented.