CN116998104A - Inverter control device, inverter circuit, motor module, and inverter control method - Google Patents

Abstract

An inverter control device for controlling a three-phase inverter of a two-phase modulation scheme, the three-phase inverter including a first input terminal, a second input terminal, a capacitor, and three series connected bodies, the inverter control device including a signal generation unit for generating three PWM signals to be input to the three series connected bodies, the PWM signals including at least an inverted PWM section for applying an inverted PWM signal, the inverted PWM signal being an inverted phase with respect to a normal phase PWM signal, the inverted PWM section being a section for applying the normal phase PWM signal to two of three phases and the inverted PWM signal to one of the three phases, the signal generation unit selecting, as an inverted PWM phase, a phase in which a current zero crossing occurs next in a time axis direction, in the inverted PWM section.

Description

Inverter control device, inverter circuit, motor module, and inverter control method

Technical Field

The invention relates to an inverter control device, an inverter circuit, a motor module, and an inverter control method.

Background

An inverter control device that controls a three-phase inverter is known (for example, patent document 1). In the inverter control device described in patent document 1, which of the two triangular waves is used in comparison with each phase and which phase is fixed to the maximum value or the minimum value is switched according to the output voltage phase and the output current phase of the inverter.

Prior art literature

Patent literature

Patent document 1: international publication No. 2017/34028

Disclosure of Invention

Problems to be solved by the invention

However, in the inverter control device described in patent document 1, when the current phase is delayed from the voltage phase, there are 12 operation states in the electrical angle 1 period. When the delay of the current phase is large and the power factor is low, a different operation state is further applied. Therefore, the switching control of the operation state becomes complicated, and the control program becomes complicated.

The present invention has been made in view of the above-described problems, and an object thereof is to provide an inverter control device, an inverter circuit, a motor module, and an inverter control method that can simplify a control program.

Means for solving the problems

The inverter control device of the present invention controls a three-phase inverter of a two-phase modulation scheme. The three-phase inverter includes a first input terminal, a second input terminal, a capacitor, and three strings. A first voltage is applied to the first input terminal. A second voltage is applied to the second input terminal. The second voltage is lower than the first voltage. The capacitor is connected between the first input terminal and the second input terminal. The three series bodies are connected with two semiconductor switching elements in series. The inverter control device is provided with a signal generation unit. The signal generating unit generates three PWM signals to be input to the three series bodies, respectively. The PWM signal includes at least an inverted PWM interval to which an inverted PWM signal is applied. The inverted PWM signal is in an inverted phase relative to the positive phase PWM signal. The inverted PWM interval is an interval in which the normal phase PWM signal is applied to two of three phases and the inverted PWM signal is applied to one of the three phases. The signal generating unit selects, as an inverted PWM phase, a phase in which a current zero-crossing occurs next in the time axis direction in the inverted PWM section.

An inverter circuit according to an example of the present invention includes the inverter control device described above, a first input terminal, a second input terminal, a capacitor, and three series bodies. A first voltage is applied to the first input terminal. A second voltage is applied to the second input terminal. The second voltage is lower than the first voltage. The capacitor is connected between the first input terminal and the second input terminal. The three series bodies are connected with two semiconductor switching elements in series.

An exemplary motor module of the present invention includes the inverter control device, the three-phase inverter, and the three-phase motor described above. The three-phase inverter is controlled by the inverter control device. The three-phase inverter is a two-phase modulation scheme. The three-phase motor is input to the output of the inverter.

An exemplary inverter control method of the present invention is a method of controlling a three-phase inverter of a two-phase modulation scheme. The three-phase inverter includes a first input terminal, a second input terminal, a capacitor, and three strings. A first voltage is applied to the first input terminal. A second voltage is applied to the second input terminal. The second voltage is lower than the first voltage. The capacitor is connected between the first input terminal and the second input terminal. The three series bodies are connected with two semiconductor switching elements in series. Three PWM signals are input to each of the three strings. The PWM signal includes at least an inverted PWM interval to which an inverted PWM signal is applied. The inverted PWM signal is in an inverted phase relative to the positive phase PWM signal. The inverted PWM interval is an interval in which the normal phase PWM signal is applied to two of three phases and the inverted PWM signal is applied to one of the three phases. The inverter control method includes: and a selection step of selecting, as an inverted PWM phase, a phase which generates a current zero-crossing next as viewed in the time axis direction in the inverted PWM section.

Effects of the invention

According to the exemplary present invention, the control program can be simplified.

Drawings

Fig. 1 is a block diagram of a motor module according to an embodiment of the present invention.

Fig. 2 is a circuit diagram showing an inverter section.

Fig. 3 is a diagram showing an output voltage and an output current.

Fig. 4 is a diagram showing an output voltage and an output current.

Fig. 5A is a diagram for explaining the charge-discharge current of the capacitor.

Fig. 5B is a diagram for explaining the charge-discharge current of the capacitor.

Fig. 5C is a diagram for explaining the charge-discharge current of the capacitor.

Fig. 6A is a diagram for explaining the charge-discharge current of the capacitor.

Fig. 6B is a diagram for explaining the charge-discharge current of the capacitor.

Fig. 6C is a diagram for explaining the charge-discharge current of the capacitor.

Fig. 7A is a diagram for explaining the charge/discharge current of the capacitor.

Fig. 7B is a diagram for explaining the charge-discharge current of the capacitor.

Fig. 7C is a diagram for explaining the charge-discharge current of the capacitor.

Fig. 8 is a diagram showing an output voltage and an output current.

Fig. 9 is a diagram showing an output voltage and an output current.

Fig. 10 is a diagram showing an output voltage and an output current.

Fig. 11 is a diagram showing an output voltage and an output current.

Fig. 12 is a diagram showing an output voltage and an output current.

Fig. 13A is a diagram for explaining the charge/discharge current of the capacitor.

Fig. 13B is a diagram for explaining the charge/discharge current of the capacitor.

Fig. 13C is a diagram for explaining the charge/discharge current of the capacitor.

Fig. 14A is a diagram for explaining the charge/discharge current of the capacitor.

Fig. 14B is a diagram for explaining the charge-discharge current of the capacitor.

Fig. 14C is a diagram for explaining the charge-discharge current of the capacitor.

Fig. 15 is a diagram showing an output voltage and an output current.

Fig. 16 is a diagram showing an output voltage and an output current.

Fig. 17 is a diagram showing a section to which inverse PWM is applied and a phase to which an inverse PWM signal is applied in each divided section.

Fig. 18 is a flowchart showing an inverter control method.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding portions are denoted by the same reference numerals, and the description thereof will not be repeated.

Referring to fig. 1 and 2, a motor module 200 according to an embodiment of the present invention will be described. Fig. 1 is a block diagram of a motor module 200 according to an embodiment of the present invention. Fig. 2 is a circuit diagram showing the inverter section 110.

As shown in fig. 1, the motor module 200 includes a motor drive circuit 100 and a three-phase motor M. The three-phase motor M is driven by a motor driving circuit 100. The three-phase motor M is, for example, a brushless DC motor. The three-phase motor M has a U-phase, a V-phase, and a W-phase. The motor drive circuit 100 corresponds to an example of an "inverter circuit".

The motor driving circuit 100 controls driving of the three-phase motor M in a two-phase modulation manner. The motor drive circuit 100 includes an inverter unit 110 and an inverter control device 12. The inverter unit 110 corresponds to an example of a "three-phase inverter".

The inverter unit 110 is controlled by the inverter control device 12. The inverter 110 is a two-phase modulation system and is three-phase. The inverter section 110 has three output terminals 102. The three output terminals 102 include an output terminal 102u, an output terminal 102v, and an output terminal 102w. The three output terminals 102 output three-phase output voltages and three-phase output currents to the three-phase motor M. Specifically, the output terminal 102U outputs the U-phase output voltage Vu and the U-phase output current Iu to the three-phase motor M. The output terminal 102V outputs the V-phase output voltage Vv and the V-phase output current Iv to the three-phase motor M. The output terminal 102W outputs the W-phase output voltage Vw and the W-phase output current Iw to the three-phase motor M. The output of the inverter unit 110 is input to the three-phase motor M.

As shown in fig. 2, the inverter 110 includes a first input terminal P, a second input terminal N, a capacitor C, and three serial bodies 112. The inverter unit 110 further includes a dc voltage source B. The dc voltage source B may be external to the inverter unit 110.

A first voltage V1 is applied to the first input terminal P. The first input terminal P is connected to a dc voltage source B.

A second voltage V2 is applied to the second input terminal N. The second input terminal N is connected to a dc voltage source B. The second voltage V2 is lower than the first voltage V1.

The capacitor C is connected between the first input terminal P and the second input terminal N.

Two semiconductor switching elements are connected in series in the three series bodies 112. The semiconductor switching element is, for example, an IGBT (insulated gate bipolar transistor). The semiconductor switching element may be another transistor such as a field effect transistor. The three series bodies 112 include a series body 112u, a series body 112v, and a series body 112w. The three series bodies 112 are connected in parallel with each other. One end of each of the three series bodies 112 is connected to the first input terminal P. The other ends of the three serial bodies 112 are connected to the second input terminal N. The rectifying elements D are connected in parallel to the semiconductor switching elements, respectively, with the first input terminal P side (upper side of the drawing) as a cathode and the second input terminal N side (lower side of the drawing) as an anode. In the case of using a field effect transistor as the semiconductor switching element, a parasitic diode may be used as the rectifying element.

The three series bodies 112 each have a first semiconductor switching element and a second semiconductor switching element. Specifically, the series body 112u includes a first semiconductor switching element Up and a second semiconductor switching element Un. The series body 112v has a first semiconductor switching element Vp and a second semiconductor switching element Vn. The series body 112w has a first semiconductor switching element Wp and a second semiconductor switching element Wn.

The first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are connected to the first input terminal P. In other words, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are semiconductor switching elements on the high voltage side.

The second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are connected to the second input terminal N. In other words, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are semiconductor switching elements on the low voltage side.

The first semiconductor switching element and the second semiconductor switching element are connected at a connection point 114. Specifically, the first semiconductor switching element Up and the second semiconductor switching element Un are connected at a connection point 114 u. The first semiconductor switching element Vp and the second semiconductor switching element Vn are connected at a connection point 114 v. The first semiconductor switching element Wp and the second semiconductor switching element Wn are connected at a connection point 114 w.

The connection points 114 of the three series bodies 112 are connected to the three output terminals 102, respectively. Specifically, the connection point 114u in the series body 112u is connected to the output terminal 102 u. Connection point 114v in serial body 112v is connected to output terminal 102 v. The connection point 114w in the series body 112w is connected to the output terminal 102 w.

The PWM signal is input to the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp. The PWM signal is output from the signal generating section 120. Hereinafter, in this specification, the PWM signal input to the first semiconductor switching element Up may be referred to as an "upppwm signal". In addition, the PWM signal input to the first semiconductor switching element Vp is sometimes referred to as a "VpPWM signal". The PWM signal input to the first semiconductor switching element Wp is sometimes referred to as a "WpPWM signal". The first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are switched on and off in a predetermined PWM period. For example, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are turned on when the upppwm signal, the VpPWM signal, and the WpPWM signal are high, respectively. On the other hand, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are turned off when the upppwm signal, the VpPWM signal, and the WpPWM signal are low, respectively.

The PWM signal is input to the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn. The PWM signal is output from the signal generating section 120. Hereinafter, in this specification, the PWM signal input to the second semiconductor switching element Un may be referred to as a "Un PWM signal". The PWM signal input to the second semiconductor switching element Vn may be referred to as a "VnPWM signal". The PWM signal input to the second semiconductor switching element Wn is sometimes referred to as a "WnPWM signal". The second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are switched on and off at a prescribed PWM period. For example, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned on when the Un pwm signal, the VnPWM signal, and the WnPWM signal are high levels, respectively. On the other hand, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned off when the Un pwm signal, the VnPWM signal, and the WnPWM signal are low levels, respectively.

As shown in fig. 1, the inverter control device 12 includes a signal generation unit 120. The signal generating unit 120 includes a carrier generating unit 122, a voltage command value generating unit 124, and a comparing unit 126. The signal generating unit 120 is a hardware circuit including a processor such as a CPU (Central Processing Unit ), an ASIC (Application Specific Integrated Circuit, application specific integrated circuit), and the like. The processor of the signal generating unit 120 executes a computer program stored in a memory device, and thereby functions as a carrier wave generating unit 122, a voltage command value generating unit 124, and a comparing unit 126.

The signal generation section 120 controls the inverter section 110. Specifically, the signal generating unit 120 generates a PWM signal and outputs the PWM signal to control the inverter unit 110. More specifically, the signal generating unit 120 generates three PWM signals to be input to the three serial bodies 112, respectively.

The carrier generating unit 122 generates a carrier signal. The carrier signal is, for example, a triangular wave. In addition, the carrier signal may be a sawtooth wave.

The voltage command value generation unit 124 generates a voltage command value. The voltage command value corresponds to a voltage value output from the motor drive circuit 100. That is, the voltage command value generation unit 124 generates voltage values corresponding to the output voltage Vu, the output voltage Vv, and the output voltage Vw as voltage command values.

The comparison unit 126 generates a PWM signal by comparing the carrier signal and the voltage command value.

The operation of the signal generating unit 120 will be described with reference to fig. 3. Fig. 3 is a diagram showing an output voltage and an output current.

The upper diagram of fig. 3 shows the output voltage Vu, the output voltage Vv and the output voltage Vw. In the upper diagram of fig. 3, the output voltage Vu is shown by a solid line, the output voltage Vv is shown by a broken line, and the output voltage Vw is shown by a dash-dot line. The vertical axis of fig. 3 shows the voltage values normalized by the input voltages V1 to V2, and the output voltages of the respective phases take values in the range of 0 to 1. The value also represents a duty ratio, which is a ratio of the on time of the first semiconductor switching element of each phase to the PWM period. The horizontal axis of fig. 3 represents the electrical rotation angle of the motor in degrees.

The lower graph of fig. 3 shows the output current Iu, the output current Iv and the output current Iw. In the lower diagram of fig. 3, the output current Iu is shown by a solid line, the output current Iv is shown by a broken line, and the output current Iw is shown by a dash-dot line. The horizontal axis of fig. 3 represents the electrical rotation angle of the motor in degrees.

As shown in fig. 3, the output voltage waveform has a period in which one of the three phases becomes off-fixed. The off-fixation means that the first semiconductor switching element is continuously turned off and the second semiconductor switching element is continuously turned on during a period of a plurality of PWM periods. Specifically, the output voltage Vu becomes off-fixed at an electrical angle of 210 degrees to an electrical angle of 330 degrees. The output voltage Vv becomes off-fixed at an electrical angle of 0 to 90 degrees and at an electrical angle of 210 to 330 degrees. The output voltage Vw becomes off-fixed at an electrical angle of 210 degrees to an electrical angle of 330 degrees. In the present specification, as shown in fig. 3, a modulation scheme in which one of three phases of the output voltage waveform is turned off and fixed may be referred to as a modulation scheme in the off and fixed mode (Min type).

As shown in fig. 3, the signal generating unit 120 divides the electrical angle 1 into a plurality of divided sections. The signal generating unit 120 divides the electrical angle 1 cycle into a plurality of divided sections for each current zero crossing. Specifically, the signal generating unit 120 divides the electrical angle 1 into a first divided section T1, a second divided section T2, a third divided section T3, a fourth divided section T4, a fifth divided section T5, and a sixth divided section T6. In the present specification, the first divided section T1, the second divided section T2, the third divided section T3, the fourth divided section T4, the fifth divided section T5, and the sixth divided section T6 may be collectively referred to as a divided section T. The present invention is not limited to the case where the signal generating unit 120 is entirely divided into the divided sections T at the current zero-crossing points. For example, the signal generating unit 120 may divide the current into the divided sections T in the vicinity of the zero-crossing of the current. The detection of the current zero-crossing point may be obtained by direct observation by a means such as a current sensor or by prediction from calculation.

The second segment T2 immediately follows the first segment T1. The third segment T3 is immediately followed by the second segment T2. The fourth segment T4 immediately follows the third segment T3. The fifth segment T5 is immediately followed by the fourth segment T4. The sixth segment T6 is immediately followed by the fifth segment T5. Here, the first division section T1 is an electrical angle of 20 degrees to 80 degrees. The second division section T2 has an electrical angle of 80 degrees to 140 degrees. The third segment T3 has an electrical angle of 140 degrees to 200 degrees. The fourth division section T4 has an electrical angle of 200 degrees to 260 degrees. The fifth division section T5 is 260 to 320 degrees in electrical angle. The sixth division section T6 is an electrical angle 320 to 360 degrees.

The first divided section T1 is a section in which only the V-phase output current Iv is negative. The second division section T2 is a section in which only the output current Iu of the U phase is positive. The third divided section T3 is a section in which only the W-phase output current Iw is negative. The fourth divided section T4 is a section in which only the V-phase output current Iv is positive. The fifth divided section T5 is a section in which only the output current Iu of the U phase is negative. The sixth divided section T6 is a section in which only the W-phase output current Iw is positive.

The PWM signal includes at least an inverted PWM interval to which the inverted PWM signal is applied. The inverted PWM signal is inverted relative to the normal PWM signal. The opposite phase indicates, for example, when switching is performed in the U-phase and the V-phase, the phases are shifted so that the state where only the first semiconductor switching element Up is turned on and the state where only the first semiconductor switching element Vp is turned on exist in the PWM1 period. More preferably, the opposite phase indicates that the phase is shifted so that the state where both the first semiconductor switching element Up and the first semiconductor switching element Vp are on and the state where both the first semiconductor switching element Up and the first semiconductor switching element Vp are off do not exist in the PWM1 period. For example, the opposite phase represents a 180 degree phase shift. In addition, it may be slightly offset from 180 degrees. The inverted PWM interval is an interval in which a positive phase PWM signal is applied to two of the three phases and an inverted PWM signal is applied to one of the three phases.

The signal generating unit 120 determines, for each of the plurality of divided sections T, any one of a normal phase PWM section and an inverse phase PWM section in which the normal phase PWM signal is applied to all three phases. Here, the signal generating unit 120 applies the inverse PWM period to the first divided period T1, the third divided period T3, and the fifth divided period T5. In the second divided section T2, the fourth divided section T4, and the sixth divided section T6, the signal generating unit 120 applies the normal phase PWM section to all phases.

In the inverted PWM section, the signal generating unit 120 selects, as the inverted PWM phase, a phase in which a current zero-crossing occurs next in the time axis direction. Specifically, in the first divided section T1, which is the inverted PWM section, the W phase in which the current zero crossing occurs next is selected as the inverted PWM phase. In a third divided section T3 which is an inverted PWM section, a U-phase in which a current zero-crossing occurs next in the time axis direction is selected as an inverted PWM phase. In a fifth divided section T5 which is an inverted PWM section, a V-phase which causes a current zero-crossing next viewed in the time axis direction is selected as an inverted PWM phase.

The signal generating unit 120 switches the phase to which the inverted PWM signal is applied in the inverted PWM section to the normal phase PWM signal at the current zero crossing. The phase where the current zero-crossing occurs represents the phase where the absolute value of the observed current is smallest in the time axis direction. The present invention is not limited to the signal generation unit 120 switching the phase to which the inverted PWM signal is applied in the inverted PWM interval to the normal phase PWM signal entirely at the current zero-crossing point. For example, the signal generating unit 120 may switch the phase to which the inverted PWM signal is applied in the inverted PWM section to the normal phase PWM signal in the vicinity of the current zero-crossing. The detection of the current zero-crossing point may be obtained by direct observation by a means such as a current sensor or by prediction from calculation.

The selection of the normal phase PWM section and the reverse phase PWM section by the signal generating section 120 will be described with reference to fig. 4 to 7C. Fig. 4 is a diagram showing an output voltage and an output current. Fig. 5A to 7C are diagrams for explaining charge/discharge current of the capacitor C.

As shown in fig. 4, the phases of the output currents (output current Iu, output current Iv, and output current Iw) of the three phases are delayed by 20 degrees from the phases of the output voltages (output voltage Vu, output voltage Vv, and output voltage Vw) of the three phases.

First, a case where normal phase PWM signals are input to the first semiconductor switching element in the section (a) will be described. Fig. 5A to 5C are diagrams showing sections in which the electrical angle is 140 degrees to 200 degrees in the section (a).

As shown in fig. 5C, a positive PWM signal is input to the first semiconductor switching element Up. The first semiconductor switching element Vp is inputted with a positive PWM signal. A low-level signal is input to the first semiconductor switching element Wp.

In the section (1) in fig. 5C, as shown in fig. 5A, the Up gate signal and the Vp gate signal are at high level. Further, the Wp gate signal is low. Accordingly, the first semiconductor switching element Up and the first semiconductor switching element Vp are turned on, and the first semiconductor switching element Wp is turned off. On the other hand, the second semiconductor switching element Un and the second semiconductor switching element Vn are turned off, and the second semiconductor switching element Wn is turned on. Accordingly, the discharge current from the capacitor C increases.

In the section (2) in fig. 5C, as shown in fig. 5B, the Up gate signal, the Vp gate signal, and the Wp gate signal are at low level. Accordingly, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are turned off. On the other hand, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned on. Therefore, the charging current to the capacitor C increases.

In this way, in the case where the (a) section normal phase PWM is inputted to the first semiconductor switching element, the charge-discharge current from the capacitor C increases.

Next, a case where inverse PWM is applied to the section (a) will be described. Fig. 6A to 6C are diagrams showing sections in which the electrical angle is 140 degrees to 200 degrees in the section (a).

As shown in fig. 6C, an inverted PWM signal is input to the first semiconductor switching element Up. The first semiconductor switching element Vp is inputted with a positive PWM signal. A low-level signal is input to the first semiconductor switching element Wp.

In the section (1) in fig. 6C, the Vp gate signal is at a high level as shown in fig. 6A. Further, the Up gate signal and the Wp gate signal are low. Accordingly, the first semiconductor switching element Vp is turned on, and the first semiconductor switching element Up and the first semiconductor switching element Wp are turned off. On the other hand, the second semiconductor switching element Vn is turned off, and the second semiconductor switching element Un and the second semiconductor switching element Wn are turned on. Therefore, compared with the case of fig. 5A, the inverter current is dispersed, and the charge/discharge current of the capacitor C can be suppressed.

In the section (2) in fig. 6C, as shown in fig. 6B, the Up gate signal is at a high level. In addition, vp gate signal and Wp gate signal are low. Accordingly, the first semiconductor switching element Up is turned on, and the first semiconductor switching element Vp and the first semiconductor switching element Wp are turned off. On the other hand, the second semiconductor switching element Un is turned off, and the second semiconductor switching element Vn and the second semiconductor switching element Wn are turned on. Therefore, compared with the case of fig. 5B, the inverter current is dispersed, and the charge/discharge current of the capacitor C can be suppressed.

In this way, if the inverse PWM is applied in the (a) interval, the inverter current is dispersed, and the charge/discharge current of the capacitor C can be suppressed.

Next, a case where inverse PWM is applied in the (B) section will be described. Fig. 7A to 7C are diagrams showing sections in which the electrical angle is 80 degrees to 140 degrees in the section (B).

As shown in fig. 7C, a positive PWM signal is input to the first semiconductor switching element Up. An inverted PWM signal is input to the first semiconductor switching element Vp. A low-level signal is input to the first semiconductor switching element Wp.

In the section (1) in fig. 7C, as shown in fig. 7A, the Up gate signal is at a high level. In addition, vp gate signal and Wp gate signal are low. Accordingly, the first semiconductor switching element Up is turned on, and the first semiconductor switching element Vp and the first semiconductor switching element Wp are turned off. On the other hand, the second semiconductor switching element Un is turned off, and the second semiconductor switching element Vn and the second semiconductor switching element Wn are turned on.

In the section (2) in fig. 7C, the Vp gate signal is at a high level as shown in fig. 7B. Further, the Up gate signal and the Wp gate signal are low. Accordingly, the first semiconductor switching element Vp is turned on, and the first semiconductor switching element Up and the first semiconductor switching element Wp are turned off. On the other hand, the second semiconductor switching element Vn is turned off, and the second semiconductor switching element Un and the second semiconductor switching element Wn are turned on. In this case, a reverse current flows into the capacitor C, and the charge/discharge current of the capacitor C increases. Therefore, in the (B) section, the PWM waveform at the positive phase as shown in fig. 5C is preferably applied.

The selection of the normal phase PWM section and the reverse phase PWM section of the signal generating section 120 will be described with reference to fig. 7A to 7C and fig. 8. Fig. 8 is a diagram showing an output voltage and an output current.

As shown in fig. 8, the phases of the output currents (output current Iu, output current Iv, and output current Iw) of the three phases are delayed by 40 degrees from the phases of the output voltages (output voltage Vu, output voltage Vv, and output voltage Vw) of the three phases.

If the phase delay of the three-phase output current exceeds 30 degrees, the interval (a) is reduced by an excess amount, and the interval (C) is generated. The interval (C) corresponds to a period from when the stationary phase is switched off to when the current zero-crossing occurs.

In the section (C) where the electrical angle is 90 degrees to 100 degrees, as described with reference to fig. 7A to 7C, a reverse current flows into the capacitor C, and the charge/discharge current of the capacitor C increases. Therefore, in the (C) section, the PWM waveform at the positive phase as shown in fig. 5C is preferably applied.

The reverse phase application section is further described with reference to fig. 9. Fig. 9 is a diagram showing an output voltage and an output current. Fig. 9 is a diagram showing a case where the rotation direction of the motor M is CW rotation (clockwise rotation). That is, the rotation direction is a direction in which the electrical angle is from 0 degrees toward 360 degrees.

As shown in fig. 9, the phases of the output currents (output current Iu, output current Iv, and output current Iw) of the three phases are delayed by 40 degrees from the phases of the output voltages (output voltage Vu, output voltage Vv, and output voltage Vw) of the three phases.

The inverted PWM interval is applied to the first divided interval T1, the third divided interval T3, and the fifth divided interval T5. As described with reference to fig. 3, in the inverted PWM section, a phase in which a current zero-crossing occurs next in the time axis direction is selected as an inverted PWM phase. For example, in the first segment T1, positive PWM signals are used for V and U phases among the three phases, and negative PWM signals are used for W among the three phases. Therefore, as shown in fig. 9, even when the phase of the output current of the three phases is delayed by more than 30 degrees from the output voltage of the three phases, and a (C) section is generated in which the inverted PWM signal is preferably not applied, the W phase to which the inverted PWM signal is applied before the (C) section is continuously turned off in the (C) section, and the positive PWM signal is automatically applied to the U phase and the V phase to be switched in the (C) section. Therefore, in the case where the current phase is delayed by more than 30 degrees and the case where it is not more than 30 degrees, there is no need to make a case distinction. Therefore, the control program can be simplified.

In the third division section T3, positive PWM signals are used for V and W phases in the three phases, and inverted PWM signals are used for U in the three phases. Therefore, the positive PWM signal is automatically applied to the V-phase and W-phase switching in the (C) section, similarly to the first divided section T1.

In the fifth segment T5, positive PWM signals are used for U and W phases among the three phases, and negative PWM signals are used for V among the three phases. Therefore, the positive PWM signal is automatically applied to the U-phase and W-phase switching in the (C) section, as in the first divided section T1.

The inversion application section is further described with reference to fig. 10. Fig. 10 is a diagram showing an output voltage and an output current. Fig. 10 is a diagram showing a case where the rotation direction of the motor M is CCW rotation (counterclockwise rotation). That is, the rotation direction is a direction in which the electrical angle is from 360 degrees toward 0 degrees.

As shown in fig. 10, the phases of the output currents (output current Iu, output current Iv, and output current Iw) of the three phases are delayed by 40 degrees from the phases of the output voltages (output voltage Vu, output voltage Vv, and output voltage Vw) of the three phases.

The inverted PWM interval is applied to the first divided interval T1, the third divided interval T3, and the fifth divided interval T5. As described with reference to fig. 3, in the inverted PWM section, a phase in which a current zero-crossing occurs next in the time axis direction is selected as an inverted PWM phase. For example, in the first segment T1, positive PWM signals are used for V and W phases of the three phases, and negative PWM signals are used for U phases of the three phases. Therefore, as shown in fig. 10, even when the phase of the output current of the three phases is delayed by more than 30 degrees from the output voltage of the three phases, and a (C) section is generated in which the inverted PWM signal is preferably not applied, the U-phase to which the inverted PWM signal is applied before the (C) section is continuously turned off in the (C) section, and the positive PWM signal is automatically applied to the V-phase and the W-phase to be switched in the (C) section. Therefore, in the case where the current phase is delayed by more than 30 degrees and the case where it is not more than 30 degrees, there is no need to make a case distinction. Therefore, the control program can be simplified.

In the third division section T3, positive PWM signals are used for the U-phase and W-phase of the three phases, and inverted PWM signals are used for the V-phase of the three phases. Therefore, the positive PWM signal is automatically applied to the U-phase and W-phase switching in the (C) section, as in the first divided section T1.

In the fifth division section T5, positive PWM signals are used for the U-phase and V-phase of the three phases, and inverted PWM signals are used for the W-phase of the three phases. Therefore, the positive PWM signal is automatically applied to the U-phase and V-phase switching in the (C) section, as in the first divided section T1.

As described with reference to fig. 9 and 10, the inverter control device 12 can change the order of the phases of the three-phase output waveforms. Therefore, the degree of freedom of control can be improved. In the case of driving the motor, the rotation direction of the motor can be switched.

The signal generating unit 120 switches the phase to which the inverted PWM signal is applied in the inverted PWM section to the normal phase PWM signal at the current zero crossing. Therefore, the control program can be simplified.

The signal generating unit 120 determines, for each of the plurality of divided sections T, any one of a normal phase PWM section and an inverse phase PWM section in which the normal phase PWM signal is applied to all three phases. Therefore, the control program can be simplified.

The signal generating unit 120 divides the electrical angle 1 cycle into the divided sections T for each current zero-crossing. Therefore, the control program can be simplified.

The signal generating unit 120 divides the electrical angle 1 into a first divided section T1, a second divided section T2, a third divided section T3, a fourth divided section T4, a fifth divided section T5, and a sixth divided section T6. Therefore, the control program can be simplified.

In addition, the signal generating unit 120 applies the inverse PWM period to the first divided period T1, the third divided period T3, and the fifth divided period T5. In the second divided section T2, the fourth divided section T4, and the sixth divided section T6, the signal generating unit 120 applies the normal phase PWM section to all phases. Therefore, the off-fixed mode (Min type) can be controlled.

Next, another example of the operation of the signal generating unit 120 will be described with reference to fig. 11. Fig. 11 is a diagram showing an output voltage and an output current.

The upper diagram of fig. 11 shows the output voltage Vu, the output voltage Vv, and the output voltage Vw. In the upper diagram of fig. 11, the output voltage Vu is shown by a solid line, the output voltage Vv is shown by a broken line, and the output voltage Vw is shown by a chain line. The vertical axis of fig. 11 shows voltage values normalized by the input voltages V1 to V2, and the output voltages of the respective phases are in the range of 0 to 1. The value also represents a duty ratio, which is a ratio of the on time of the first semiconductor switching element of each phase to the PWM period. The horizontal axis of fig. 11 represents the electric rotation angle of the motor in degrees.

The lower graph of fig. 11 shows the output current Iu, the output current Iv, and the output current Iw. In the lower diagram of fig. 11, the output current Iu is shown by a solid line, the output current Iv is shown by a broken line, and the output current Iw is shown by a chain line. The horizontal axis of fig. 11 represents the electric rotation angle of the motor in degrees.

As shown in fig. 11, the output voltage waveform has a period in which one of three phases is on-fixed. The on-fixation means that the first semiconductor switching element is continuously on and the second semiconductor switching element is continuously off during a plurality of PWM periods. Specifically, the output voltage Vu is fixed on at an electrical angle of 30 degrees to 150 degrees. The output voltage Vv is set to be on-fixed at an electrical angle of 150 degrees to 270 degrees. The output voltage Vw is set to be on-fixed at an electrical angle of 0 to 30 degrees and an electrical angle of 270 to 360 degrees. In this specification, as shown in fig. 11, a modulation scheme in which an output voltage waveform has a period in which one of three phases is on-fixed may be referred to as an on-fixed mode (Max-type) modulation scheme.

In the present embodiment, the signal generating unit 120 applies the inverted PWM interval to the second divided section T2, the fourth divided section T4, and the sixth divided section T6. The normal phase PWM period is applied to the first divided period T1, the third divided period T3, and the fifth divided period T5. Therefore, the access fixed mode (Max type) can be controlled.

In the present embodiment, the signal generating unit 120 selects, as the inverted PWM phase, a phase in which a current zero-crossing occurs next as viewed in the time axis direction in the inverted PWM section. Specifically, in the second division section T2 which is the inverted PWM section, the V-phase in which the current zero-crossing occurs next as viewed in the time axis direction is selected as the inverted PWM phase. In a fourth divided section T4 which is an inverted PWM section, a W-phase in which a current zero-crossing occurs next in the time axis direction is selected as an inverted PWM phase. In a sixth divided section T6 which is an inverted PWM section, a U-phase in which a current zero-crossing occurs next in the time axis direction is selected as an inverted PWM phase.

In the on-fixed mode (Max type), it is also not necessary to perform case discrimination in the case where the current phase is delayed by more than 30 degrees and in the case where it is not delayed by more than 30 degrees. Therefore, the control program can be simplified.

Next, another example of the operation of the signal generating unit 120 will be described with reference to fig. 12. Fig. 12 is a diagram showing an output voltage and an output current.

The upper diagram of fig. 12 shows the output voltage Vu, the output voltage Vv, and the output voltage Vw. In the upper diagram of fig. 12, the output voltage Vu is shown by a solid line, the output voltage Vv is shown by a broken line, and the output voltage Vw is shown by a chain line. The vertical axis of fig. 12 shows the voltage values normalized by the input voltages V1 to V2, and the output voltages of the respective phases are in the range of 0 to 1. The value also represents a duty ratio, which is a ratio of the on time of the first semiconductor switching element of each phase to the PWM period. The horizontal axis of fig. 12 represents the electric rotation angle of the motor in degrees.

The lower graph of fig. 12 shows the output current Iu, the output current Iv, and the output current Iw. In the lower diagram of fig. 12, the output current Iu is shown by a solid line, the output current Iv is shown by a broken line, and the output current Iw is shown by a chain line. The horizontal axis of fig. 12 represents the electric rotation angle of the motor in degrees.

As shown in fig. 12, the output voltage waveform has a period in which one of the three phases becomes on-fixed and a period in which one of the three phases becomes off-fixed. Specifically, the output voltage Vu is on-fixed at an electrical angle of 80 degrees to 140 degrees. The output voltage Vu becomes off-fixed at an electrical angle of 260 degrees to 320 degrees. The output voltage Vv is set to be on-fixed at an electrical angle of 200 to 260 degrees. The output voltage Vv is fixed to be off at an electrical angle of 20 degrees to 80 degrees. The output voltage Vw is turned on and fixed at an electrical angle of 0 to 20 degrees and an electrical angle of 320 to 360 degrees. The output voltage Vw becomes off-fixed at an electrical angle of 140 degrees to 200 degrees. As shown in fig. 12, a modulation scheme in which the output voltage waveform has a period in which one of three phases is on-fixed and a period in which one of the three phases is off-fixed is sometimes referred to as an on-off fixed mode (Max-Min type) modulation scheme. The modulation scheme of the on-off fixed mode (Max-Min type) is a modulation scheme in which the on fixed mode (Max type) and the off fixed mode (Min type) are switched every 60 degree interval.

The charge/discharge current of the capacitor C will be described with reference to fig. 12 to 14C. Fig. 13A to 14C are diagrams for explaining charge/discharge current of the capacitor C.

As shown in fig. 12, the phases of the output currents (output current Iu, output current Iv, and output current Iw) of the three phases are delayed by 20 degrees from the phases of the output voltages (output voltage Vu, output voltage Vv, and output voltage Vw) of the three phases.

First, a case where inverse PWM is applied in the (a) section will be described. Fig. 13A to 13C are diagrams showing sections in which the electrical angle is 140 degrees to 200 degrees in the section (a).

As shown in fig. 13C, a positive PWM signal is input to the first semiconductor switching element Vp. An inverted PWM signal is input to the first semiconductor switching element Up. A low-level signal is input to the first semiconductor switching element Wp.

In the section (1) in fig. 13C, the Vp gate signal is at a high level as shown in fig. 13A. In addition, the Up gate signal and the Wp gate signal are low. Accordingly, the first semiconductor switching element Vp is turned on, and the first semiconductor switching element Up and the first semiconductor switching element Wp are turned off. On the other hand, the second semiconductor switching element Vn is turned off, and the second semiconductor switching element Un and the second semiconductor switching element Wn are turned on. Therefore, compared with the case of fig. 5A, the inverter current is dispersed, and the charge/discharge current of the capacitor C can be suppressed.

In the case of the modulation scheme of the on-off fixed mode (Max-Min type), the inverse PWM is applied not only in the (a) section but also in the (B) section.

Next, a case where inverse PWM is applied in the (B) section will be described. Fig. 14A to 14C are diagrams showing the intervals in which the electrical angle is 0 to 20 degrees and 320 to 360 degrees in the interval (B).

As shown in fig. 14C, a positive PWM signal is input to the first semiconductor switching element Vp. An inverted PWM signal is input to the first semiconductor switching element Up. A low-level signal is input to the first semiconductor switching element Wp.

In the section (1) in fig. 14C, as shown in fig. 14A, the Vp gate signal and the Wp gate signal are at high level. In addition, the Up gate signal is low. Accordingly, the first semiconductor switching element Vp and the first semiconductor switching element Wp are turned on, and the first semiconductor switching element Up is turned off. On the other hand, the second semiconductor switching element Vn and the second semiconductor switching element Wn are turned off, and the second semiconductor switching element Un is turned on. In this case, no reverse current flows to the capacitor C. Therefore, the charge/discharge current of the capacitor C can be suppressed.

In the section (2) in fig. 14C, as shown in fig. 14B, the Up gate signal and the Wp gate signal are at high level. In addition, the Vp gate signal is low. Accordingly, the first semiconductor switching element Up and the first semiconductor switching element Wp are turned on, and the first semiconductor switching element Vp is turned off. On the other hand, the second semiconductor switching element Un and the second semiconductor switching element Wn are turned off, and the second semiconductor switching element Vn is turned on. In this case, a reverse current flows into the capacitor C, and the charge/discharge current of the capacitor C increases. In this case, no reverse current flows to the capacitor C. Therefore, the charge/discharge current of the capacitor C can be suppressed.

The reverse phase application section will be described with reference to fig. 15. Fig. 15 is a diagram showing an output voltage and an output current. Fig. 15 is a diagram showing a case where the rotation direction of the motor M is CW rotation (clockwise rotation). That is, the rotation direction is a direction in which the electrical angle is from 0 degrees toward 360 degrees.

As shown in fig. 15, the phases of the output currents (output current Iu, output current Iv, and output current Iw) of the three phases are delayed by 40 degrees from the phases of the output voltages (output voltage Vu, output voltage Vv, and output voltage Vw) of the three phases.

The signal generating unit 120 applies the inverse PWM section to the first divided section T1, the second divided section T2, the third divided section T3, the fourth divided section T4, the fifth divided section T5, and the sixth divided section T6. Therefore, the on-off fixed mode (Min-Max type) can be controlled.

In the inverted PWM section, a phase in which a current zero-crossing is observed next in the time axis direction is selected as an inverted PWM phase. For example, in the first segment T1, positive PWM signals are used for V and U phases among the three phases, and negative PWM signals are used for W among the three phases. In the second division section T2, positive PWM signals are used for U and W phases among the three phases, and inverted PWM signals are used for V among the three phases. In the third division section T3, positive PWM signals are used for V and W phases in the three phases, and inverted PWM signals are used for U in the three phases. In the fourth segment T4, positive PWM signals are used for V and U phases among the three phases, and negative PWM signals are used for W among the three phases. In the fifth segment T5, positive PWM signals are used for U and W phases among the three phases, and negative PWM signals are used for V among the three phases. In the sixth segment T6, positive PWM signals are used for V and W phases of the three phases, and negative PWM signals are used for U phases of the three phases.

The inverter control device 12 has an on-fixed mode (Max type) and an off-fixed mode (Min type). The signal generating section 120 switches between an on-fixed mode (Max type) and an off-fixed mode (Min type) at each current zero crossing. Therefore, the control program can be simplified. In the present embodiment, a waveform of an on-fixed pattern (Max type) is applied to a segment T in which only one phase is positive. Specifically, in the present embodiment, waveforms in the on-fixed mode (Max type) are applied to the second division section T2, the fourth division section T4, and the sixth division section T6. On the other hand, in the divided section T where only one phase is negative current, a waveform of the off-fixed mode (Min type) is applied. Specifically, in the present embodiment, waveforms in the off-fixed pattern (Min type) are applied to the first segment T1, the third segment T3, and the fifth segment T5.

In the present embodiment, even when the phase of the three-phase output current is delayed by more than 30 degrees from the three-phase output voltage to generate the (C) section, the reverse current to the capacitor C can be suppressed. Therefore, in the case where the current phase is delayed by more than 30 degrees and the case where it is not more than 30 degrees, there is no need to make a case distinction. Therefore, the control program can be simplified.

The inversion application section is further described with reference to fig. 16. Fig. 16 is a diagram showing an output voltage and an output current. Fig. 16 is a diagram showing a case where the rotation direction of the motor M is CCW rotation (counterclockwise rotation). That is, the rotation direction is a direction in which the electrical angle is from 360 degrees toward 0 degrees.

As shown in fig. 16, the phases of the output currents (output current Iu, output current Iv, and output current Iw) of the three phases are delayed by 40 degrees from the phases of the output voltages (output voltage Vu, output voltage Vv, and output voltage Vw) of the three phases.

The signal generating unit 120 applies the inverse PWM section to the first divided section T1, the second divided section T2, the third divided section T3, the fourth divided section T4, the fifth divided section T5, and the sixth divided section T6.

In the inverted PWM section, a phase in which a current zero-crossing is observed next in the time axis direction is selected as an inverted PWM phase. For example, in the first segment T1, positive PWM signals are used for V and W phases of the three phases, and negative PWM signals are used for U phases of the three phases. In the second division section T2, positive PWM signals are used for the U-phase and V-phase of the three phases, and inverted PWM signals are used for the W-phase of the three phases. In the third division section T3, positive PWM signals are used for the U-phase and W-phase of the three phases, and inverted PWM signals are used for the V-phase of the three phases. In the fourth segment T4, positive PWM signals are used for V and W phases in the three phases, and negative PWM signals are used for U phases in the three phases. In the fifth division section T5, positive PWM signals are used for the U-phase and V-phase of the three phases, and inverted PWM signals are used for the W-phase of the three phases. In the sixth segment T6, positive PWM signals are used for U and W phases among the three phases, and negative PWM signals are used for V among the three phases.

The inverter control device 12 has an on-fixed mode (Max type) and an off-fixed mode (Min type). The signal generating unit 120 switches between an on-fixed mode (Max type) and an off-fixed mode (Min type) at each current zero crossing, and in the present embodiment, applies a waveform of the on-fixed mode (Max type) to the divided section T in which only one phase is a positive current. Specifically, in the present embodiment, waveforms in the on-fixed mode (Max type) are applied to the second division section T2, the fourth division section T4, and the sixth division section T6. On the other hand, in the divided section T where only one phase is negative current, a waveform of the off-fixed mode (Min type) is applied. Specifically, in the present embodiment, waveforms in the off-fixed pattern (Min type) are applied to the first segment T1, the third segment T3, and the fifth segment T5.

In the present embodiment, even when the phase of the three-phase output current is delayed by more than 30 degrees from the three-phase output voltage to generate the (C) section, the reverse current to the capacitor C can be suppressed. Therefore, in the case where the current phase is delayed by more than 30 degrees and the case where it is not more than 30 degrees, there is no need to make a case distinction. Therefore, the control program can be simplified.

The inversion application section is further described with reference to fig. 17. Fig. 17 is a diagram showing a section to which inverse PWM is applied and a phase to which an inverse PWM signal is applied in each divided section.

As shown in fig. 17, in the CW rotation in the off-fixed mode (Min type), an inverted PWM signal is applied to W in the first divided section T1. In the third segment T3, an inverted PWM signal is used for U. In the fifth segment T5, an inverted PWM signal is applied to V.

In the CCW rotation in the off-fixed mode (Min type), the inverted PWM signal is applied to U in the first segment T1. In the third segment T3, an inverted PWM signal is applied to V. In the fifth segment T5, an inverted PWM signal is used for W.

In the CW rotation in the on-fixed mode (Max type), an inverted PWM signal is applied to V in the second division period T2. In the fourth segment T4, an inverted PWM signal is used for W. In the sixth segment T6, the inverted PWM signal is applied to U.

In CCW rotation in the on fixed mode (Max type), an inverted PWM signal is applied to W in the second division period T2. In the fourth segment T4, an inverted PWM signal is used for U. In the sixth segment T6, an inverted PWM signal is applied to V.

In the CW rotation in the on-off fixed mode (Min-Max type), an inverted PWM signal is applied to W in the first division section T1. In the second division interval T2, an inverted PWM signal is used for V. In the third segment T3, an inverted PWM signal is used for U. In the fourth segment T4, an inverted PWM signal is used for W. In the fifth segment T5, an inverted PWM signal is applied to V. In the sixth segment T6, the inverted PWM signal is applied to U.

In CCW rotation using (Min-Max type), an inverted PWM signal is applied to U in the first segment T1. In the second division period T2, an inverted PWM signal is used for W. In the third segment T3, an inverted PWM signal is applied to V. In the fourth segment T4, an inverted PWM signal is used for U. In the fifth segment T5, an inverted PWM signal is used for W. In the sixth segment T6, an inverted PWM signal is applied to V.

As shown in fig. 17, the signal generating unit 120 applies the inverted PWM signal to different phases in accordance with the rotation direction for the same division section T in which the inverted PWM signal is applied. Therefore, control can be performed according to the rotation direction.

The inverter control method will be described with reference to fig. 18. Fig. 18 is a flowchart showing an inverter control method. The inverter control is performed by executing the processing of step S102 to step S118 shown in fig. 18. The inverter control method is a method of controlling a three-phase inverter of a two-phase modulation scheme.

Step S102: the signal generating unit 120 derives an instantaneous angle. Specifically, the position (electrical angle) of the developed rotor is derived. The process advances to step S104.

Step S104: the signal generating unit 120 derives an instantaneous value of each phase output. In detail, the sine wave output voltage of each phase is calculated from the instantaneous angle. The process advances to step S106.

Step S106: the signal generating unit 120 determines in which divided section T the instantaneous angle is included. The process advances to step S108.

Step S106: the signal generating unit 120 calculates a modulation offset in a variable form (Min type or Max type) corresponding to the divided section T. I.e. the duty cycle is derived.

Step S108: the signal generating unit 120 selects the inverse PWM application mode according to the divided section T and the rotation direction. Specifically, the signal generating unit 120 selects whether or not to apply the inverse PWM and the applied phase. More specifically, the signal generating unit 120 selects, as the inverted PWM phase, a phase that generates a current zero-crossing next in the time axis direction in the inverted PWM section. Step S108 corresponds to an example of the "selection step". The process advances to step S112.

Step S112: the signal generating section 120 determines whether or not a phase to which inversion is applied exists. When the signal generating unit 120 determines that there is no phase to which the inversion is applied (no in step S112), the process proceeds to step S116. When the signal generating unit 120 determines that the phase to which the inversion is applied exists (yes in step S112), the process proceeds to step S114.

Step S114: the signal generating unit 120 changes the duty ratio of the inverted PWM phase to 1 duty ratio. The process advances to step S116.

Step S116: the signal generation section 120 sets the duty value to the register. The process advances to step S118.

Step S118: the signal generating unit 120 sets the normal phase PWM and the reverse phase PWM. The process ends.

As described above, the inverter control method includes: and a selection step of selecting, as an inverted PWM phase, a phase in which a current zero-crossing occurs next as viewed in the time axis direction in the inverted PWM section. When the phase selected as the inverted PWM phase is on-fixed or off-fixed as in the section (C) of fig. 9, 10, 15, and 16, the duty value set to the register may be set to 1 or 0 in the state where the inverted PWM phase is set. Therefore, in the case where the current phase is delayed by more than 30 degrees and the case where it is not more than 30 degrees, there is no need to make a case distinction. Therefore, the control program can be simplified.

The embodiments of the present invention are described above with reference to the drawings (fig. 1 to 18). However, the present invention is not limited to the above-described embodiments, and may be implemented in various forms within a scope not departing from the gist thereof. For ease of understanding, the drawings schematically show the respective components, and the thickness, length, number, etc. of the components are different from the actual ones due to convenience in manufacturing the drawings. The materials, shapes, sizes, and the like of the respective constituent elements shown in the above-described embodiments are examples, and are not particularly limited, and various modifications can be made within a range substantially not departing from the effects of the present invention.

Industrial applicability

The present invention can be used in an inverter control device, an inverter circuit, a motor module, and an inverter control method.

Description of the reference numerals

12 inverter control device

100 motor driving circuit (inverter circuit)

110 inverter (three-phase inverter)

112. 112u, 112v, 112w concatemers

120 signal generating section

200 motor module

C capacitor

M motor

N second input terminal

P first input terminal

T-partition section

T1 first partition section

T2 second division section

T3 third partition section

T4 fourth partition section

T5 fifth partition section

T6 sixth partition section

V1 first voltage

V2 second voltage.

Claims (14)

1. An inverter control device for controlling a three-phase inverter of a two-phase modulation scheme, characterized in that,

the three-phase inverter includes:

a first input terminal to which a first voltage is applied;

a second input terminal to which a second voltage lower than the first voltage is applied;

a capacitor connected between the first input terminal and the second input terminal;

three serial bodies, which are connected with two semiconductor switching elements in series,

the inverter control device includes a signal generation unit that generates three PWM signals to be input to the three series bodies, respectively,

The PWM signal comprises at least an inverted PWM interval to which an inverted PWM signal is applied,

the inverted PWM signal is in an inverted phase relative to the positive phase PWM signal,

the inverted PWM interval is an interval in which the normal phase PWM signal is applied to two of three phases and the inverted PWM signal is applied to one of the three phases,

the signal generating unit selects, as an inverted PWM phase, a phase in which a current zero-crossing occurs next in the time axis direction in the inverted PWM section.

2. The inverter control device according to claim 1, wherein,

the order of the phases of the three-phase output waveforms can be changed.

3. The inverter control device according to claim 1 or 2, characterized in that,

the signal generation unit converts a phase switch to which the inverted PWM signal is applied in the inverted PWM section into the normal PWM signal at a current zero crossing.

4. The inverter control device according to any one of claims 1 to 3,

the signal generating unit divides the electrical angle into a plurality of divided sections,

the signal generating unit determines, for each of the plurality of divided sections, either a normal phase PWM section and an inverse phase PWM section, in which a normal phase PWM signal is applied to all three phases.

5. The inverter control apparatus according to claim 4, wherein,

the signal generating unit divides the electrical angle by one revolution into the divided sections at each current zero crossing.

6. The inverter control device according to claim 4 or 5, characterized in that,

the signal generating unit divides the electrical angle into a first divided section, a second divided section that is adjacent to the first divided section, a third divided section that is adjacent to the second divided section, a fourth divided section that is adjacent to the third divided section, a fifth divided section that is adjacent to the fourth divided section, and a sixth divided section that is adjacent to the fifth divided section.

7. The inverter control apparatus according to claim 6, wherein,

the signal generating section applies the inverted PWM interval in the first divided section, the third divided section, and the fifth divided section,

the signal generating unit applies the normal phase PWM period to all phases in the second divided period, the fourth divided period, and the sixth divided period.

8. The inverter control apparatus according to claim 6, wherein,

the signal generating unit applies the inverted PWM section to the second divided section, the fourth divided section, and the sixth divided section,

The normal phase PWM interval is applied to the first, third, and fifth divided intervals.

9. The inverter control apparatus according to claim 6, wherein,

the signal generating unit applies the inverted PWM section to the first divided section, the second divided section, the third divided section, the fourth divided section, the fifth divided section, and the sixth divided section.

10. The inverter control apparatus according to claim 9, wherein,

the inverter control device has an on-fixed mode and an off-fixed mode,

the signal generating section switches the on-fixed mode and the off-fixed mode at each current zero-crossing.

11. The inverter control device according to claim 1, wherein,

the signal generating unit applies the inverted PWM signal to the same divided section to which the inverted PWM signal is applied, and the inverted PWM signal is applied to different respective sections according to the rotation direction.

12. An inverter circuit is characterized by comprising:

the inverter control apparatus of any one of claims 1 to 11;

a first input terminal to which a first voltage is applied;

a second input terminal to which a second voltage lower than the first voltage is applied;

A capacitor connected between the first input terminal and the second input terminal;

three serial bodies, which are connected with two semiconductor switching elements in series.

13. An electric motor module, comprising:

the inverter control apparatus of any one of claims 1 to 11;

a three-phase inverter which is controlled by the inverter control device and is of a two-phase modulation scheme;

a three-phase motor to which an output of the inverter is input.

14. An inverter control method for controlling a three-phase inverter of a two-phase modulation scheme is characterized in that,

the three-phase inverter includes:

a first input terminal to which a first voltage is applied;

a second input terminal to which a second voltage lower than the first voltage is applied;

a capacitor connected between the first input terminal and the second input terminal;

three serial bodies, which are connected with two semiconductor switching elements in series,

three PWM signals are input to the three concatemers respectively,

the PWM signal comprises at least an inverted PWM interval to which an inverted PWM signal is applied,

the inverted PWM signal is in an inverted phase relative to the positive phase PWM signal,

the inverted PWM interval is an interval in which the normal phase PWM signal is applied to two of three phases and the inverted PWM signal is applied to one of the three phases,

The inverter control method includes: and a selection step of selecting, as an inverted PWM phase, a phase which generates a current zero-crossing next as viewed in the time axis direction in the inverted PWM section.