CN116980362A - Multitasking method and device for SPI architecture - Google Patents

Abstract

This application relates to the field of data transmission technology and discloses a multi-tasking method for SPI architecture. When receiving the data sending instruction sent by the external trigger source, determine the priority of the register storage corresponding to the sequence data to be sent; determine each register storage priority in order from high to low according to the priority of the register storage corresponding to the sequence data to be sent. The tasks to be sent in the sequence data to be sent; send each task to be sent to the corresponding chip select device. According to the data sending instruction from the external trigger source, the priority stored in the register corresponding to the sending sequence number is directly read, and data is sent based on the priority. Priority judgment and data sending are only performed through hardware, avoiding the need to rely on software for priority determination. The judgment caused the problem of frequent hardware interruption, which effectively reduced the load rate of the processor and improved the data transmission efficiency. This application also discloses a multi-tasking device for SPI architecture.

Description

Multitasking method and device for SPI architecture

Technical field

The present application relates to the field of data communication technology, for example, to a multi-tasking method and device for SPI architecture.

Background technique

The software architecture of automobile controllers is mostly developed based on the Automotive Open System Architecture (AUTOSAR). In the classic AUTOSAR architecture, the SPI (Serial Peripheral Interface) driver is abstracted into a sequence (Sequence) and a task ( The data structure of Job and Channel sets a series of SPI operations as a Sequence. A Sequence contains one or more Jobs, and a Job contains one or more Channels. For a Sequence, it can be set as an internal job to allow the insertion of a higher-priority Sequence job after execution is completed.

In related technologies, software is required to determine the priority of data to be transmitted, and then send sequence data with higher priority.

In the process of implementing the embodiments of this application, it was found that there are at least the following problems in the related technology:

Software priority judgment depends on hardware SPI interrupts. For scenarios with high real-time performance, frequent interrupts and software scheduling will increase the system operating burden, thus reducing the transmission efficiency of the data transmission system.

It should be noted that the information disclosed in the above background section is only used to enhance understanding of the background of the present application, and therefore may include information that does not constitute prior art known to those of ordinary skill in the art.

Contents of the invention

In order to provide a basic understanding of some aspects of the disclosed embodiments, a simplified summary is provided below. The summary is not intended to be a general review, nor is it intended to identify key/important elements or delineate the scope of the embodiments, but is intended to serve as a prelude to the detailed description that follows.

Embodiments of the present application provide a multi-tasking method and device for SPI architecture to improve data transmission efficiency.

In some embodiments, the method includes: upon receiving a data sending instruction sent by an external trigger source, determining the priority of register storage corresponding to the sequence data to be sent; according to the priority of register storage corresponding to the sequence data to be sent In order from high to low, determine the tasks to be sent in each sequence data to be sent; send each task to be sent to the corresponding chip select device.

Optionally, it also includes: when receiving newly added sequence data, comparing the priorities of the newly added sequence data and the current sequence data to obtain a priority comparison result; wherein the current sequence data is the sequence data sent at the current moment. ; Determine the tasks to be sent at the next moment based on the comparison results.

Optionally, determining the task to be sent at the next moment according to the comparison result includes: when the comparison result indicates that the priority of the newly added sequence data is higher than the priority of the current sequence data, determining that the task to be sent at the next moment is All tasks to be sent that are newly added to the sequence data; when the comparison result indicates that the priority of the current sequence data is higher than the priority of the newly added sequence data, it is determined that the tasks to be sent at the next moment are those that have not been sent in the current sequence data. of tasks to be sent.

Optionally, the method further includes: before comparing the priorities of the newly added sequence data and the current sequence data, determining whether the current sending task is completed; and after the current sending task is completed, comparing the priorities of the newly added sequence data and the current sequence data.

Optionally, it also includes determining the sequence data to be sent in the following manner: obtaining the address information contained in the data sending instruction; reading the data corresponding to the address information from the memory as the sequence data to be sent according to the address information contained in the data sending instruction. .

Optionally, the method further includes: receiving the data to be written sent by the chip selection device; and writing the data to be written into the memory according to the chip selection information of the data to be written.

In some embodiments, the device includes: a priority determination module configured to determine the priority of the register storage corresponding to the sequence data to be sent when receiving a data sending instruction sent by an external trigger source; the task to be sent The determination module is configured to determine the tasks to be sent in each sequence data to be sent in order from high to low according to the priority stored in the register corresponding to the sequence data to be sent; the sending module is configured to determine each task to be sent Sent to the corresponding chip select device.

In some embodiments, the device includes: a data transmission channel, a data processing unit and a sequence data interface unit, wherein: the data transmission channel is connected to the data processing unit and is configured to receive a data sending instruction sent by an external trigger source. In the case of , send the sequence data to be sent to the data processing unit; the data processing unit, connected to the sequence data interface unit, is configured to: receive the sequence data to be sent, and determine the priority of register storage corresponding to the sequence data to be sent; according to The priority of the register storage corresponding to the sequence data to be sent is determined from high to low to determine the task to be sent in each sequence data to be sent; the sequence data interface unit is connected to multiple chip select devices and is configured to receive the sequence data to be sent. Task, send the task to be sent to the corresponding chip select device.

In some embodiments, the controller includes: a controller body; the above-mentioned multi-tasking device for SPI architecture is installed on the controller body.

The multi-tasking method and device for SPI architecture provided by the embodiments of this application can achieve the following technical effects:

The embodiment of the present application directly reads the priority stored in the register corresponding to the sending sequence number according to the data sending instruction from the external trigger source, and performs data sending based on the priority. Priority judgment and data sending are only performed through hardware, avoiding the need to rely on software. The problem of frequent hardware interrupts caused by priority judgment effectively reduces the load rate of the processor and improves data transmission efficiency.

The above general description and the following description are exemplary and explanatory only and are not intended to limit the application.

Description of the drawings

One or more embodiments are exemplified by corresponding drawings. These exemplary descriptions and drawings do not constitute limitations to the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings are not limited to scale and in which:

Figure 1 is a schematic diagram of the transmission tasks in the AUTOSAR architecture;

Figure 2 is a flow chart of a method for serial data transmission through software in related technologies;

Figure 3 is a flow chart of a multi-tasking method for SPI architecture provided by an embodiment of the present application;

Figure 4 is a schematic structural diagram of a multi-tasking device for SPI architecture provided by an embodiment of the present application;

Figure 5 is a schematic structural diagram of another multi-tasking device for SPI architecture provided by an embodiment of the present application;

Figure 6 is a schematic diagram of a multi-tasking device for SPI architecture in an actual application scenario provided by an embodiment of the present application;

Figure 7 is a schematic diagram of a multi-tasking device for SPI architecture provided by an embodiment of the present application;

Figure 8 is a schematic diagram of another multi-tasking device for SPI architecture provided by an embodiment of the present application;

Figure 9 is a schematic diagram of a controller provided by an embodiment of the present application.

Detailed ways

In order to understand the characteristics and technical content of the embodiments of the present application in more detail, the implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings. The attached drawings are for reference only and are not intended to limit the embodiments of the present application. In the following technical description, for convenience of explanation, multiple details are provided to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown simplified to simplify the drawings.

The terms "first", "second", etc. in the description and claims of the embodiments of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that data so used may be interchanged where appropriate for the purposes of the embodiments of the application described herein. Furthermore, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

Unless otherwise stated, the term "plurality" means two or more.

In the embodiment of the present application, the character "/" indicates that the preceding and following objects are in an "or" relationship. For example, A/B means: A or B.

The term "and/or" is an association relationship describing objects, indicating that three relationships can exist. For example, A and/or B means: A or B, or A and B.

Serial Peripheral Interface (SPI) is widely used in automotive controllers, such as control power supply chips, transceiver chips, high- and low-side driver chips, etc. Therefore, SPI is commonly implemented in mainstream automotive microcontroller chips. controller. The SPI controller mainly implements the SPI protocol, that is, the serial-to-parallel conversion of data, sending and receiving. When sending, software or DMA writes the data into the sending shift register. The data is serially output to the data bus. When receiving, the data bus is The serial data on the CPU is converted into data with a specified bit width and stored in the receive data register, and the corresponding data is read by software or DMA.

The software architecture of automotive controllers is mostly developed based on Automotive Open System Architecture (AUTOSAR). As shown in Figure 1, it is a schematic diagram of the transmission tasks in the AUTOSAR architecture. In the AUTOSAR architecture, the SPI driver is abstracted into the data structures of Sequence, Job and Channel, and a series of SPI operations are set as a Sequence. A Sequence contains one or more Jobs, and a Job contains one or more Channels. For a Sequence, it can be set as an internal job to allow the insertion of a higher-priority Sequence job after execution is completed. As shown in Figure 2, it is a schematic flow chart of processing sending tasks of different priorities through software in related technologies. When the existing SPI controller architecture handles sending tasks of different priorities, it needs to be judged by software after the end of each job. The priority of the current transmission task, the Job in the Sequence with the highest priority will be sent. Determining the current task priority through software relies on hardware SPI interrupts. However, in high-real-time scenarios such as chassis, the number of hardware interrupts is strictly limited, and frequent software scheduling of SPI tasks will increase the system operating load.

Based on this, the embodiment of this application proposes a serial data transmission method and controller architecture that supports hardware transmission task priority scheduling. On the basis of supporting the general SPI protocol, through the Job priority processing module of AUTOSAR, each After the job transfer is completed, the job of the sequence with the highest priority among the tasks currently to be transferred will be automatically transferred. Supporting hardware triggering, the serial data transmission controller (ie SPI controller) can automatically transfer the Sequence stored in the memory to the shift register. In order to realize periodic SPI task scheduling, it can also reduce the system load caused by software scheduling and improve system operating efficiency.

As shown in Figure 3, the embodiment of the present application provides a multi-tasking method for SPI architecture. This method is applied to the multi-tasking controller of the SPI architecture. The schematic diagram of the serial data transmission controller is shown in Figure 4. , one end of the serial data transmission controller is connected to the memory, and the other end is connected to multiple chip select devices. During the data sending phase, the serial data transmission controller reads the data to be sent at the specified location in the memory, and after processing, determines the Send the sequence and send it to the corresponding chip select device. In the data receiving phase, the serial data transmission controller receives the data to be written sent by the chip select device and writes the data to be written into the memory. As shown in Figure 3, the method specifically includes:

S301: Upon receiving a data sending instruction sent by an external trigger source, determine the priority of register storage corresponding to the sequence data to be sent.

Among them, the external trigger source is a trigger source that triggers related processing instructions through hardware, such as a timer. The serial data transmission controller can receive a data transmission instruction when the set time of each timer arrives, thereby triggering the transmission and/or reception of serial data.

S302: Determine the tasks to be sent in each sequence data to be sent in order of priority stored in the register corresponding to the sequence data to be sent.

The priority of the sequence data Sequence is stored in the register. Specifically, the priority of each Sequence can be identified by three-digit binary numbers. These three-digit binary numbers represent the priorities of 0-6. The number 0 corresponds to the lowest priority. The number 6 corresponds to the highest priority. Of course, the priority can also be set in other ways according to user needs. The embodiments of this application do not limit the specific form of the priority.

S303: Send each task to be sent to the corresponding chip select device.

Each Sequence includes one or more Jobs, and each Job is stored in the buffer. As an example, the data structure corresponding to each Job occupies 32 bits, of which 16 bits are the data itself, and the other 16 bits are configuration information. The configuration information includes the timing format of the currently sent Job data, including the corresponding chip select signal and sampling edge. , data bit width, data endianness, etc.

Specifically, each sequence data (Sequence) includes one or more tasks (Jobs) to be sent, and the priority of all Jobs is the same as the priority of the Sequence to which the Job belongs, that is, the priority of all Jobs in the same Sequence. are all the same, therefore, after determining the Sequence with the highest priority, all jobs in the Sequence are sent in sequence.

The above method provided by the embodiment of the present application directly reads the priority stored in the register corresponding to the transmission sequence number according to the data transmission instruction of the external trigger source, and performs data transmission based on the priority, and only performs priority judgment and data transmission through hardware. , avoiding the problem of frequent hardware interrupts caused by relying on software to determine priorities, effectively reducing the load rate of the processor and improving data transmission efficiency.

Optionally, before determining the priority of register storage corresponding to the sequence data to be sent, it also includes: according to the address information contained in the data sending instruction, reading the data corresponding to the address information from the memory as the data to be sent.

Optionally, the above method also includes: when receiving newly added sequence data, comparing the priorities of the newly added sequence data and the current sequence data to obtain a priority comparison result; wherein the current sequence data is sent at the current moment. Sequence data; determine the tasks to be sent at the next moment based on the comparison results.

Specifically, within a cycle, new sequence data will also be received. For example, the external trigger source is a timer that triggers every 5ms. When 5ms arrives, the existing sequence data are S1, S2, and S3, where, S3 has the highest priority, S1 has the second priority, and S2 has the lowest priority. After comparing the priorities of S1, S2, and S3, it is determined that the order of sending sequence data is from high to low priority, that is, S3, S1, and S2. First send all the jobs in S3 in sequence, then send all the jobs in S1, and finally send all the jobs in S2. However, during the process of sending the Job, new Sequence data S4 is received. Since each Job cannot be interrupted during the sending process, after the current Job is sent, the priority of the new S4 and the currently sent Sequence is judged. , and based on the comparison result, re-determine which Sequence job the next sent Job is. In this way, it can be ensured that the tasks to be processed at every moment are the tasks with the highest priority, ensuring the accuracy of data transmission.

Optionally, the method further includes: before comparing the priorities of the newly added sequence data and the current sequence data, determining whether the current sending task is completed; and after the current sending task is completed, comparing the priorities of the newly added sequence data and the current sequence data.

Specifically, since the currently sending Job cannot be interrupted, priority comparison can only be performed after the current Job is sent. The sending time of the current Job can be determined based on the data length. In this way, the priority can be re-judged without interrupting the job being sent, avoiding data transmission errors caused by job interruption and improving the accuracy of data transmission.

Optionally, determining the task to be sent at the next moment according to the comparison result includes: when the comparison result indicates that the priority of the newly added sequence data is higher than the priority of the current sequence data, determining that the task to be sent at the next moment is All tasks to be sent will be newly added to the sequence data. When the comparison result indicates that the priority of the current sequence data is higher than the priority of the newly added sequence data, it is determined that the task to be sent at the next moment is the task to be sent that has not been sent in the current sequence data.

Continuing from the previous example, the Sequence to which the currently sent Job belongs is S2. After the current Job is sent, the priorities of the newly added S4 and S2 are compared. If the comparison result shows that the newly added S4 has a higher priority than S2, then no Instead of continuing to send the remaining jobs in S2, all the jobs in S4 are sent. After all the jobs in S4 are sent, the remaining jobs in S2 are sent.

If the comparison result shows that the priority of S2 is higher than the priority of the newly added S4, then continue to send the remaining jobs in S2.

In this way, it can be ensured that the currently transmitted data is always the data with the highest priority, further improving the accuracy of data transmission.

It should be noted that within a timing period, after all Sequences are sent, the data transmission task within the timing period is completed.

Optionally, it also includes determining the sequence data to be sent in the following manner: obtaining the address information contained in the data sending instruction; reading the data corresponding to the address information from the memory as the sequence data to be sent according to the address information contained in the data sending instruction. .

During the actual working process, software or DMA can write the sending data into the memory, read the data from the memory through the data sending channel and save it in the sending buffer queue. The data bit width of TxFIFO is 32 bits. In order to support AUTOSAR application scenarios, the upper 16 bits of TxFIFO data are set as control bits. Control the timing format of the currently sent data, including the corresponding chip select signal, sampling edge, data bit width, data endianness, whether to disable after the transmission is completed, etc. The other 16 bits store the data itself. It also supports Job mode. In this mode, the software can configure the transmission data length of the current Job, and the hardware can configure an interrupt trigger after judging that the Job transmission is completed.

Optionally, the method further includes: receiving the data to be written sent by the chip selection device; and writing the data to be written into the memory according to the chip selection information of the data to be written.

When working specifically, combined with the Job mode of the SPI controller, the user stores the data to be sent into the system RAM through software (such as APP), and configures an external trigger source, such as configuring a timer with a 5ms period trigger, and each timer An SPI Sequence transmission will be triggered. The transmission channel corresponding to the data transmission channel 601 will load the data in RAM into the sequence transmission buffer according to the configured address. The priority processing module 6023 determines the priority of all currently cached Sequences and determines If the Sequence with the highest priority is selected, all jobs in the Sequence will be sent. For example, set the external trigger source to a timer with a period of 5ms. After reaching 5ms, read the data corresponding to the configured address to the sequence sending buffer, that is, read the four Sequences of S1, S2, S3, and S4. After judging the current four The highest priority among the Sequences is S2, then the jobs in S2 are sent in sequence. After each job transmission is completed, it will automatically detect whether the currently sent Sequence in the sequence sending buffer has the highest priority. If not, the Job of the highest priority Sequence will be sent. If the current Sequence is the highest priority, continue to send the Sequence. The remaining jobs in the Sequence. If all Sequence transmissions are completed, it returns to the Idle state. In the same way, the sequence receiving buffer will select the receiving channel in the data transmission channel 601 according to the chip select information corresponding to the current transmission data, and store the data into the system RAM at the corresponding address. The entire data transmission process does not require the intervention of software to realize the cycle. SPI Sequence triggering and task scheduling. Both the receiving sequence and the sending sequence support not being triggered by software, but are triggered periodically by timers and do not rely on hardware interrupts, thus effectively reducing the CPU load rate.

As shown in FIG. 5 , a multi-tasking device 500 for SPI architecture provided by an embodiment of the present application includes a data transmission channel 501, a data processing unit 502 and a sequence data interface unit 503, wherein:

The data transmission channel 501 is connected to the data processing unit 502 and is configured to send sequence data to be sent to the data processing unit 502 when receiving a data sending instruction sent by an external trigger source;

The data processing unit 502 is connected to the sequence data interface unit 503 and is configured as:

Receive the sequence data to be sent and determine the priority of register storage corresponding to the sequence data to be sent;

Determine the tasks to be sent in each sequence data to be sent according to the priority stored in the register corresponding to the sequence data to be sent;

The sequence data interface unit 503 is connected to multiple chip select devices and is configured to receive tasks to be sent and send the tasks to be sent to the corresponding chip select devices.

The above-mentioned multi-tasking device for SPI architecture provided by the embodiment of the present application directly reads the priority stored in the register corresponding to the transmission sequence number according to the data transmission instruction of the external trigger source, and performs data transmission based on the priority, only through The hardware performs priority judgment and data transmission, avoiding the problem of frequent hardware interruption caused by relying on software for priority judgment, effectively reducing the load rate of the processor and improving data transmission efficiency.

As shown in FIG. 6 , an embodiment of the present application provides a multi-tasking device 600 for SPI architecture in a practical application scenario. The right half of Figure 6 implements the data serial-to-parallel conversion function required by the general SPI protocol. In main mode, it supports 8 chip select devices, and each chip select can independently set the data communication format.

The multi-tasking device 600 for SPI architecture in Figure 6 includes a data transmission channel 601, a data processing unit 602 and a sequence data interface unit 603. The secondary modules included in each module and the functions of each module are described in the following table 1 shown.

Table 1

Optionally, the data transmission channel 601 includes a data sending channel; the above-mentioned reading from the memory and sending the sequence data to be sent includes: the data sending channel reads the address information corresponding to the address information from the memory according to the address information contained in the data sending instruction. The data is used as the data to be sent; the data sending channel sends the data to be sent to the data processing unit.

During the actual working process, software or DMA can write the sending data into the memory, read the data from the memory through the data sending channel and save it in the sending buffer queue. The data bit width of TxFIFO is 32 bits. In order to support AUTOSAR application scenarios, the upper 16 bits of TxFIFO data are set as control bits. Control the timing format of the currently sent data, including the corresponding chip select signal, sampling edge, data bit width, data endianness, whether to disable after the transmission is completed, etc. The other 16 bits store the data itself. It also supports Job mode. In this mode, the software can configure the transmission data length of the current Job, and the hardware can configure an interrupt trigger after judging that the Job transmission is completed.

Optionally, the data processing unit 602 includes:

The trigger control logic module 6021 is configured to respond to the trigger condition and issue data transmission instructions to the data transmission channel;

The sequence sending buffer 6022 is configured to receive the sequence data to be sent sent by the data transmission channel;

The priority processing module 6023 is configured to determine the sequence data to be sent with the highest priority in the sequence sending buffer, and send the tasks to be sent in the sequence data to be sent with the highest priority to the task processing module in sequence;

The task processing module 6024 is configured to send the received task to be sent to the sequence data interface unit.

Optionally, the priority processing module 6023 is further configured to: in response to receiving newly added sequence data newly entered into the sequence sending buffer, compare the priorities of the newly added sequence data and the current sequence data to obtain a comparison result; where, currently The sequence data is the sequence data sent at the current moment; the task to be sent at the next moment is sent to the task processing module according to the comparison result.

Optionally, in response to receiving newly added sequence data that newly enters the sequence sending buffer, comparing the priorities of the newly added sequence data and the current sequence data, and obtaining a comparison result, including: comparing the newly added sequence data with the current sequence data. Before setting the priority, determine whether the current sending task is completed; after the current sending task is completed, compare the priority of the newly added sequence data and the current sequence data.

Optionally, sending the task to be sent at the next moment to the task processing module according to the comparison result, including: when the comparison result indicates that the priority of the newly added sequence data is higher than the priority of the current sequence data, sending the task to the task processing module in turn Send all pending tasks newly added to the sequence data. When the comparison result indicates that the priority of the current sequence data is higher than the priority of the newly added sequence data, the unsent to-be-sent tasks in the current sequence data are continued to be sent.

Optionally, the sequence data interface unit 603 includes: a sending buffer configured to receive and store tasks to be sent;

The sending buffer includes: a data content storage area, configured to store the data content of the task to be sent; a configuration information storage area, configured to store the chip select signal, sampling edge, data bit width, and data endian of the task to be sent.

Optionally, the sequence data interface unit also includes: a receiving buffer configured to receive data to be written from the chip select device and send it to the data processing unit; the data processing unit also includes: a sequence data receiving buffer configured to According to the chip select information of the data to be written, the data to be written is written into the memory through the data receiving channel in the data transmission channel.

When working specifically, combined with the Job mode of the SPI controller, the user stores the data to be sent into the system RAM through software (such as APP), and configures an external trigger source, such as configuring a timer with a 5ms period trigger, and each timer An SPI Sequence transmission will be triggered. The transmission channel corresponding to the data transmission channel 601 will load the data in RAM into the sequence transmission buffer according to the configured address. The priority processing module 6023 determines the priority of all currently cached Sequences and determines If the Sequence with the highest priority is selected, all jobs in the Sequence will be sent. For example, set the external trigger source to a timer with a period of 5ms. After reaching 5ms, read the data corresponding to the configured address to the sequence sending buffer, that is, read the four Sequences of S1, S2, S3, and S4. After judging the current four The highest priority among the Sequences is S2, then the jobs in S2 are sent in sequence. After each job transmission is completed, it will automatically detect whether the currently sent Sequence in the sequence sending buffer has the highest priority. If not, the Job of the highest priority Sequence will be sent. If the current Sequence is the highest priority, continue to send the Sequence. The remaining jobs in the Sequence. If all Sequence transmissions are completed, it returns to the Idle state. In the same way, the sequence receiving buffer will select the receiving channel in the data transmission channel 601 according to the chip select information corresponding to the current transmission data, and store the data into the system RAM at the corresponding address. The entire data transmission process does not require the intervention of software to realize the cycle. SPI Sequence triggering and task scheduling. Both the receiving sequence and the sending sequence support not being triggered by software, but are triggered periodically by timers and do not rely on hardware interrupts, thus effectively reducing the CPU load rate.

As shown in FIG. 7 , a multi-tasking device 700 for SPI architecture provided by an embodiment of the present application includes:

The priority determination module 701 is configured to determine the priority of register storage corresponding to the sequence data to be sent when receiving a data sending instruction sent by an external trigger source;

The task to be sent determination module 702 is configured to determine the tasks to be sent in each sequence data to be sent in order of the priority stored in the register corresponding to the sequence data to be sent;

The sending module 703 is configured to send each task to be sent to the corresponding chip select device.

The above-mentioned device provided by the embodiment of the present application directly reads the priority stored in the register corresponding to the transmission sequence number according to the data transmission instruction of the external trigger source, and performs data transmission based on the priority, and only performs priority judgment and data transmission through hardware. , avoiding the problem of frequent hardware interrupts caused by relying on software to determine priorities, effectively reducing the load rate of the processor and improving data transmission efficiency.

As shown in FIG. 8 , an embodiment of the present application provides a multi-tasking device 800 for SPI architecture, including a processor (processor) 100 and a memory (memory) 101 . Optionally, the device may also include a communication interface (Communication Interface) 102 and a bus 103. Among them, the processor 100, the communication interface 102, and the memory 101 can communicate with each other through the bus 103. Communication interface 102 may be used for information transmission. The processor 100 can call logical instructions in the memory 101 to execute the multi-tasking method for the SPI architecture of the above embodiment.

In addition, the above-mentioned logical instructions in the memory 101 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

As a computer-readable storage medium, the memory 101 can be used to store software programs and computer-executable programs, such as program instructions/modules corresponding to the methods in the embodiments of the present application. The processor 100 executes program instructions/modules stored in the memory 101 to execute functional applications and data processing, that is, to implement the multi-tasking method for the SPI architecture of the above embodiment.

The memory 101 may include a stored program area and a stored data area, wherein the stored program area may store an operating system and at least one application program required for a function; the stored data area may store data created according to the use of the terminal device, etc. In addition, the memory 101 may include a high-speed random access memory and may also include a non-volatile memory.

As shown in FIG. 9 , an embodiment of the present application provides a controller 900 , including: a controller body, and the above-mentioned multi-tasking process 700 (800) for SPI architecture. The multitasking device 700 (800) for SPI architecture is installed on the controller body. The installation relationship described here is not limited to placement inside the controller, but also includes installation connections with other components of the controller, including but not limited to physical connections, electrical connections, or signal transmission connections. Those skilled in the art can understand that the multitasking device 700 (800) for the SPI architecture can be adapted to a feasible controller body, thereby realizing other feasible embodiments.

Embodiments of the present application provide a computer-readable storage medium that stores computer-executable instructions. The computer-executable instructions are configured to execute the multi-tasking method for the SPI architecture of the above embodiments.

Embodiments of the present application provide a computer program product. The computer program product includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer, the The computer executes the multi-tasking method for the SPI architecture of the above embodiment.

The above-mentioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

The technical solution of the embodiment of the present application can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes one or more instructions to enable a computer device (which can be a personal computer, a server, or a network equipment, etc.) to perform all or part of the steps of the method described in the embodiments of this application. The aforementioned storage media can be non-transitory storage media, including: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk, etc. A medium that can store program code or a temporary storage medium.

The foregoing description and drawings illustrate embodiments of the application sufficiently to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples represent only possible variations. Unless explicitly required, individual components and features are optional and the order of operations may vary. Portions and features of some embodiments may be included in or substituted for those of other embodiments. Furthermore, the words used in this application are used only to describe the embodiments and not to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. . Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed items. In addition, when used in this application, the term "comprise" and its variations "comprises" and/or "comprising" etc. refer to stated features, integers, steps, operations, elements, and/or The presence of a component does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groupings of these. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method or apparatus including the stated element. In this article, each embodiment may focus on its differences from other embodiments, and the same and similar parts among various embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiment, then the relevant parts can be referred to the description of the method part.

Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The skilled person may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present application. The skilled person can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be described again here.

In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units may only be a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined. Either it can be integrated into another system, or some features can be ignored, or not implemented. In addition, the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present application can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.

The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operations of possible implementations of systems, methods, and computer program products according to embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code that contains one or more components for implementing the specified logical function(s). Executable instructions. In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two consecutive blocks may actually execute substantially in parallel, or they may sometimes execute in the reverse order, depending on the functionality involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, operations or steps corresponding to different blocks may also occur in a sequence different from that disclosed in the description, and sometimes there is no specific distinction between different operations or steps. order. For example, two consecutive operations or steps may actually be performed substantially in parallel, or they may sometimes be performed in reverse order, depending on the functionality involved. Each block in the block diagram and/or flowchart illustration, and combinations of blocks in the block diagram and/or flowchart illustration, may be implemented by special purpose hardware-based systems that perform the specified functions or actions, or may be implemented using special purpose hardware implemented in combination with computer instructions.

Claims (10)

1. A multi-tasking method for SPI architecture, characterized by including: Upon receiving a data sending instruction from an external trigger source, determine the priority of register storage corresponding to the sequence data to be sent; Determine the tasks to be sent in each sequence data to be sent according to the priority stored in the register corresponding to the sequence data to be sent; Send each to-be-sent task to the corresponding chip select device. 2. The method of claim 1, further comprising: When receiving newly added sequence data, compare the priorities of the newly added sequence data and the current sequence data to obtain the priority comparison result; where the current sequence data is the sequence data sent at the current moment; Determine the tasks to be sent at the next moment based on the comparison results. 3. The method according to claim 2, characterized in that determining the task to be sent at the next moment according to the comparison result includes: When the comparison result indicates that the priority of the newly added sequence data is higher than the priority of the current sequence data, it is determined that the tasks to be sent at the next moment are all the tasks to be sent that will be newly added to the sequence data; When the comparison result indicates that the priority of the current sequence data is higher than the priority of the newly added sequence data, it is determined that the task to be sent at the next moment is the task to be sent that has not been sent in the current sequence data. 4. The method of claim 2, further comprising: Before comparing the priorities of the newly added sequence data and the current sequence data, determine whether the current sending task is completed; After the current sending task is completed, the priorities of the newly added sequence data and the current sequence data are compared. 5. The method according to claim 1, further comprising determining the sequence data to be sent in the following manner: Obtain the address information contained in the data sending command; According to the address information contained in the data sending instruction, the data corresponding to the address information is read from the memory as the sequence data to be sent. 6. The method according to any one of claims 1 to 5, further comprising: Receive data to be written sent by the chip select device; According to the chip select information of the data to be written, the data to be written is written into the memory. 7. A multi-tasking device for SPI architecture, characterized by comprising: The priority determination module is configured to determine the priority of register storage corresponding to the sequence data to be sent when receiving a data sending instruction sent by an external trigger source; The to-be-sent task determination module is configured to determine the to-be-sent tasks in each to-be-sent sequence data according to the priority stored in the register corresponding to the to-be-sent sequence data; The sending module is configured to send each to-be-sent task to the corresponding chip select device. 8. A multi-tasking device for SPI architecture, characterized by including a data transmission channel, a data processing unit and a sequence data interface unit, wherein: The data transmission channel is connected to the data processing unit and is configured to send sequence data to be sent to the data processing unit upon receiving a data sending instruction sent by an external trigger source; The data processing unit, connected to the sequence data interface unit, is configured as: Receive the sequence data to be sent and determine the priority of register storage corresponding to the sequence data to be sent; Determine the tasks to be sent in each sequence data to be sent according to the priority stored in the register corresponding to the sequence data to be sent; The sequence data interface unit is connected to multiple chip select devices and is configured to receive tasks to be sent and send the tasks to be sent to the corresponding chip select devices. 9. The device according to claim 8, characterized in that the data processing unit includes: The trigger control logic module is configured to respond to trigger conditions and issue data transmission instructions to the data transmission channel; The sequence sending buffer is configured to receive the to-be-sent sequence data sent by the data transmission channel; The priority processing module is configured to determine the sequence data to be sent with the highest priority in the sequence sending buffer, and send the tasks to be sent in the sequence data to be sent with the highest priority to the task processing module in sequence; The task processing module is configured to send the received task to be sent to the sequence data interface unit. 10. The device according to claim 8, wherein the sequence data interface unit includes: Send buffer, configured to receive and store tasks to be sent; The send buffer includes: The data content storage area is configured to store the data content of the task to be sent; The configuration information storage area is configured to store the chip select signal, sampling edge, data bit width, and data endian of the task to be sent.