CN116963417A - A digital isolator ceramic packaging structure - Google Patents

Abstract

The invention discloses a digital isolator ceramic packaging structure, which includes: a ceramic tube shell; an insulating adhesive ceramic tube is provided with a first surface cavity and a second surface cavity on opposite sides of the ceramic tube shell; an insulating adhesive ceramic tube The shell is also provided with a number of bonding fingers for wire bonding; the first interface isolation circuit, the insulating adhesive sheet glue, the first interface isolation circuit is arranged in the cavity of the first surface of the insulating adhesive sheet glue; the second interface isolation circuit, the insulating adhesive sheet glue The second interface isolation circuit of the sheet adhesive is set in the cavity of the second side of the insulating sheet adhesive; among them, the cavity of the first side of the insulating sheet adhesive is sealed by a parallel sealing and welding process, and the cavity of the second side of the insulating sheet adhesive is made of gold-tin alloy It is sealed by a melting sealing process; the first and second side cavities of the insulating adhesive sheet are also filled with pressure-resistant organic silica gel; the present invention aims to reduce the size of the packaging structure while meeting the high reliability of scene applications.

Description

A digital isolator ceramic packaging structure

Technical field

The present invention relates to the technical field of isolator packaging, and specifically to a digital isolator ceramic packaging structure.

Background technique

Traditional photoelectric isolators and inductive sensors can no longer meet existing and future application needs in terms of speed and anti-interference. Due to its inherent characteristics, the device is slow, has high power consumption, and is larger than a digital isolator. At the same time, it requires peripheral components to assist and stabilize its function, and its application scope will gradually shrink in the future. The current major manufacturers include Broadcom, Vishay, Toshiba, Panasonic, etc. Digital isolators far exceed traditional devices in terms of performance, integration, reliability, and robustness, especially in suppressing common-mode transient interference, high speed, and low power consumption requirements, and are gradually replacing traditional optoelectronic isolators. As the equipment of maintenance and repair stations becomes more and more digital and intelligent, the control system requires more and greater power system control and information feedback. The demand and requirements for isolators in maintenance are also getting higher and higher, especially in terms of reliability, digital isolators It is more reliable than traditional devices, and its size, power consumption and speed are far greater than that of optocoupler isolators. With the further development of technology in the future, digital isolators will replace traditional optocoupler devices in most applications, providing digital isolation in high-speed fields. The demand for equipment will also become more urgent.

Currently, for example, Analog Devices' isolated control area network (CAN) physical layer transceiver ADM3053 (20pin) and 5Kv rms isolated RS-485/RS-422 transceiver ADM2682E (16pin) are packaged in plastic wide body SOIC. The appearance is shown in Figure 1. From the perspective of packaging materials, in order to meet the high isolation withstand voltage requirements, ADI's products use epoxy resin encapsulation materials to achieve high insulation withstand voltage indicators; from the appearance and size diagrams, integrated CAN interface digital isolators and integrated 485 interfaces The overall dimensions of digital isolators are 12.80mm*10.30mm*2.7mm.

The disadvantages of the above solution are:

1. Plastic packaging has low reliability and does not meet the requirements of high-reliability scenario applications.

Plastic packaging materials are generally based on thermosetting materials, usually including epoxy, butyric acid, polyurethane and organic silica, among which epoxy resin is the most widely used. Plastic packaging materials are the most widely used in the electronic packaging industry due to their low cost and mature and simple manufacturing process. Plastic packaging materials have obvious advantages, but also obvious disadvantages. Most plastic materials are not dense enough, have poor thermal conductivity, have a mismatch in thermal expansion coefficient with the chip (Si), have high dielectric loss and are brittle. During the reflow soldering process, because plastic packaging materials are sensitive to humidity, the absorbed water will easily expand when heated, causing the plastic packaging devices to burst and be damaged. In particular, epoxy materials are most obviously affected by water vapor, which seriously affects the reliability of the packaging. For Industries with higher packaging reliability requirements, such as military industry and aerospace, cannot meet their industry product needs.

2. The appearance is large and does not meet the requirements of miniaturized scenario applications.

Nowadays, mainstream digital isolators adopt the plastic wide-body SOI C or SOP package form, with larger overall dimensions. For example, ADI's CAN interface and 485 interface digital isolators are both 12.80mm*10.30mm. The CAN interface and 485/422 interface require In the application scenarios where the selection is enabled, the total board area needs to be more than 26.6mm*10.3mm, which does not meet the requirements of miniaturization application scenarios.

Contents of the invention

The purpose of the present invention is to provide a digital isolator ceramic packaging structure and a preparation process, aiming to reduce the size of the packaging structure while meeting high reliability in scene applications.

The embodiments of the present invention are implemented through the following technical solutions:

The invention discloses a digital isolator ceramic packaging structure, which includes:

Ceramic tube shell, the opposite sides of the ceramic tube shell are respectively provided with a first surface cavity and a second surface cavity; the ceramic tube shell is also provided with a number of bonding fingers for wire bonding;

A first interface isolation circuit, the first interface isolation circuit is arranged in the first surface cavity;

a second interface isolation circuit, the second interface isolation circuit is arranged in the second surface cavity;

Wherein, the first side cavity is sealed using a parallel sealing and welding process, and the second side cavity is sealed using a gold-tin alloy welding process; the first side cavity and the second side cavity are also filled with pressure-resistant Silicone.

In an embodiment of the present invention, the first interface isolation circuit includes a first isolation chip, a second isolation chip, a first DC/DC isolation power supply, a first interface chip and a plurality of first bonding wires; An isolation chip, the second isolation chip, the first DC/DC isolation power supply and the first interface chip are all arranged in the first surface cavity through insulating adhesive glue, and are connected through the first key The lead wires are connected to each other.

In an embodiment of the present invention, the minimum distance between the first isolation chip and the second isolation chip is 1 mm.

In an embodiment of the present invention, the second interface isolation circuit includes a third isolation chip, a fourth isolation chip, a second DC/DC isolation power supply, a second interface chip and a plurality of second bonding wires; The three isolation chips, the fourth isolation chip, the second DC/DC isolation power supply and the second interface chip are all arranged in the second surface cavity through insulating adhesive, and are connected through the second key The lead wires are connected to each other.

In an embodiment of the present invention, the minimum distance between the third isolation chip and the fourth isolation chip is 1 mm.

In one embodiment of the present invention, the parallel sealing and welding process includes a metal welding frame made of Kovar and a parallel sealing and welding cover plate; the metal welding frame made of Kovar is arranged on the ceramic body corresponding to the first surface cavity. On the tube shell, the parallel sealing and welding cover plate is welded on the ceramic tube shell and covers the first surface cavity.

In one embodiment of the present invention, the gold-tin alloy fusion sealing process includes an electroplated metal area and a ceramic gold-tin fusion sealing cover plate; the electroplated metal area is provided in the ceramic tube shell corresponding to the second surface cavity. On the ceramic tube shell, the gold-tin alloy seal is welded to the ceramic tube shell and covers the second surface cavity.

In an embodiment of the present invention, the distance between the electroplated metal area and the lead-out end of the ceramic tube shell is 0.8 mm.

In an embodiment of the present invention, the ceramic tube shell is also provided with a glue injection hole and an exhaust hole.

The technical solutions of the embodiments of the present invention have at least the following advantages and beneficial effects:

In a digital isolator that integrates the first interface isolation circuit and the second interface isolation circuit and satisfies the signal input end and output end isolation withstand voltage capability of more than 2500Vrms, the present invention can meet the requirements for miniaturization of product packaging appearance, that is, the board area is reduced. It is less than 1/2 of the conventional separated plastic-encapsulated digital isolator. At the same time, the invention adopts a ceramic packaging structure, which can avoid the reduction of the voltage resistance of the digital isolator due to water vapor intrusion in high-temperature and high-humidity environments. Plastic encapsulated digital isolators have problems such as poor reliability, short lifespan or even failure caused by cracking due to high-energy radiation exposure and low vacuum expansion.

Description of the drawings

Figure 1 is a structural principle diagram of the prior art;

Figure 2 is an exploded view of the present invention;

Figure 3 is a cross-sectional view of the present invention;

Figure 4 is a schematic diagram of the assembly of the first cavity;

Figure 5 is a schematic diagram of the assembly of the second surface cavity;

Figure 6 is a front view of the ceramic tube shell;

Figure 7 is a back view of the ceramic tube shell;

Figure 8 is a dimensional drawing of the present invention.

Icon: 1-ceramic tube shell, 1a-first side cavity, 1b-second side cavity, 1c-glue injection hole, 1d-exhaust hole, 11-Kovar metal welding frame, 12-parallel sealing welding Cover plate, 13-electroplated metal area, 14-ceramic gold-tin fusion sealing cover plate, 2-first interface isolation circuit, 21-first isolation chip, 22-second isolation chip, 23-first DC/DC isolation power supply , 24-the first interface chip, 25-the first bonding wire, 3-the second interface isolation circuit, 31-the third isolation chip, 32-the fourth isolation chip, 33-the second DC/DC isolation power supply, 34- The second interface chip, 35-second bonding wire, 4-voltage-resistant organic silicone, 5-insulating adhesive sheet.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, rather than all embodiments. The components of the embodiments of the invention generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations.

Therefore, the following detailed description of the embodiments of the invention provided in the appended drawings is not intended to limit the scope of the claimed invention, but rather to represent selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.

It should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate the orientation or positional relationship: The orientations or positional relationships shown in the drawings are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood. are limitations of the present invention. Furthermore, the terms “first”, “second” and “third” are used for descriptive purposes only and are not to be understood as indicating or implying relative importance. It is used only to distinguish one entity or operation from another entity or operation, but does not necessarily require or imply any such actual relationship or order between these entities or operations.

In the description of the present invention, it should be noted that, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood on a case-by-case basis.

In the description of the present invention, "plurality" means two or more than two, unless otherwise explicitly and specifically limited.

Example 1:

Please refer to Figures 2-8, a digital isolator ceramic packaging structure, including a ceramic shell 1, a first interface isolation circuit 2, a second interface isolation circuit 3, a Kovar material metal welding frame 11, and a parallel welding cover plate 12. Electroplated metal area 13 and ceramic gold-tin fusion sealing cover plate 14.

As shown in Figure 8, in this embodiment, the size of the ceramic shell 1 is preferably 9.5mm*9.5mm*4.3mm, that is, the length is 9.5mm, the width is 9.5mm, and the thickness is 4.3mm; when the chip select CAN interface and 485 interface are required In the application scenario, the area of the flat board is less than 1/2 of the traditional discrete device digital isolator. The structure is packaged in ceramic CLCC25, with pins arranged on both sides of the signal isolation. The minimum pin spacing is 8.1mm, which meets 2500V isolation withstand voltage requirement.

The ceramic tube shell 1 is provided with a first surface cavity 1a and a second surface cavity 1b on opposite sides respectively. The side of the ceramic tube shell 1 provided with the first surface cavity 1a is also provided with a number of wire bonding holes. Bonding finger.

As shown in Figure 2, Figure 3 and Figure 4, the first interface isolation circuit 2 is arranged in the first surface cavity 1a; specifically, the first interface isolation circuit 2 includes a first isolation chip 21, a second isolation chip 22, The first DC/DC isolated power supply 23, the first interface chip 24 and a plurality of first bonding wires 25, and the first isolation chip 21, the second isolation chip 22, the first DC/DC isolated power supply 23 and the first interface chip 24 They are respectively arranged in the first surface cavity 1a through insulating adhesive sheets 5 and arranged as shown in FIG. 4, and the various components are connected to each other through first bonding wires 25.

Among them, the minimum distance between the first isolation chip 21 and the second isolation chip 22 is 1 mm, ensuring sufficient distance to reduce the risk of high-voltage breakdown. It should be noted that in this embodiment, in actual process production, due to errors caused by the process, the minimum distance between the first isolation chip 21 and the second isolation chip 22 can be an interval, and the interval value is 1mm-1.2mm. , the minimum distance between the first isolation chip 21 and the second isolation chip 22 is within this interval value, which can meet the process requirements.

In this embodiment, the first interface isolation circuit 2 is preferably a CAN interface isolation circuit, and the first interface chip 24 is preferably a CAN interface chip.

As shown in Figure 3, the first surface cavity 1a is filled with pressure-resistant organic silica gel 4, completely covering the first isolation chip 21, the second isolation chip 22, the first DC/DC isolation power supply 23, and the first interface chip 24 and insulation adhesive sheet glue 5. This ensures that the first isolation chip 21 and the second isolation chip 22 as well as the primary and secondary sides of the first DC/DC isolation power supply 23 meet the voltage withstand capabilities required by the design.

The first surface cavity 1a is sealed using a parallel sealing and welding process. Specifically, as shown in Figures 2, 3 and 4, a metal welding frame 11 made of Kovar is welded to the ceramic tube shell 1 with the first surface cavity 1a. position, the parallel sealing and welding cover plate 12 is welded on the ceramic tube shell 1 and covers the first surface cavity 1a. The parallel sealing and welding process can simultaneously ensure the air sealing requirements of this ceramic packaging structure when the pressure-resistant organic silicone 4 does not withstand high temperatures.

As shown in Figure 2, Figure 3 and Figure 5, the second interface isolation circuit 3 is provided in the second surface cavity 1b; specifically, the second interface isolation circuit 3 includes a third isolation chip 31, a fourth isolation chip 32, The second DC/DC isolated power supply 33, the second interface chip 34 and a plurality of second bonding wires 35, and the third isolation chip 31, the fourth isolation chip 32, the second DC/DC isolated power supply 33 and the second interface chip 34 They are respectively arranged in the second surface cavity 1b through insulating adhesive sheets 5 and arranged as shown in FIG. 5 , and the various components are connected to each other through second bonding wires 35 .

Among them, the minimum distance between the third isolation chip 31 and the fourth isolation chip 32 is 1 mm, ensuring sufficient distance to reduce the risk of high-voltage breakdown. It should be noted that in this embodiment, in the same manner as the first interface isolation circuit 2 , in actual process production, due to errors caused by the process, the minimum distance between the first isolation chip 21 and the second isolation chip 22 may be one. The interval value is 1mm-1.2mm. The minimum distance between the third isolation chip 31 and the fourth isolation chip 32 is within the interval value, which can meet the process requirements.

In this embodiment, the second interface isolation circuit 3 is preferably a 485 interface isolation circuit, and the second interface chip 34 is preferably a 485 interface chip.

As shown in Figure 3, the second surface cavity 1b is also filled with pressure-resistant organic silica gel 4, completely covering the third isolation chip 31, the fourth isolation chip 32, the second DC/DC isolation power supply 33, and the second interface chip. 34 and insulating sheet glue 5. This can ensure that the third isolation chip 31 and the fourth isolation chip 32 as well as the primary and secondary sides of the second DC/DC isolation power supply 33 meet the voltage withstand capabilities required by the design.

The second side cavity 1b is sealed using a gold-tin alloy sealing process. Specifically, as shown in Figures 2, 3, 5 and 7, the electroplated metal area 13 is provided on the ceramic along the outer periphery of the second side cavity 1b. On the tube shell 1, a ceramic gold-tin fusion sealing cover plate 14 is welded on the ceramic tube shell 1 and covers the second surface cavity 1b. The gold-tin alloy sealing process can ensure the air sealing requirements of the second side cavity of this ceramic packaging structure while meeting the design of this ceramic packaging structure. It also provides a semi-enclosed filling space for pouring pressure-resistant organic silicone 4.

It should be noted that the sealing method of the surface where the lead-out end of the device of the ceramic tube 1 is located is also sealed by a glass cover plate or a cover plate made of other materials with excellent insulation properties.

Furthermore, the distance between the electroplated metal area 13 and the lead-out end of the ceramic tube shell 1 is preferably 0.8mm. This size can ensure that the signal input and output pins of the digital isolator will not be affected by the metal between the electroplated metal area 13 and the second side cavity 1b. High voltage breakdown in the sealing area due to insufficient surface creepage distance.

Further, as shown in Figure 6, the ceramic tube shell 1 is provided with a glue injection hole 1c and an exhaust hole 1d. The glue injection hole 1c and the exhaust hole 1d are connected with the second surface cavity 1b. The glue injection hole 1c is used for The pressure-resistant organic silica gel 4 is filled into the sealed second surface cavity 1b to meet the process requirements. The exhaust hole 1d is used to discharge the air in the second surface cavity during the filling process of the pressure-resistant organic silica gel 4. In this embodiment, the size of the glue injection hole 1c is preferably 1.8mm*9mm, and the size of the exhaust hole 1d is 1.8mm*7.8mm. The exhaust holes and glue injection holes will penetrate the first side cavity and the second side cavity.

This embodiment is a digital isolator that integrates the CAN interface and the 485 interface and meets the isolation voltage resistance of the signal input end and the output end to reach more than 2500Vrms. It can meet the requirements for miniaturization of the product packaging appearance, that is, the board area is reduced to less than that of conventional isolation. 1/2 of the plastic package digital isolator. At the same time, the invention adopts a ceramic package structure, which can avoid the reduction of the voltage resistance of the plastic package isolator due to water vapor intrusion in high temperature and high humidity environments, and the plastic package digital isolator in the space environment. High-energy ray irradiation cracking, low vacuum expansion, etc. cause problems such as poor reliability, short life, and even failure.

Example 2

A preparation process for preparing the digital isolator ceramic packaging structure described in the above embodiments includes the following steps:

S1. First, stick the first isolation chip 21, the second isolation chip 22, the first DC/DC isolation power supply 23 and the first interface chip 24 inside the first surface cavity 1a using the insulating adhesive glue 5 and heat it at 150°C. Curing for two hours in the environment; then stick the third isolation chip 31, the fourth isolation chip 32, the second DC/DC isolation power supply 33 and the second interface chip 34 to the second side cavity 1b with the insulating adhesive sheet glue 5 Internally and cured at 150°C for two hours;

S2. Use thermal pressure ultrasonic bonding to bond the first isolation chip 21, the second isolation chip 22, the first DC/DC isolation power supply 23, the first interface chip 24, and the third isolation chip 31 and the fourth isolation chip. 32. Bonding of the second DC/DC isolated power supply 33 and the second interface chip 34;

S3. Weld the ceramic tube shell 1, the electroplated metal area 13 and the ceramic gold-tin fusion sealing cover 14 together to cover the second side cavity 1b; put the Kovar metal welding frame 11 corresponding to the first side cavity 1a is welded to the ceramic tube shell 1;

S4. First, pour the pressure-resistant organic silica gel 4 into the second surface cavity 1b through the injection hole 1c, and perform high-temperature curing at least twice, and then pour the pressure-resistant organic silica gel 4 into the first surface cavity 1a until cured. The rear colloid plane is flush with the metal welding frame; after the above process is completed, the parallel sealing and welding cover plate 12 is welded to the ceramic tube shell 1 to cover the first surface cavity 1a.

In this embodiment, the preparation of the digital isolator ceramic packaging structure described in the above embodiment is completed according to the method of bonding the chip - wire bonding - alloy sealing - potting or injection glue - alloy sealing or parallel sealing and welding.

In another implementation manner of this embodiment, the chip can also be bonded according to the second surface cavity 1b - the second surface cavity 1b wire bonding - alloy sealing - the first surface cavity 1a bonding - the first surface The digital isolator ceramic packaging structure described in the above embodiment is prepared by wire bonding of the cavity 1a - glue filling or glue injection - alloy sealing or parallel sealing and welding.

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims (9)

1. A digital isolator ceramic packaging structure, characterized by including: Ceramic tube shell, the opposite sides of the ceramic tube shell are respectively provided with a first surface cavity and a second surface cavity; the ceramic tube shell is also provided with a number of bonding fingers for wire bonding; A first interface isolation circuit, the first interface isolation circuit is arranged in the first surface cavity; a second interface isolation circuit, the second interface isolation circuit is arranged in the second surface cavity; Wherein, the first side cavity is sealed using a parallel sealing and welding process, and the second side cavity is sealed using a gold-tin alloy welding process; the first side cavity and the second side cavity are also filled with pressure-resistant Silicone. 2. A digital isolator ceramic packaging structure according to claim 1, characterized in that the first interface isolation circuit includes a first isolation chip, a second isolation chip, a first DC/DC isolation power supply, a first An interface chip and a plurality of first bonding wires; the first isolation chip, the second isolation chip, the first DC/DC isolation power supply and the first interface chip are all arranged on the The first surface is inside the cavity and connected to each other through the first bonding wire. 3. A digital isolator ceramic packaging structure according to claim 2, characterized in that the minimum distance between the first isolation chip and the second isolation chip is 1 mm. 4. A digital isolator ceramic packaging structure according to claim 1, characterized in that the second interface isolation circuit includes a third isolation chip, a fourth isolation chip, a second DC/DC isolation power supply, a second An interface chip and a plurality of second bonding wires; the third isolation chip, the fourth isolation chip, the second DC/DC isolation power supply and the second interface chip are all arranged on the The second surface is inside the cavity and connected to each other through the second bonding wire. 5. A digital isolator ceramic packaging structure according to claim 4, characterized in that the minimum distance between the third isolation chip and the fourth isolation chip is 1 mm. 6. A digital isolator ceramic packaging structure according to claim 1, wherein the parallel sealing and welding process includes a Kovar metal welding frame and a parallel sealing and welding cover plate; the Kovar metal welding frame The parallel sealing and welding cover plate is welded on the ceramic tube shell along the outer circumferential direction of the first surface cavity, and covers the Kovar metal welding frame and the ceramic tube shell. Describe the first surface cavity. 7. A digital isolator ceramic packaging structure according to claim 1, characterized in that the gold-tin alloy sealing process includes an electroplated metal area and a ceramic gold-tin fusion sealing cover plate; the electroplated metal area is provided on On the ceramic tube shell with the second surface cavity, the gold-tin alloy sealing is welded on the ceramic tube shell and covers the electroplated metal area and the second surface cavity. 8. A digital isolator ceramic packaging structure according to claim 7, characterized in that the distance between the electroplated metal area and the lead-out end of the ceramic tube shell is 0.8 mm. 9. A digital isolator ceramic packaging structure according to claim 1, characterized in that the ceramic tube shell is also provided with a glue injection hole and an exhaust hole.