CN116960000A - Large-board-level fan-out type packaging method and large-board-level fan-out type packaging structure - Google Patents
Large-board-level fan-out type packaging method and large-board-level fan-out type packaging structure Download PDFInfo
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- CN116960000A CN116960000A CN202310786144.3A CN202310786144A CN116960000A CN 116960000 A CN116960000 A CN 116960000A CN 202310786144 A CN202310786144 A CN 202310786144A CN 116960000 A CN116960000 A CN 116960000A
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 36
- 238000005520 cutting process Methods 0.000 claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 claims abstract description 27
- 238000004381 surface treatment Methods 0.000 claims abstract description 15
- 239000000853 adhesive Substances 0.000 claims abstract description 11
- 230000001070 adhesive effect Effects 0.000 claims abstract description 11
- 238000009432 framing Methods 0.000 claims abstract description 5
- 229910052737 gold Inorganic materials 0.000 claims description 20
- 239000010931 gold Substances 0.000 claims description 20
- 238000007789 sealing Methods 0.000 claims description 19
- 238000003825 pressing Methods 0.000 claims description 9
- 239000003292 glue Substances 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 claims description 7
- 239000012634 fragment Substances 0.000 abstract description 6
- 239000002313 adhesive film Substances 0.000 abstract description 3
- 239000002390 adhesive tape Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 108
- 239000005022 packaging material Substances 0.000 description 7
- 238000009713 electroplating Methods 0.000 description 5
- 238000005553 drilling Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000037303 wrinkles Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a large-board-level fan-out type packaging method and a large-board-level fan-out type packaging structure. The large-board-level fan-out type packaging method comprises the following steps: providing a temporary carrier plate and a plurality of chips, attaching the chips to the temporary carrier plate and cutting the chips into blocks to form frame-cutting chips; carrying out surface treatment on the chips on each frame cutting chip, typesetting and framing a plurality of frame cutting chips; manufacturing a frame, attaching the frame to the temporary carrier plates after splicing the frames, and enabling the frame to cover gaps among the temporary carrier plates so that chips are exposed out of the frame; performing plastic packaging on the chip, and separating the temporary carrier plate to obtain a chip plastic packaging body; and electrically leading out the chip I/O port from the double sides of the chip plastic package body. The invention improves the warping of the board on the basis of the Die-First process, shortens the production flow, avoids fragments in the process of sheet flowing, does not need to adhere adhesive tape or film to fix or improve the strength of the plastic package body after separating the temporary carrier board, and achieves the purposes of small warping, no fragments, no residual adhesive, less working procedures, improved production efficiency and yield and reduced cost.
Description
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a large-board-level fan-out type packaging method and a large-board-level fan-out type packaging structure.
Background
At present, a PCB carrier plate is generally adopted as a substrate (RDL-First technology) for large-board-level fan-out packaging, a chip is pasted on the PCB carrier plate, then plastic packaging is carried out, and I/O is led out by single-sided circuit layering; or a Die-First process is adopted by a separable temporary carrier plate, chips are firstly pasted on the separable temporary carrier plate, then the separable temporary carrier plate is subjected to plastic package, and RDL (RDL) is added to lead out the I/O of the chips.
No matter the chip has only single-sided I/O or the front and back sides have I/O to be led out or multi-layer circuits are needed, the existing technology has the defects of board warpage, long single-sided RDL layering process, high chip breaking risk of the flowing sheet during or after the temporary carrier plate is separated, and the like, so that the production efficiency is greatly reduced, the yield is reduced, and the cost is increased.
Disclosure of Invention
The invention aims to provide a large-board-level fan-out type packaging method and a large-board-level fan-out type packaging structure manufactured by the method, which are used for improving board warpage, shortening the production flow, avoiding fragments in the process of sheet flow, avoiding sticking adhesive tapes or films to fix or improve the strength of a plastic package body after separating a temporary carrier plate, and achieving the purposes of small warpage, no fragments, no residual adhesive, fewer working procedures, improving the production efficiency and yield and reducing the cost.
To achieve the purpose, the invention adopts the following technical scheme:
the large-board-level fan-out packaging method comprises the following steps:
s10, providing a temporary carrier plate and a plurality of chips, attaching the chips to the temporary carrier plate and dicing to form a frame-cutting chip;
s20, carrying out surface treatment on the chips on each frame cutting chip, and typesetting and framing a plurality of frame cutting chips;
s30, manufacturing a frame according to typesetting, attaching the frame to the temporary carrier plates after frame assembly, enabling the frame to cover gaps between the temporary carrier plates of two adjacent frame-cutting chips after frame assembly, enabling all chips to be exposed to the frame, and removing bubbles after attachment; wherein the frame is a semi-transparent BT plate containing no copper, which can provide insulation and sufficient rigidity to the frame;
s40, performing plastic packaging treatment on the chip, and then separating the temporary carrier plate to obtain a chip plastic package body;
s50, electrically leading out the I/O port of the chip from the two sides of the chip plastic package body.
The temporary carrier plate in the invention is in a large plate level. Because the chip must be subjected to surface treatment, the chip is limited by corresponding processing equipment, and the large-board-level temporary carrier plate attached with the chip must be cut into small blocks, namely frame-cutting chips; after the surface treatment is carried out on the chips on the frame cutting chips, typesetting and frame splicing are carried out on each frame cutting chip according to the design, at the moment, gaps exist between temporary carrier plates of two adjacent frame cutting chips, the situation that plastic packaging materials flow out along the gaps exists when plastic packaging is directly carried out, and the product yield is affected; according to the invention, the frame in the hollowed-out form is manufactured according to typesetting design, then the frame is attached to the temporary carrier plates after the frame is spliced, and the frame just covers the gap between the temporary carrier plates of two adjacent frame cutting chips, so that the outflow of plastic packaging materials can be avoided, and the product yield can be improved. And removing the temporary carrier plate after plastic packaging, and manufacturing a circuit to electrically lead out the I/O port of the chip, so as to obtain the large-plate fan-out type packaging structure. In addition, the frame is embedded into the plastic packaging material, so that the rigidity of the product can be effectively improved, the phenomenon of fragments is avoided, and the yield of the product is improved.
In step S30, the tape and the film are not required to be stuck in the film-feeding process, so that the influence of residual adhesive on products is avoided, and the product yield is improved. The double-sided symmetrical design and manufacture of the rewiring layer can effectively reduce warpage and greatly improve production efficiency.
In the invention, in step S40, the corresponding plastic packaging material is selected according to the product requirement, and after plastic packaging, the temporary carrier plate and the bonding adhesive can be removed by means of bonding, and the corresponding bonding removing scheme can be adopted according to the bonding adhesive characteristics, wherein the plastic packaging and the bonding removing are all prior art in the field, and detailed description is omitted.
In the present invention, the surface treatment of the chip is a conventional technology in the art, and detailed description thereof is omitted.
As a preferred embodiment of the large board-level fan-out package method, step S10 specifically includes:
s10a, providing a temporary carrier plate, and pressing bonding glue on one side of the temporary carrier plate along the thickness direction of the temporary carrier plate;
s10b, providing a plurality of port chips with I/O on two sides, and attaching the chips to the bonding adhesive;
s10c, cutting the temporary carrier plate attached with the chips into a plurality of frame cutting chips.
In the invention, the temporary carrier plate can be selected from BT plate or FR4, and dust removal treatment is needed to be carried out on the temporary carrier plate before bonding glue is pressed. When the bonding glue is pressed, the pressure, temperature and speed during pressing are required to be controlled, so that bubbles and wrinkles are avoided.
As one of the preferable schemes of the large board-level fan-out package method, step S50 specifically includes the steps of:
s50a, carrying out hole opening treatment on the chip plastic package body to form a plurality of through holes and blind holes for exposing I/O ports of the chip;
s50b, manufacturing a first conductive column in the through hole and the blind hole, and manufacturing a first rewiring layer electrically connected with the first conductive column on two sides of the chip plastic package body;
s50c, preparing a nickel-palladium-gold layer on the surface of the first rewiring layer.
In step S50c, the first redistribution layer is subjected to surface treatment, that is, a protective layer, that is, a nickel-palladium-gold layer, is prepared on the first redistribution layer by electroless nickel-palladium-gold, and the nickel-palladium-gold layer can protect the first redistribution layer on one hand and is beneficial to SMT or wire bonding on the other hand.
As a second preferred embodiment of the large board-level fan-out package method, step S50 specifically includes the following steps:
s50a, carrying out hole opening treatment on the chip plastic package body to form a plurality of through holes and blind holes for exposing I/O ports of the chip;
s50b, manufacturing a first conductive column in the through hole and the blind hole, and manufacturing a first rewiring layer electrically connected with the first conductive column on two sides of the chip plastic package body;
s50c, respectively pressing dielectric layers on the two sides of the chip plastic package body and the surface of the rewiring layer, wherein corresponding dielectric layer materials and corresponding pressing parameters can be selected according to product requirements;
s50d, carrying out hole opening treatment (laser hole opening, particularly adopting corresponding laser drilling parameters according to the requirement of blind holes of products) on the dielectric layer to form a plurality of hole structures (namely blind holes) exposing the bonding pad area of the first rewiring layer;
s50e, manufacturing a second conductive post electrically connected with the pad region of the first rewiring layer in the hole structure, and manufacturing a second rewiring layer electrically connected with the second conductive post on the surface of the dielectric layer at the same time;
s50f, preparing a nickel-palladium-gold layer on the surface of the second redistribution layer.
In the above two schemes, in step S50a, the chip plastic package body (specifically, the plastic package layer formed after the plastic package material is cured) is specifically subjected to punching treatment by using laser, and corresponding laser punching parameters are adopted according to the requirements of the blind holes and the through holes of the product, which is not described in detail. In step S50b, electroplating parameters are set according to the product requirements, and electroplating is performed on both sides of the chip plastic package body. Before step S50b, a seed layer may be first fabricated in the blind hole and the through hole and on the surface of the chip molding body by sputtering, and then a first redistribution layer may be fabricated, so as to improve the bonding force between the first redistribution layer and the chip molding body, and improve the stability of the circuit structure.
In step S50f, the second redistribution layer is subjected to surface treatment, that is, a protective layer, namely, a nickel-palladium-gold layer, is prepared on the second redistribution layer by nickel-palladium-gold chemical treatment, and the nickel-palladium-gold layer can protect the second redistribution layer on one hand and is beneficial to SMT or wire bonding on the other hand.
Before step S50e, the seed layer may be prepared first, and then the second redistribution layer may be prepared according to need, which will not be described in detail.
On the other hand, the invention provides a large board-level fan-out type packaging structure manufactured by adopting one of the preferable schemes of the large board-level fan-out type packaging method, which comprises the following steps:
the packaging structure comprises a plastic sealing layer, a frame and a plurality of groups of chips, wherein the frame and the plurality of groups of chips are packaged in the plastic sealing layer, two adjacent groups of chips are separated by the frame, and one surfaces of the chips and the frame are flush with one side of the plastic sealing layer;
the first rewiring layers are electrically connected with the first conductive columns and the I/O ports of the chip;
and the nickel palladium gold layer is positioned on the surface of the first rewiring layer.
Wherein, the frame is embedded to the plastic envelope, can improve the rigidity of product, avoids the piece, promotes the product yield.
In still another aspect, the present invention provides a large board fan-out package structure manufactured by adopting the second preferred scheme of the large board fan-out package method, including:
the packaging structure comprises a plastic sealing layer, a frame and a plurality of groups of chips, wherein the frame and the plurality of groups of chips are packaged in the plastic sealing layer, two adjacent groups of chips are separated by the frame, and one surfaces of the chips and the frame are flush with one side of the plastic sealing layer;
the first rewiring layers are electrically connected with the first conductive columns and the I/O ports of the chip;
the dielectric layers are positioned on two sides of the plastic sealing layer and cover the first rewiring layer;
a second conductive pillar electrically connected to the first redistribution layer through the dielectric layer and a second redistribution layer on the surface of the dielectric layer, the second redistribution layer being electrically connected to the second conductive pillar;
and the nickel palladium gold layer is positioned on the surface of the second redistribution layer.
The scheme adopts the structural design of a plurality of rewiring layers, and can improve the line strength.
The invention has the beneficial effects that:
1. after the surface treatment is carried out on the chips on the frame cutting chips, typesetting and frame splicing are carried out on each frame cutting chip according to the design.
2. The frame is embedded into the plastic packaging material, so that the rigidity of the product can be effectively improved, the phenomenon of fragments in the sheet flowing process is avoided, and the product yield is improved.
3. And in the film flowing process, adhesive tapes and films are not required to be adhered, so that the influence of residual adhesive on products is avoided.
4. And circuits are manufactured on two sides simultaneously, so that the production efficiency is greatly improved.
Drawings
Fig. 1 is a flowchart of a large board-level fan-out package method according to embodiment 1 of the present invention.
Fig. 2 is a schematic cross-sectional view of a temporary carrier according to embodiment 1 of the present invention.
Fig. 3 is a schematic cross-sectional view of the bonding adhesive of embodiment 1 of the present invention attached to a temporary carrier.
Fig. 4 is a schematic cross-sectional view of a chip attached to a temporary carrier according to embodiment 1 of the present invention.
Fig. 5 is a schematic cross-sectional view of a temporary carrier with chips cut according to embodiment 1 of the present invention.
Fig. 6 is a schematic cross-sectional view of a split frame chip according to embodiment 1 of the present invention.
Fig. 7 is a schematic cross-sectional view of a frame according to embodiment 1 of the present invention.
Fig. 8 is a schematic cross-sectional view of a temporary carrier plate with a frame attached to the temporary carrier plate after the frame is assembled according to embodiment 1 of the present invention.
Fig. 9 is a schematic cross-sectional view of the molded product according to embodiment 1 of the present invention.
Fig. 10 is a schematic cross-sectional view of the temporary carrier plate according to embodiment 1 of the present invention after removal.
Fig. 11 is a schematic partial cross-sectional view of the molding layer of example 1 of the present invention after opening.
Fig. 12 is a schematic partial cross-sectional view of the first conductive pillar and the first redistribution layer according to embodiment 1 of the present invention.
Fig. 13 is a schematic view in partial cross-section after the piezoelectric layer according to embodiment 1 of the present invention.
Fig. 14 is a schematic partial cross-sectional view of a dielectric layer after opening according to embodiment 1 of the present invention.
Fig. 15 is a schematic partial cross-sectional view of a second conductive pillar and a second redistribution layer according to embodiment 1 of the present invention.
Fig. 16 is a schematic partial sectional view of the second redistribution layer according to embodiment 1 of the present invention after surface treatment.
Fig. 17 is a physical diagram of a large board-level fan-out package structure according to embodiment 1 of the present invention.
Fig. 18 is a schematic partial sectional view of the first re-wiring layer after surface treatment according to embodiment 2 of the present invention.
Detailed Description
The technical scheme of the invention is further described by the following specific embodiments.
The various starting materials of the present invention are commercially available, or may be prepared according to methods conventional in the art, unless specifically indicated.
Example 1
As shown in fig. 1, the large board-level fan-out package method of the present embodiment is as follows:
1. a BT plate is selected as a temporary carrier plate 1 (figure 2), and the surface of the temporary carrier plate 1 is dedusted;
2. as shown in fig. 3, bonding glue 2 is pressed on a temporary carrier plate 1, and the pressure, temperature and speed during pressing are controlled to avoid bubbles and wrinkles;
3. as shown in fig. 4, a plurality of groups of chips 3 are attached to a temporary carrier plate 1;
4. as shown in fig. 5, the temporary carrier plate 1 after the patch is cut according to a chipset to form frame-cutting chips a, and the chips 3 on each frame-cutting chip a are in a group;
5. surface treatment of the chip 3 on the split frame chip A;
6. typesetting and framing the frame-cutting chips A, as shown in FIG. 6;
7. according to typesetting requirements, a semitransparent BT plate (without copper) is selected to manufacture a frame 4 with a hollowed-out structure shown in FIG. 7, and the thickness of the frame 4 is selected according to product requirements;
8. attaching a frame 4 to the temporary carrier plate 1 after frame splicing, wherein the frame is fixed on the temporary carrier plate 1 through bonding glue 2 on the temporary carrier plate 1 to remove bubbles after attaching, and each group of chips 3 is positioned in a hollowed-out area of the frame 4 as shown in fig. 8;
9. the chip 3 and the frame 4 are subjected to plastic package by adopting EMC plastic package materials, as shown in figure 9;
10. after the plastic packaging material is solidified (namely, plastic packaging layer 5), separating the temporary carrier plate 1 and removing the bonding adhesive 2, as shown in fig. 10;
11. laser drilling the plastic layer 5, and forming a plurality of through holes 51 and blind holes 52 exposing the I/O ports of the chip 3, as shown in FIG. 11;
12. as shown in fig. 12, first conductive pillars 61 are formed in the through holes 51 and the blind holes 52 by electroplating, and first rewiring layers 52 are simultaneously formed on both sides of the molding layer 5;
13. dielectric layer 7 is pressed on both sides of plastic layer 5 and on the surface of first re-wiring layer 62 as shown in fig. 13;
14. laser drilling the dielectric layer 7 to form a via 71 exposing a portion of the first re-wiring layer 62, as shown in fig. 14;
15. fabricating a second conductive pillar 81 in the via hole 71 by electroplating and simultaneously fabricating a second redistribution layer 82 on both sides of the dielectric layer 7, as shown in fig. 15;
16. the surface treatment is performed on the double-sided second redistribution layer 82, that is, nickel palladium gold is formed on the surface of the second redistribution layer 82, so as to obtain a nickel palladium gold layer 9, and a large-board-level fan-out type package structure (physical diagram is shown in fig. 17) as shown in fig. 16 is obtained.
As shown in fig. 16, the large board-level fan-out package structure of the present embodiment includes:
the packaging structure comprises a plastic layer 5, a frame 4 and a plurality of groups of chips 3, wherein the frame 4 and the groups of chips 3 are packaged in the plastic layer 5, two adjacent groups of chips 3 are separated by the frame 4, and one surfaces of the chips 3 and the frame 4 are flush with one side of the plastic layer 5;
a plurality of first conductive pillars 61 penetrating through the plastic sealing layer 5 and first rewiring layers 62 located at two sides of the plastic sealing layer 5, wherein the first rewiring layers 62 are electrically connected with the first conductive pillars 61 and the I/O ports of the chip 3;
a dielectric layer 7 located at both sides of the plastic layer 5 and covering the first re-wiring layer 62;
a second conductive pillar 81 electrically connected to the first redistribution layer 62 through the dielectric layer 7 and a second redistribution layer 82 located on the surface of the dielectric layer 7, the second redistribution layer 82 being electrically connected to the second conductive pillar 81;
and a nickel-palladium-gold layer 9 on the surface of the second redistribution layer 82.
Example 2
This embodiment is substantially the same as embodiment 1 described above (refer to fig. 1 to 12 of embodiment 1), except that the rewiring layer has a double-sided single-layer structure.
Specifically, the large board-level fan-out package method of the present embodiment is as follows:
1. FR4 is selected as a temporary carrier plate 1 (refer to figure 2), and the surface of the temporary carrier plate 1 is dedusted;
2. pressing bonding glue 2 (refer to fig. 3) on the temporary carrier plate 1, and controlling the pressure, temperature and speed during pressing to avoid bubbles and wrinkles;
3. attaching a plurality of groups of chips 3 (refer to fig. 4) on the temporary carrier plate 1;
4. cutting the temporary carrier plate 1 after the surface mounting according to a chipset to form frame cutting chips A (refer to FIG. 5), wherein the chips 3 on each frame cutting chip A are in a group;
5. surface treatment of the chip 3 on the split frame chip A;
6. typesetting and framing the frame-cutting chips A (refer to FIG. 6);
7. according to typesetting requirements, a frame 4 (refer to fig. 7) with a hollowed-out structure is manufactured by using a semitransparent BT plate (without copper), and the thickness of the frame 4 is selected according to product requirements;
8. attaching a frame 4 to the spliced temporary carrier plate 1 (refer to fig. 8), fixing the frame on the temporary carrier plate 1 through bonding glue 2 on the temporary carrier plate 1, and removing bubbles after attaching, wherein each group of chips is positioned in a hollowed-out area of the frame 4;
9. the chip 3 and the frame 4 are subjected to plastic package by adopting EMC plastic package materials (refer to FIG. 9);
10. after the plastic packaging material is solidified (namely, plastic packaging layer 5), separating the temporary carrier plate 1 and removing the bonding adhesive 2 (refer to fig. 10);
11. laser drilling the plastic layer 5, and forming a plurality of through holes 51 and blind holes 52 (refer to fig. 11) for exposing the I/O ports of the chip;
12. manufacturing first conductive pillars 61 in the through holes 51 and the blind holes 52 by electroplating, and simultaneously manufacturing first rewiring layers 62 on both sides of the plastic sealing layer 5 (refer to fig. 12);
13. the surface treatment is performed on the double-sided first redistribution layer 62, that is, the surface of the first redistribution layer 62 is plated with nickel-palladium-gold, so as to obtain the nickel-palladium-gold layer 9, and a large-board-level fan-out package structure as shown in fig. 18 is obtained.
As shown in fig. 18, the large board-level fan-out package structure of the present embodiment includes:
the packaging structure comprises a plastic layer 5, a frame 4 and a plurality of groups of chips 3, wherein the frame 4 and the groups of chips 3 are packaged in the plastic layer 5, two adjacent groups of chips 3 are separated by the frame 4, and one surfaces of the chips 3 and the frame 4 are flush with one side of the plastic layer 5;
a plurality of first conductive pillars 61 penetrating through the plastic sealing layer 5 and first rewiring layers 62 located at two sides of the plastic sealing layer 5, wherein the first rewiring layers 62 are electrically connected with the first conductive pillars 61 and the I/O ports of the chip 3;
and a nickel palladium gold layer 9 on the surface of the first redistribution layer 62.
The above examples are only for illustrating the detailed method of the present invention, and the present invention is not limited to the above detailed method, i.e., it does not mean that the present invention must be implemented depending on the above detailed method. It should be apparent to those skilled in the art that any modification of the present invention, equivalent substitution of raw materials for the product of the present invention, addition of auxiliary components, selection of specific modes, etc., falls within the scope of the present invention and the scope of disclosure.
Claims (7)
1. The large-board-level fan-out type packaging method is characterized by comprising the following steps of:
s10, providing a temporary carrier plate and a plurality of chips, attaching the chips to the temporary carrier plate and dicing to form a frame-cutting chip;
s20, carrying out surface treatment on the chips on each frame cutting chip, and typesetting and framing a plurality of frame cutting chips;
s30, manufacturing a frame according to typesetting, attaching the frame to the temporary carrier plates after frame splicing, enabling the frame to cover gaps between the temporary carrier plates of two adjacent frame-cutting chips after frame splicing, and enabling all chips to be exposed out of the frame;
s40, performing plastic packaging treatment on the chip, and then separating the temporary carrier plate to obtain a chip plastic package body;
s50, electrically leading out the I/O port of the chip from the two sides of the chip plastic package body.
2. The large board-level fan-out packaging method according to claim 1, wherein step S10 specifically comprises:
s10a, providing a temporary carrier plate, and pressing bonding glue on one side of the temporary carrier plate along the thickness direction of the temporary carrier plate;
s10b, providing a plurality of chips, and attaching the chips to the bonding adhesive;
s10c, cutting the temporary carrier plate attached with the chips into a plurality of frame cutting chips.
3. The large board-level fan-out package method of claim 1, wherein in step S30, the frame is a copper-free translucent BT board.
4. The large board-level fan-out package method according to any of claims 1-3, wherein step S50 specifically comprises the steps of:
s50a, carrying out hole opening treatment on the chip plastic package body to form a plurality of through holes and blind holes for exposing I/O ports of the chip;
s50b, manufacturing a first conductive column in the through hole and the blind hole, and manufacturing a first rewiring layer electrically connected with the first conductive column on two sides of the chip plastic package body;
s50c, preparing a nickel-palladium-gold layer on the surface of the first rewiring layer.
5. The large board-level fan-out package method according to any of claims 1-3, wherein step S50 specifically comprises the steps of:
s50a, carrying out hole opening treatment on the chip plastic package body to form a plurality of through holes and blind holes for exposing I/O ports of the chip;
s50b, manufacturing a first conductive column in the through hole and the blind hole, and manufacturing a first rewiring layer electrically connected with the first conductive column on two sides of the chip plastic package body;
s50c, respectively pressing dielectric layers on the two sides of the chip plastic package body and the surface of the rewiring layer;
s50d, carrying out hole opening treatment on the dielectric layer to form a plurality of hole structures which expose the pad area of the first rewiring layer;
s50e, manufacturing a second conductive post electrically connected with a pad region of the first rewiring layer in the hole structure, and manufacturing a second rewiring layer electrically connected with the second conductive post on the surface of the dielectric layer;
s50f, preparing a nickel-palladium-gold layer on the surface of the second redistribution layer.
6. A large board-level fan-out package structure manufactured according to the large board-level fan-out package method of any of claims 1-4, comprising:
the packaging structure comprises a plastic sealing layer, a frame and a plurality of groups of chips, wherein the frame and the plurality of groups of chips are packaged in the plastic sealing layer, two adjacent groups of chips are separated by the frame, and one surfaces of the chips and the frame are flush with one side of the plastic sealing layer;
the first rewiring layers are electrically connected with the first conductive columns and the I/O ports of the chip;
and the nickel palladium gold layer is positioned on the surface of the first rewiring layer.
7. A large board-level fan-out package structure manufactured according to the large board-level fan-out package method of any of claims 1-3 or 5, comprising:
the packaging structure comprises a plastic sealing layer, a frame and a plurality of groups of chips, wherein the frame and the plurality of groups of chips are packaged in the plastic sealing layer, two adjacent groups of chips are separated by the frame, and one surfaces of the chips and the frame are flush with one side of the plastic sealing layer;
the first rewiring layers are electrically connected with the first conductive columns and the I/O ports of the chip;
the dielectric layers are positioned on two sides of the plastic sealing layer and cover the first rewiring layer;
a second conductive pillar electrically connected to the first redistribution layer through the dielectric layer and a second redistribution layer on the surface of the dielectric layer, the second redistribution layer being electrically connected to the second conductive pillar;
and the nickel palladium gold layer is positioned on the surface of the second redistribution layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310786144.3A CN116960000A (en) | 2023-06-28 | 2023-06-28 | Large-board-level fan-out type packaging method and large-board-level fan-out type packaging structure |
| PCT/CN2024/102250 WO2025002311A1 (en) | 2023-06-28 | 2024-06-28 | Large panel level fan-out packaging method and large panel level fan-out packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310786144.3A CN116960000A (en) | 2023-06-28 | 2023-06-28 | Large-board-level fan-out type packaging method and large-board-level fan-out type packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116960000A true CN116960000A (en) | 2023-10-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310786144.3A Pending CN116960000A (en) | 2023-06-28 | 2023-06-28 | Large-board-level fan-out type packaging method and large-board-level fan-out type packaging structure |
Country Status (2)
| Country | Link |
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| CN (1) | CN116960000A (en) |
| WO (1) | WO2025002311A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118782481A (en) * | 2024-09-04 | 2024-10-15 | 长电集成电路(绍兴)有限公司 | Rework method of plastic film |
| WO2025002311A1 (en) * | 2023-06-28 | 2025-01-02 | 广东佛智芯微电子技术研究有限公司 | Large panel level fan-out packaging method and large panel level fan-out packaging structure |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6031059B2 (en) * | 2014-03-31 | 2016-11-24 | 信越化学工業株式会社 | Semiconductor device, stacked semiconductor device, post-sealing stacked semiconductor device, and manufacturing method thereof |
| WO2019160566A1 (en) * | 2018-02-15 | 2019-08-22 | Didrew Technology (Bvi) Limited | Method of simultaneously fabricating multiple wafers on large carrier with warpage control stiffener |
| WO2019160567A1 (en) * | 2018-02-19 | 2019-08-22 | Didrew Technology (Bvi) Limited | System and method of fabricating glass frame fan out packaging |
| CN116960000A (en) * | 2023-06-28 | 2023-10-27 | 广东佛智芯微电子技术研究有限公司 | Large-board-level fan-out type packaging method and large-board-level fan-out type packaging structure |
-
2023
- 2023-06-28 CN CN202310786144.3A patent/CN116960000A/en active Pending
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2024
- 2024-06-28 WO PCT/CN2024/102250 patent/WO2025002311A1/en unknown
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2025002311A1 (en) * | 2023-06-28 | 2025-01-02 | 广东佛智芯微电子技术研究有限公司 | Large panel level fan-out packaging method and large panel level fan-out packaging structure |
| CN118782481A (en) * | 2024-09-04 | 2024-10-15 | 长电集成电路(绍兴)有限公司 | Rework method of plastic film |
Also Published As
| Publication number | Publication date |
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| WO2025002311A1 (en) | 2025-01-02 |
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