CN116940929A - Methods, electronic devices, computer-readable storage media, and program products for simulating electrical circuits - Google Patents
Methods, electronic devices, computer-readable storage media, and program products for simulating electrical circuits Download PDFInfo
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Abstract
本公开涉及一种用于对电路进行仿真的方法。该方法包括：接收用于确定电路版图中的相邻互连线的局部失配的局部提取指示；响应于接收到局部提取指示，基于互连线模型库、互连线失配模型集和电路版图，生成目标网表数据；以及对目标网表数据进行仿真，以生成针对相邻互连线的局部仿真结果。通过在接收到局部提取指示的情形下使用互连线模型库、互连线失配模型集和电路版图，可以提取与互连线失配模型集中对应的互连线失配模型中的相邻互连线的寄生电容表示和相邻互连线的电阻表示。此外，由于寄生电容表示和寄生电阻表示包含了蒙特卡洛因子，因此可以在寄生电容表示和寄生电阻表示中表征局部波动的情形。
The present disclosure relates to a method for simulating a circuit. The method includes: receiving a local extraction indication for determining local mismatch of adjacent interconnect lines in the circuit layout; in response to receiving the local extraction indication, based on the interconnect line model library, the interconnect line mismatch model set and the circuit Layout, generate target netlist data; and simulate the target netlist data to generate local simulation results for adjacent interconnect lines. By using an interconnect model library, an interconnect mismatch model set, and a circuit layout upon receiving local extraction instructions, adjacent interconnect mismatch models in the interconnect mismatch model set can be extracted. An indication of the parasitic capacitance of an interconnect line and an indication of the resistance of adjacent interconnect lines. In addition, since the parasitic capacitance representation and the parasitic resistance representation include Monte Carlo factors, local fluctuations can be characterized in the parasitic capacitance representation and the parasitic resistance representation.
Description
The present disclosure relates to the field of hardware design, and more particularly to a method, an electronic device, a computer readable storage medium, and a program product for simulating a circuit.
In the process of designing and manufacturing integrated circuit chips, specification formulation, integrated circuit design, chip manufacture, packaging, testing and the like are usually included, wherein the integrated circuit design further includes the stages of circuit design, layout design, mask plate manufacture and the like. The designed circuit typically requires simulation of the designed circuit before it is used in manufacturing to ensure correctness of the circuit design and to reduce performance degradation due to process variations during manufacturing.
For example, although adjacent interconnect lines are given the same line width and line spacing in the design process, the adjacent interconnect lines may have shape mismatch such as Low Error Region (LER) and erosion (error) due to the influence of processes such as optical proximity correction (optical proximity correction, OPC), photolithography, etching, chemical mechanical polishing (chemical mechanical polishing, CMP), and the like, which may also be called local fluctuation (local fluctuation) effect.
The symmetry requirements of analog circuit designs such as current mirrors are extremely stringent, requiring evaluation of not only local fluctuations of the device, but also mismatch of adjacent interconnect lines. Local fluctuations at the device level can be simulated by Monte Carlo by invoking a mismatch model by an integrated circuit generic simulator (simulation program with integrated circuit emphasis, SPICE) simulator, but local fluctuations in the electrical characteristics of the interconnect lines are often difficult to obtain. This is because the electrical characteristics of the interconnect lines are usually obtained by extracting the parasitics of the layout by a layout parasitics extraction (layout parasitic extraction, LPE) tool, and the layout parasitics have more components and complex distribution, so that the conventional scheme generally faces huge simulation calculation amount. In conventional schemes, only the electrical characteristics of the interconnect lines at a number of fixed process corners are typically extracted. While a fixed process angle typically characterizes the process's extreme conditions, this may oversmall the effects of local fluctuations of the interconnect lines, resulting in over-design.
Disclosure of Invention
In view of the above, embodiments of the present disclosure aim to provide a method, an electronic device, a computer readable storage medium and a program product for simulating a circuit, which may be used to avoid over-design of the circuit for process corner situations and may reflect local fluctuations of parasitic parameters in the interconnect lines.
According to a first aspect of the present disclosure, a method for simulating a circuit is provided. The method comprises the following steps: a local extraction indication is received for determining a local mismatch of neighboring interconnect lines in the circuit layout. The method further comprises the steps of: in response to receiving the local extraction indication, generating target netlist data based on an interconnection line model library, an interconnection line mismatch model set and a circuit layout, the target netlist data including a plurality of extracted parasitic parameter representations, the interconnection line model library including a plurality of representations of three-dimensional structures of a plurality of interconnection lines, the interconnection line mismatch model set including a parasitic capacitance representation between adjacent interconnection lines and a resistance representation of adjacent interconnection lines, at least one of the parasitic capacitance representation and the resistance representation being associated with a monte carlo factor. The method further comprises the steps of: and simulating the target netlist data to generate a local simulation result for the adjacent interconnection lines. By using the interconnect line model library, the set of interconnect line mismatch models, and the circuit layout in the case where the local extraction instruction is received, parasitic capacitance representations of adjacent interconnect lines and resistance representations of adjacent interconnect lines in the interconnect line mismatch model corresponding to the set of interconnect line mismatch models can be extracted. Furthermore, since the parasitic capacitance representation and the parasitic resistance representation contain monte carlo factors, the situation of local fluctuations can be characterized in the parasitic capacitance representation and the parasitic resistance representation. Compared with the conventional scheme for calculating the electrical characteristics of the interconnection line under the limit process angle, the technical scheme disclosed by the invention can not only avoid over-design caused under the limit process angle, but also embody the local fluctuation condition of the interconnection line, thereby providing moderate and correct circuit design.
In a possible implementation manner of the first aspect, the method further includes: an interconnection line mismatch model set is generated based on the process parameters for the circuit layout and the library of interconnection line models. By substituting the process parameters of the circuit layout into the corresponding interconnect model library, the set of interconnect mismatch models can be flexibly configured by the user for different process parameters, thereby providing accurate simulation of local fluctuations of parasitic parameters with respect to the interconnect.
In a possible implementation manner of the first aspect, generating the target netlist data based on the interconnect line model library, the set of interconnect line mismatch models and the circuit layout includes: comparing the circuit layout with a library of interconnect models to generate a set of structures including matching interconnect lines; and extracting the matched interconnection line structure set by using the interconnection line mismatch model set to generate target netlist data. By comparing the circuit layout with the model library of interconnect lines, the interconnect line structure including adjacent interconnect lines that need to be focused on in the circuit layout can be extracted, and the amount of computation of interconnect lines that need not to be focused on can be reduced.
In a possible implementation manner of the first aspect, generating the set of interconnect line mismatch models based on the process parameters for the circuit layout and the library of interconnect line models includes: the models in the library of interconnect line models are parsed by a field solver based on process parameters to generate a set of interconnect line mismatch models.
In one possible implementation manner of the first aspect, parsing, by the field solver, the model in the interconnect line model library based on the process parameters includes: the field solver uses boundary sources or random walk algorithms to parse the models in the library of interconnect line models based on the process parameters.
In a possible implementation manner of the first aspect, the method further includes: receiving a global extraction indication for determining interconnect lines in the circuit layout; generating global netlist data based on an interconnection line model library, a resistor-capacitor process file database and a circuit layout in response to receiving a global extraction instruction, the global netlist data including representations of electrical characteristics of interconnection lines at a plurality of process corners, the interconnection line model library including a plurality of representations of three-dimensional structures of the plurality of interconnection lines; and simulating the global netlist data to generate global simulation results for the interconnect lines at the plurality of process corners. By further setting the global extraction indication, not only a simulation of the local fluctuation situation of the parasitic parameters of the interconnect line, but also an extraction of the electrical properties of the interconnect line at conventional process corners can be provided. This may give the user more flexibility to meet different demands.
In a possible implementation manner of the first aspect, different types of parasitic capacitance representations among the parasitic capacitance representation and the resistance representation are assigned different monte carlo factors. In one possible implementation of the first aspect, the monte carlo factor comprises a gaussian factor. It was found through research that the use of gaussian factors can substantially cover the situation of local fluctuations of parasitic parameters of the interconnect lines, so that local fluctuations of parasitic parameters of the interconnect lines can be simulated in a simple manner.
According to a second aspect of the present disclosure, an electronic device is provided. The electronic device comprises a receiving unit, a generating unit and a simulation unit. The receiving unit is configured to: a local extraction indication is received for determining a local mismatch of neighboring interconnect lines in the circuit layout. The generation unit is configured to: in response to receiving the local extraction indication, generating target netlist data based on an interconnection line model library, an interconnection line mismatch model set and a circuit layout, the target netlist data including a plurality of extracted parasitic parameter representations, the interconnection line model library including a plurality of representations of three-dimensional structures of a plurality of interconnection lines, the interconnection line mismatch model set including a parasitic capacitance representation between adjacent interconnection lines and a resistance representation of adjacent interconnection lines, at least one of the parasitic capacitance representation and the resistance representation being associated with a monte carlo factor. The simulation unit is configured to: and simulating the target netlist data to generate a local simulation result for the adjacent interconnection lines. By using the library of interconnect line models, the set of interconnect line mismatch models, and the circuit layout in the case where the local extraction instruction is received, parasitic capacitance representations of adjacent interconnect lines and resistance representations of adjacent interconnect lines in the interconnect line mismatch model corresponding to the set of interconnect line mismatch models can be extracted. Furthermore, since the parasitic capacitance representation and the parasitic resistance representation contain monte carlo factors, the situation of local fluctuations can be characterized in the parasitic capacitance representation and the parasitic resistance representation. Compared with the conventional scheme for calculating the electrical characteristics of the interconnection line under the limit process angle, the technical scheme disclosed by the disclosure not only can avoid over-design caused under the limit process angle, but also can embody the local fluctuation condition of the interconnection line, thereby providing moderate and correct circuit design.
In a possible implementation manner of the second aspect, the generating unit is further configured to: an interconnection line mismatch model set is generated based on the process parameters for the circuit layout and the library of interconnection line models. By substituting the process parameters of the circuit layout into the corresponding interconnect model library, the set of interconnect mismatch models can be flexibly configured by the user for different process parameters, thereby providing accurate simulation of local fluctuations of parasitic parameters with respect to the interconnect.
In a possible implementation manner of the second aspect, the generating unit is further configured to: comparing the circuit layout with a library of interconnect models to generate a set of structures including matching interconnect lines; and extracting the matched interconnection line structure set by using the interconnection line mismatch model set to generate target netlist data. By comparing the circuit layout with the model library of interconnect lines, the interconnect line structure including adjacent interconnect lines that need to be focused on in the circuit layout can be extracted, and the amount of computation of interconnect lines that need not to be focused on can be reduced.
In a possible implementation manner of the second aspect, the generating unit is further configured to: the models in the library of interconnect line models are parsed by a field solver based on process parameters to generate a set of interconnect line mismatch models.
In a possible implementation manner of the second aspect, the generating unit is further configured to: the field solver uses boundary sources or random walk algorithms to parse the models in the library of interconnect line models based on the process parameters.
In a possible implementation manner of the second aspect, the receiving unit is further configured to: receiving a global extraction indication for determining interconnect lines in the circuit layout; the generating unit is further configured to: generating global netlist data based on an interconnection line model library, a resistor-capacitor process file database and a circuit layout in response to receiving a global extraction instruction, the global netlist data including representations of electrical characteristics of interconnection lines at a plurality of process corners, the interconnection line model library including a plurality of representations of three-dimensional structures of the plurality of interconnection lines; and the simulation unit is further configured to: the global netlist data is simulated to generate global simulation results for interconnect lines at a plurality of process corners. By further setting the global extraction indication, not only a simulation of the local fluctuation situation of the parasitic parameters of the interconnect line, but also an extraction of the electrical properties of the interconnect line at conventional process corners can be provided. This may give the user more flexibility to meet different demands.
In a possible implementation manner of the second aspect, different types of parasitic capacitance representations in the parasitic capacitance representation and the resistance representation are allocated different monte carlo factors. In one possible implementation of the second aspect, the monte carlo factor comprises a gaussian factor. It was found through research that the use of gaussian factors can substantially cover the situation of local fluctuations of parasitic parameters of the interconnect lines, so that local fluctuations of parasitic parameters of the interconnect lines can be simulated in a simple manner.
In a third aspect of the present disclosure, an electronic device is provided. The electronic device includes: at least one processor; at least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions when executed by the at least one processor cause the apparatus to perform the method according to the first aspect.
In a fourth aspect of the present disclosure, a computer-readable storage medium is provided. The computer readable storage medium stores a computer program which, when executed by a processor, implements a method according to the first aspect.
In a fifth aspect of the present disclosure, a computer program product is provided. The computer program product comprises computer executable instructions which, when executed by a processor, cause the computer to implement the method according to the first aspect.
It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.
The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals denote like or similar elements, in which:
FIG. 1 shows a schematic perspective view of a conventional path interconnect structure;
FIG. 2 shows a flow chart of a design fabrication process of an integrated circuit;
FIG. 3 illustrates a schematic flow diagram for simulating a circuit in accordance with some embodiments of the present disclosure;
FIG. 4 illustrates a parasitic distribution schematic of an interconnect line model in accordance with some embodiments of the present disclosure;
FIG. 5 illustrates a schematic diagram of parasitic distribution of another interconnect line model in accordance with further embodiments of the present disclosure;
FIG. 6 illustrates a schematic diagram of a labeled interconnect line structure, according to some embodiments of the present disclosure;
FIG. 7 shows a schematic block diagram of an example device that may be used to implement embodiments of the present disclosure; and
Fig. 8 illustrates a schematic block diagram of an electronic device, according to some embodiments of the present disclosure.
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.
In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. The term "and/or" means at least one of the two items associated therewith. For example, "a and/or B" means A, B, or a and B. Other explicit and implicit definitions are also possible below.
In the following description of the specific embodiments, some repetition is not described in detail, but it should be understood that the specific embodiments have mutual references and may be combined with each other.
As described above, local fluctuations in the electrical characteristics of the interconnect lines are often difficult to obtain. This is because the electrical characteristics of the interconnect lines are usually obtained by extracting parasitics from the layout by the LPE tool, and the layout parasitic parameters are not only more in components, but also complex in distribution, so that the conventional scheme generally faces huge simulation calculation amount. In conventional schemes, only the electrical characteristics of the interconnect lines at a number of fixed process corners are typically extracted. While a fixed process angle typically characterizes the process limitations, this may oversmall the effects of local fluctuations of the interconnect lines, resulting in over-design.
In the present disclosure, by using the interconnect line model library, the interconnect line mismatch model set, and the circuit layout in the case where the local extraction instruction is received, parasitic capacitance representations and resistance representations of adjacent interconnect line structures in the corresponding interconnect line mismatch model in the interconnect line mismatch model set can be extracted. Furthermore, since the parasitic capacitance representation and the parasitic resistance representation contain monte carlo factors, the situation of local fluctuations can be characterized in the parasitic capacitance representation and the parasitic resistance representation. Through simulation, the situation of local fluctuation of parasitic parameters possibly generated in the subsequent process can be obtained, so that the situation of local fluctuation can be adjusted in advance in the design stage. In this way, the technical solution of the present disclosure may avoid not only over-design caused at the limiting process angle, but also may embody local fluctuations of the interconnect line, compared to conventional solutions that calculate the electrical characteristics of the interconnect line at the limiting process angle, thereby providing a moderately correct circuit design.
Fig. 1 shows a schematic perspective view of a conventional path interconnect structure 100. Interconnect line structure 100 has an input inverter 102 and three fan-out inverters 104, 106, and 108. The inverters are connected through interconnection lines. In this interconnect structure, only a simplified back-end-of-line (BEOL) parasitic is considered to include 12 independent parasitic resistances and 24 independent parasitic capacitances. If each is extracted by means of Monte Carlo, there are at least 36 independent variables to be randomly calculated. For post-layout simulation, such huge simulation calculations cannot be realized at all. Only fixed process corner extraction is typically used to characterize the process limits. Extraction at a fixed process angle can overspin the effects of local fluctuations, creating an over-design.
Fig. 2 shows a flow chart of a design fabrication process 200 for an integrated circuit. The design fabrication process 200 begins with specification formulation 220. In the stage of specification 210, the functional and performance requirements that the integrated circuit needs to meet are determined. Then, in the stage of the integrated circuit design 220, the circuit design 222 is first performed by means of electronic design automation (electronic design automation, EDA) software. After the circuit is determined, the layout and wiring of the circuit cells in the integrated circuit are determined by performing the physical design 224, resulting in a circuit layout. After the circuit layout is obtained, mask fabrication 226 may be performed to obtain a mask for forming the designed circuit on the wafer. Subsequently, in a stage of fabrication 230, integrated circuits are formed on the wafer by photolithography, etching, ion implantation, thin film deposition, polishing, and the like. In the stage of packaging 240, the wafer is cut to obtain a die, and the die is packaged by processes such as adhesion, soldering, and die sealing to obtain a chip. The resulting chips are tested in a stage of testing 250 to ensure that the performance of the finished chips meets the requirements determined in specification 220. Finally, the chips 260 that are under test may be delivered to the customer.
The layout design 224 mainly includes steps of division, layout planning, layout, clock tree synthesis, wiring, and the like, and involves evaluation indexes such as routability, time delay, power consumption, area, manufacturability, and the like. In the layout design 224, it is necessary to evaluate local fluctuations of parasitic parameters of the interconnect lines (especially adjacent interconnect lines).
Fig. 3 illustrates a schematic flow diagram of a method 300 for simulating a circuit according to some embodiments of the disclosure. At 302, an electronic device, such as a computer, receives input from a user, i.e., a local extraction indication for determining a local mismatch of adjacent interconnect lines in a circuit layout. In one embodiment, a computer program, such as EDA software, may provide a plurality of user options on an interface, such as a global mode option and a local extraction option. In the case where the user selects a local extraction option for a local mismatch, the user actually inputs a local extraction indication to the electronic device for determining the local mismatch of neighboring interconnect lines in the circuit layout. In another embodiment, the user may also cause the electronic device to perform the method 300 by entering commands. The present disclosure is not limited in this regard. It is understood that the method 300 shown in fig. 3 may be performed by an electronic device having computing capabilities, such as a personal computer, workstation, server, or the like. The present disclosure is not limited in this regard.
At 304, the electronic device generates target netlist data based on the library of interconnect line models, the set of interconnect line mismatch models, and the circuit layout in response to receiving the local extraction instructions. In one embodiment, the model library of interconnect lines includes a plurality of representations of three-dimensional structures of a plurality of interconnect lines. For example, the interconnect model library may include a pizza (pizza) structure in which two metal interconnect lines overlap or a sandwich structure in which three metal interconnect lines overlap, etc. The EDA software may include a number of typical interconnect line model structures. In addition, the user can also customize the interconnect line model structure according to the requirements of the self circuit design to form an interconnect line model library or supplement a default interconnect line model library in EDA software.
In one embodiment, the electronic device may be configured to call a field solver of the EDA tool. The field solver constructs a set of interconnect line mismatch models based on a boundary element or random walk (floating random walk) algorithm and relying on a large number of built-in interconnect line model structures (e.g., interconnect line model structures from an interconnect line model library) of EDA tools, substituting various process parameters from an interconnect line process file into the interconnect line model structures for simulation. The process parameters include, for example, the width and thickness of the interconnect line conductors, etc., the thickness and dielectric constant of the dielectric layer between or near the interconnect lines, etc. It will be appreciated that other interconnect model analysis tools and other algorithms may be used. The set of interconnect line mismatch models includes a representation of parasitic capacitance between adjacent interconnect lines and a representation of resistance of adjacent interconnect lines. At least one of the parasitic capacitance representation and the resistance representation is associated with a monte carlo factor.
Fig. 4 illustrates a parasitic distribution schematic of an interconnect line model 400, according to some embodiments of the present disclosure. Interconnect line model 400 is a conventional sandwich-like cross-structure in which parasitic capacitance and resistance of adjacent interconnect lines are defined. The sandwich cross structure comprises a first layer of metal interconnection lines M N+1 402. A plurality of second-layer metal interconnection lines M N 404-2, 404-4, 404-6 (hereinafter referred to individually or collectively as 404) and a third layer metal interconnect line M N-1 406, where M N+1 402 and M N-1 406 and M N 404 are orthogonal to each other. M is M N-1 406 and M N The thickness of the dielectric layer between 404 is denoted by IMDBt, and M N+1 402 and M N The thickness of the dielectric layer between 404 is denoted IMDTt. The width of the interconnect line is denoted by Mw, and the thickness of the interconnect line is denoted by Mt. The spacing between adjacent interconnect lines in the same layer is denoted by P-Mw. In the sandwich structure, the interconnection line M N 404-4 and M N+1 402 have two fringe parasitic capacitances, denoted Cft, between them, and a vertical cover capacitance, denoted Cat. Interconnect line M N 404-4 and M N-1 406 have two fringe parasitic capacitances denoted by Cfb and a vertical cover capacitance denoted by Cab. Further, interconnect line M N 404-2 and interconnect line M N 404-4 have a common layer parasitic coupling capacitance denoted Cc therebetween. Similarly, interconnect line M N 404-6 and interconnect line M N 404-4 have a common layer parasitic coupling capacitance denoted Cc therebetween.
The parasitic capacitance and resistance of the sandwich-type cross structure in fig. 4 can thus be represented by the following equations (1) - (7).
Cc＝f(Mw,P-Mw,Mt)*L (1)
Cab＝f(Mw,IMDBt)*L (2)
Cat＝f(Mw,IMDTt)*L (3)
Cfb＝f(Mt,P-Mw,IMDBt)*L (4)
Cft＝f(Mt,P-Mw,IMDTt)*L (5)
Ctotal＝2*Cc+Cab+Cat+2*Cfb+2*Cft (6)
R＝Rho*L/(Mw*Mt) (7)
Where f () represents a function, L represents an interconnect line length, ctotal represents a total parasitic capacitance, and Rho represents a resistivity.
To account for localized fluctuations caused by the process, in some embodiments of the present disclosure, a Monte Carlo factor, such as a Gaussian factor, is added in equations (1) - (7). The formulas (1) to (7) can thus be rewritten as the following formulas (1A) to (7A).
Cc＝f(Mw*a0,P-Mw*a0,Mt*a1)*L (1A)
Cab＝f(Mw*a0,IMDBt*a2)*L (2A)
Cat＝f(Mw*a0,IMDTt*a3)*L (3A)
Cfb＝f(Mt*a1,P-Mw*a0,IMDBt*a2)*L (4A)
Cft＝f(Mt*a1,P-Mw*a0,IMDTt*a3)*L (5A)
Ctotal＝2*Cc+Cab+Cat+2*Cfb+2*Cft (6A)
R＝Rho*a4*L/(Mw*a0*Mt*a1) (7A)
Wherein a0-a4 represent different monte carlo factors, such as gaussian factors. It will be appreciated that since Mw and P-Mw represent the width and pitch width of the interconnect line, both can be considered the same type of parameter and can be represented using the same Gaussian factor a 0. In other embodiments, mw and P-Mw may be assigned different Monte Carlo factors. Further, since the interconnect line length L is generally large compared to the width and thickness, local fluctuations have limited influence thereon, and thus the interconnect line length may not be given a monte carlo factor. It is understood that different types of parasitic capacitance representations, such as combinations of different monte carlo factors, are assigned to different ones of the parasitic capacitance representations and the resistance representations. In particular, different types of process parameters such as interconnect line width, thickness of dielectric layer, etc. in the parasitic capacitance representation and the resistance representation may be given different monte carlo factors. Where different materials are used to form the interconnect lines, the resistivity of the different materials may also be given different Monte Carlo factors.
Fig. 5 illustrates a schematic diagram of parasitic distribution of an interconnect line model 500 in accordance with further embodiments of the present disclosure. The interconnect line model 500 is a multi-layered vertical structure including a first layer of metal interconnect lines M N+1 502. A plurality of second-layer metal interconnection lines M N 504-2, 504-4, 504-6 (hereinafter referred to individually or collectively as 504), a plurality of third layer metal interconnect lines M N-1 506-2, 506-4 (hereinafter referred to individually or collectively as 506) and fourth-layer metal interconnect line M N-2 508, wherein M N+1 502 and M N-2 508 and M N 504 and M N-1 506 are orthogonal to each other. M is M N-1 506 and M N The thickness of the dielectric layer between 504 is denoted by IMDBt, M N+1 502 and M N The thickness of the dielectric layer between 504 is denoted IMDTt, and M N-2 508 and M N-1 The thickness of the dielectric layer between 506 is denoted IMDTtx. The width of the interconnect line is represented by Mw, M N Thickness of interconnect lines in layersThe degree is denoted by Mt, and M N-1 The thickness of the interconnect lines in the layers is denoted Mtx. M is M N The spacing between adjacent interconnect lines in (a) is represented by P-Mw, and M N-1 The spacing between adjacent interconnect lines in a layer is denoted by Mwx. In the multilayer vertical structure, an interconnect line M N 504-4 and M N+1 502 have two fringe parasitic capacitances, denoted Cft, between them, and a vertical cover capacitance, denoted Cat. Interconnect line M N 504-4 and M N-1 506 have two fringe parasitic capacitances denoted Cfb therebetween. Further, interconnect line M N 504-4 and M N-2 508 have two fringe parasitic capacitances denoted by Cfbx and a vertical cover capacitance denoted by Cab. Interconnect line M N 504-2 and interconnect line M N 504-4 have a common layer parasitic coupling capacitance denoted Cc. Similarly, interconnect line M N 504-6 and interconnect line M N 504-4 have a common layer parasitic coupling capacitance denoted Cc.
The parasitic capacitance and resistance of the multilayer vertical structure in fig. 5 can thus be represented by the following formulas (8) - (15).
Cc＝f(Mw,P-Mw,Mt)*L (8)
Cab＝f(Mw,IMDBt+Mtx+IMDBtx)*L (9)
Cat＝f(Mw,IMDTt)*L (10)
Cfb＝f(Mt,P-Mw,IMDBt,Mwx)*L (11)
Cft＝f(Mt,P-Mw,IMDTt)*L (12)
Cfbx＝f(Mt,P-Mw,IMDBt+Mtx+IMDBtx) (13)
Ctotal＝2*Cc+Cab+Cat+2*Cfb+2*Cft+2*Cfbx (14)
R＝Rho*L/(Mw*Mt) (15)
Where L represents the interconnect length, ctotal represents the total parasitic capacitance, and Rho represents the resistivity.
To account for localized fluctuations caused by the process, in some embodiments of the present disclosure, a Monte Carlo factor, such as a Gaussian factor, is added in equations (8) - (15). The formulas (8) to (15) can thus be rewritten as the following formulas (8A) to (15A).
Cc＝f(Mw*a0,P-Mw*a0,Mt*a1)*L (8A)
Cab＝f(Mw*a0,IMDBt*a2+Mtx*a3+IMDBtx*a4)*L (9A)
Cat＝f(Mw*a0,IMDTt*a5)*L (10A)
Cfb＝f(Mt*a1,P-Mw*a0,IMDBt*a2,Mwx*a6)*L (11A)
Cft＝f(Mt*a1,P-Mw*a0,IMDTt*a3)*L (12A)
Cfbx＝f(Mt*a1,P-Mw*a0,IMDBt*a2+Mtx*a3+IMDBtx*a4) (13A)
Ctotal＝2*Cc+Cab+Cat+2*Cfb+2*Cft+2*Cfbx (14A)
R＝Rho*a7*L/(Mw*a0*Mt*a1) (15A)
Wherein a0-a7 represent different monte carlo factors, such as gaussian factors. It will be appreciated that since Mw and P-Mw represent the width and pitch width of the interconnect line, both can be considered the same type of parameter and can be represented using the same Gaussian factor a 0. In other embodiments, mw and P-Mw may be assigned different Monte Carlo factors. Further, since the interconnect line length L is generally large compared to the width and thickness, local fluctuations have limited influence thereon, and thus the interconnect line length may not be given a monte carlo factor. It is understood that different types of parasitic capacitance representations, such as combinations of different monte carlo factors, are assigned to different ones of the parasitic capacitance representations and the resistance representations. In particular, different types of process parameters such as interconnect line width, thickness of dielectric layer, etc. in the parasitic capacitance representation and the resistance representation may be given different monte carlo factors. Where different materials are used to form the interconnect lines, the resistivity of the different materials may also be assigned different Monte Carlo factors.
Examples of interconnect line mismatch models for generating local fluctuations in interconnect line parasitic parameters are described above for some embodiments of the present disclosure, however the present disclosure is not limited thereto. In some embodiments, a resistive-capacitive (RC) process file database may also be generated by the field solver based on the process parameters and the interconnect model library using a boundary element or random walk method. This may provide a basis for subsequent global simulation results, and will be described below.
The target netlist data includes a plurality of extracted parasitic parametric representations. Fig. 6 illustrates a schematic diagram of a tagged interconnect line structure 600, according to some embodiments of the present disclosure. Interconnect line structure 600 corresponds to interconnect line model 400 of fig. 4, and thus aspects described with respect to interconnect line model 400 may be selectively applied to interconnect line structure 600. Interconnect line junction 600 has parasitic capacitance Cc of tag a to tag C, parasitic capacitance cab+2x2cft of tag a to tag D, parasitic capacitance cab+2xcft of tag a to tag E, and resistance R of interconnect line tag a to tag a-1. One example of netlist data for this interconnect structure 600 may be shown as follows:
C1A C f(Mw*a0,P-Mw*a0,Mt*a1)*L
C2A B f(Mw*a0,P-Mw*a0,Mt*a1)*L
C3A D f(Mw*a0,IMDTt*a3)*L+2*f(Mt*a1,P-Mw*a0,IMDTt*a3)*L
C4A E f(Mw*a0,IMDBt*a2)*L+2*f(Mt*a1,P-Mw*a0,IMDBt*a2)*L
R1A A-1Rho*a4*L/(Mw*a0*Mt*a1)
The target netlist data thus illustratively includes extracted parasitic parametric representations C1, C2, C3, C4, and R1. The target netlist data comprises an interconnection line adaptation model for adapting parasitic parameters of the interconnection lines, can be used for Monte Carlo simulation, and characterizes local fluctuation effects of the interconnection lines. It will be appreciated that the interconnect line model 500 of FIG. 5 may also be used to obtain similar target netlist data to represent, and may also be used for Monte Carlo simulation.
In one embodiment, the electronic device may generate a set of interconnect line mismatch models based on the process parameters for the circuit layout and the library of interconnect line models. For example, the electronic device may compare the circuit layout to a library of interconnect model to generate a set of structures including matching interconnect lines. The set of matched interconnect line structures may comprise interconnect line structures in the circuit layout, in particular the interconnect line layout, that correspond or match at least one model in the library of interconnect line models. By comparing the circuit layout with the model library of interconnect lines, the interconnect line structure including adjacent interconnect lines that need to be focused on in the circuit layout can be extracted, and the amount of computation of interconnect lines that need not to be focused on can be reduced. The electronic device then extracts the set of matching interconnect line structures using the set of interconnect line mismatch models to generate target netlist data, such as the target netlist data shown above for interconnect line structure 600 of fig. 6. By substituting the process parameters of the circuit layout into the corresponding interconnect model library, the set of interconnect mismatch models can be flexibly configured by the user for different process parameters, thereby providing accurate simulation of local fluctuations of parasitic parameters with respect to the interconnect.
At 306, the electronic device simulates the target netlist data to generate partial simulation results for adjacent interconnect lines. By using the interconnect line model library, the set of interconnect line mismatch models, and the circuit layout in the case where the local extraction instruction is received, parasitic capacitance representations of adjacent interconnect lines and resistance representations of adjacent interconnect lines in the interconnect line mismatch model corresponding to the set of interconnect line mismatch models can be extracted. Furthermore, since the parasitic capacitance representation and the parasitic resistance representation contain monte carlo factors, the situation of local fluctuations can be characterized in the parasitic capacitance representation and the parasitic resistance representation. Compared with the conventional scheme for calculating the electrical characteristics of the interconnection line under the limit process angle, the technical scheme disclosed by the invention can not only avoid over-design caused under the limit process angle, but also embody the local fluctuation condition of the interconnection line, thereby providing moderate and correct circuit design.
In other embodiments, if the user inputs a global extraction instruction or selects a global extraction option, the electronic device may invoke the RC process file database and may generate global netlist data based on the interconnect model library, the resistor-capacitor process file database, and the circuit layout in a similar manner as the target netlist data was generated above. The global netlist data includes representations of electrical properties of interconnect lines at a plurality of process corners, and the model library of interconnect lines includes a plurality of representations of three-dimensional structures of the plurality of interconnect lines; and simulating the global netlist data to generate global simulation results for the interconnect lines at the plurality of process corners. By further setting the global extraction indication, not only a simulation of the local fluctuation situation of the parasitic parameters of the interconnect line, but also an extraction of the electrical properties of the interconnect line at conventional process corners can be provided. This may give the user more flexibility to meet different demands.
FIG. 7 shows a schematic block diagram of an example device that may be used to implement embodiments of the present disclosure. As shown, the device 700 includes a computing unit 701 that may perform various suitable actions and processes in accordance with computer program instructions stored in Random Access Memory (RAM) and/or Read Only Memory (ROM) 702 or loaded from storage unit 708 into RAM 703 and/or ROM 702. In the RAM 703 and/or the ROM 702, various programs and data required for the operation of the device 700 may also be stored. The computing unit 701 and the RAM 703 and/or the ROM 702 are connected to each other by a bus 704. An input/output (I/O) interface 705 is also connected to bus 704.
Various components in device 700 are connected to I/O interface 705, including: an input unit 706 such as a keyboard, a mouse, etc.; an output unit 707 such as various types of displays, speakers, and the like; a storage unit 708 such as a magnetic disk, an optical disk, or the like; and a communication unit 709 such as a network card, modem, wireless communication transceiver, etc. The communication unit 709 allows the device 700 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.
The computing unit 701 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 701 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 701 performs the various methods and processes described above, such as method 400. For example, in some embodiments, the method 300 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 708. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 700 via RAM and/or ROM and/or communication unit 709. One or more of the steps of the method 300 described above may be performed when a computer program is loaded into RAM and/or ROM and executed by the computing unit 701. Alternatively, in other embodiments, the computing unit 701 may be configured to perform the method 300 by any other suitable means (e.g., by means of firmware).
Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
Fig. 8 illustrates a schematic block diagram of an electronic device 800, according to some embodiments of the present disclosure. Fig. 6 illustrates a block diagram of an example electronic device 600 for designing a circuit, according to an embodiment of the disclosure. The electronic device 800 may include a plurality of modules for performing corresponding steps in the method 300 as discussed in fig. 3. As shown in fig. 8, the electronic device 800 includes a receiving unit 802, a generating unit 804, and an simulating unit 806. The receiving unit 802 is configured to: a local extraction indication is received for determining a local mismatch of neighboring interconnect lines in the circuit layout. The generating unit 804 is configured to: in response to receiving the local extraction indication, generating target netlist data based on an interconnection line model library, an interconnection line mismatch model set and a circuit layout, the target netlist data including a plurality of extracted parasitic parameter representations, the interconnection line model library including a plurality of representations of three-dimensional structures of a plurality of interconnection lines, the interconnection line mismatch model set including a parasitic capacitance representation between adjacent interconnection lines and a resistance representation of adjacent interconnection lines, at least one of the parasitic capacitance representation and the resistance representation being associated with a monte carlo factor. The simulation unit 806 is configured to: and simulating the target netlist data to generate a local simulation result for the adjacent interconnection lines. By using the library of interconnect line models, the set of interconnect line mismatch models, and the circuit layout in the case where the local extraction instruction is received, parasitic capacitance representations of adjacent interconnect lines and resistance representations of adjacent interconnect lines in the interconnect line mismatch model corresponding to the set of interconnect line mismatch models can be extracted. Furthermore, since the parasitic capacitance representation and the parasitic resistance representation contain monte carlo factors, the situation of local fluctuations can be characterized in the parasitic capacitance representation and the parasitic resistance representation. Compared with the conventional scheme for calculating the electrical characteristics of the interconnection line under the limit process angle, the technical scheme disclosed by the disclosure not only can avoid over-design caused under the limit process angle, but also can embody the local fluctuation condition of the interconnection line, thereby providing moderate and correct circuit design.
In some embodiments, the generating unit 804 is further configured to: an interconnection line mismatch model set is generated based on the process parameters for the circuit layout and the library of interconnection line models. By substituting the process parameters of the circuit layout into the corresponding interconnect model library, the set of interconnect mismatch models can be flexibly configured by the user for different process parameters, thereby providing accurate simulation of local fluctuations of parasitic parameters with respect to the interconnect.
In some embodiments, the generating unit 804 is further configured to: comparing the circuit layout with a library of interconnect models to generate a set of structures including matching interconnect lines; and extracting the matched interconnection line structure set by using the interconnection line mismatch model set to generate target netlist data. By comparing the circuit layout with the model library of interconnect lines, the interconnect line structure including adjacent interconnect lines that need to be focused on in the circuit layout can be extracted, and the amount of computation of interconnect lines that need not to be focused on can be reduced.
In some embodiments, the generating unit 804 is further configured to: the models in the library of interconnect line models are parsed by a field solver based on process parameters to generate a set of interconnect line mismatch models.
In some embodiments, the generating unit 804 is further configured to: the field solver uses boundary sources or random walk algorithms to parse the models in the library of interconnect line models based on the process parameters.
In some embodiments, the receiving unit 802 is further configured to: receiving a global extraction indication for determining interconnect lines in the circuit layout; the generating unit 804 is further configured to: generating global netlist data based on an interconnection line model library, a resistor-capacitor process file database and a circuit layout in response to receiving a global extraction instruction, the global netlist data including representations of electrical characteristics of interconnection lines at a plurality of process corners, the interconnection line model library including a plurality of representations of three-dimensional structures of the plurality of interconnection lines; and the simulation unit 806 is further configured to: the global netlist data is simulated to generate global simulation results for interconnect lines at a plurality of process corners. By further setting the global extraction indication, not only a simulation of the local fluctuation situation of the parasitic parameters of the interconnect line, but also an extraction of the electrical properties of the interconnect line at conventional process corners can be provided. This may give the user more flexibility to meet different demands.
In some embodiments, different types of parasitic capacitance representations of the parasitic capacitance representation and the resistance representation are assigned different monte carlo factors. In some embodiments, the monte carlo factor comprises a gaussian factor. It was found through research that the use of gaussian factors can substantially cover the situation of local fluctuations of parasitic parameters of the interconnect lines, so that local fluctuations of parasitic parameters of the interconnect lines can be simulated in a simple manner.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.
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