CN116940120B

CN116940120B - NOR flash memory with pairing structure and manufacturing method thereof

Info

Publication number: CN116940120B
Application number: CN202311195869.1A
Authority: CN
Inventors: 金波
Original assignee: Shanghai Lingnai Semiconductor Technology Co ltd
Current assignee: Shanghai Lingnai Semiconductor Technology Co ltd
Priority date: 2023-09-18
Filing date: 2023-09-18
Publication date: 2024-01-05
Anticipated expiration: 2043-09-18
Also published as: CN116940120A

Abstract

The invention provides a NOR flash memory with a pairing structure and a manufacturing method thereof. The manufacturing method of the NOR flash memory with the pairing structure comprises the following steps: providing a substrate, wherein the substrate comprises an isolation structure and an active area defined by the isolation structure; forming a plurality of word line grooves in a substrate, wherein each word line groove comprises a first groove and a second groove which are mutually communicated, the first groove is embedded in the substrate of the active region, and the second groove is embedded in the isolation structure; forming a plurality of charge trap structures on the substrate and forming a word line in each word line trench, one charge trap structure conformally covering the inner surface of one first trench, the word line covering at least a portion of the charge trap structures in the first trench; and forming a plurality of bit lines over the substrate. Therefore, word lines of the NOR flash memory with the group pair structure are embedded in the substrate, so that the area of a storage unit of the NOR flash memory can be reduced, and the storage density of the NOR flash memory can be improved. The NOR flash memory of the pair structure can be manufactured by the manufacturing method.

Description

NOR flash memory with pairing structure and manufacturing method thereof

Technical Field

The invention relates to the technical field of memories, in particular to a NOR flash memory with a pairing structure and a manufacturing method thereof.

Background

Flash Memory (Flash Memory) is a Nonvolatile (or non-volatile) semiconductor Memory chip that can retain stored data information in the event of a power failure. In addition, the flash memory has the advantages of small volume, low power consumption and difficult physical damage, so that the flash memory is widely applied.

With the development of semiconductor manufacturing processes, the capacity demand of NOR flash memory is increasing. How to reduce the area of the memory cells of NOR flash memory and to increase the memory density of NOR flash memory is a problem that the industry needs to continuously improve.

Disclosure of Invention

One of the objectives of the present invention is to provide a NOR flash memory with a pair structure and a method for manufacturing the NOR flash memory, which can reduce the area of the memory cells of the NOR flash memory and increase the memory density of the NOR flash memory.

In order to achieve the above object, an aspect of the present invention provides a method for manufacturing a NOR flash memory of a pair-wise structure. The manufacturing method of the NOR flash memory with the pairing structure comprises the following steps: providing a substrate, wherein the substrate comprises an isolation structure and an active region defined by the isolation structure; forming a plurality of word line grooves in the substrate, wherein each word line groove comprises a first groove and a second groove which are mutually communicated, the first groove is embedded in the substrate of the active region, and the second groove is embedded in the isolation structure; forming a plurality of charge trap structures on the substrate and forming a word line within each of the word line trenches; one of the charge trap structures conformally covers an inner surface of one of the first trenches, and the word line covers at least a portion of the charge trap structure within the first trench; forming a plurality of bit lines above the substrate, wherein every two adjacent bit lines are in a group; the NOR flash memory of the group pair structure comprises a plurality of group pair memory units, each group pair memory unit comprises two memory tubes which are adjacently arranged in the active area, each memory tube comprises a first groove and a charge trap structure in the first groove, and the two memory tubes of the group pair memory units are electrically connected through the active area below the charge trap structures of the two memory tubes; for two storage tubes of the same pair of storage units, the first sides of the two corresponding first grooves are close to each other, the second sides of the two corresponding first grooves are far away from each other, and the active areas of the second sides of the two corresponding first grooves are respectively and electrically connected with one of a group of bit lines; when data writing or data reading is performed on one storage tube of the group pair storage units, the other storage tube is used as a selection tube.

Optionally, the substrate includes a plurality of the active regions, the active regions being elongated in a first direction, the word line trenches being elongated in a second direction, each of the word line trenches crossing the plurality of active regions.

Optionally, the method of forming a plurality of charge trap structures on the substrate and forming a word line in each of the word line trenches includes: forming a charge trap layer on the substrate, the charge trap layer covering the active region and the isolation structure; removing the charge trap layer on the isolation structure; forming a word line material layer on the substrate, the word line material layer covering the substrate and filling up the plurality of first trenches; and removing the word line material layer and the charge trap layer on the top surface of the substrate, and reserving the word line material layer and the charge trap layer in the first groove, wherein the word line material layer reserved in the first groove is used as part of the word line, and the charge trap layer reserved in the first groove is used as the charge trap structure.

Optionally, after forming a plurality of charge trap structures on the substrate and forming a word line in each of the word line trenches, before forming a plurality of bit lines on the substrate, the method further comprises: forming a plurality of contact plugs on the substrate; wherein the active regions of the second sides of the two first trenches of the group of memory cells are electrically connected with the corresponding bit lines through the contact plugs.

Another aspect of the present invention provides a NOR flash memory of a pair-wise architecture. The NOR flash memory of the pair structure includes: a substrate comprising an isolation structure and an active region defined by the isolation structure; each word line groove comprises a first groove and a second groove which are mutually communicated, the first groove is embedded in the substrate of the active area, and the second groove is embedded in the isolation structure; a plurality of charge trap structures, each of the charge trap structures conformally covering an inner surface of one of the first trenches; a plurality of word lines, each of the word lines filling one of the word line trenches and covering at least a portion of the charge trapping structure in the first trench; and a plurality of bit lines, each two adjacent bit lines being a group; the NOR flash memory of the group pair structure comprises a plurality of group pair memory units, each group pair memory unit comprises two memory tubes which are adjacently arranged in the active area, each memory tube comprises a first groove and a charge trap structure in the first groove, and the two memory tubes of the group pair memory units are electrically connected through the active area below the charge trap structures of the two memory tubes; for two storage tubes of the same pair of storage units, the first sides of the two corresponding first grooves are close to each other, the second sides of the two corresponding first grooves are far away from each other, and the active areas of the second sides of the two corresponding first grooves are respectively and electrically connected with one of a group of bit lines; when data writing or data reading is performed on one storage tube of the group pair storage units, the other storage tube is used as a selection tube.

Optionally, the substrate includes a plurality of the active regions, each of the active regions being elongated in a first direction, the word line trenches being elongated in a second direction, the second direction being perpendicular to the first direction, each of the word line trenches crossing the plurality of active regions; each of the word line trenches includes a plurality of first trenches and a plurality of second trenches, the first trenches and the second trenches being arranged at intervals in the second direction.

Optionally, the storage tubes on the same active area are the same row of storage tubes, and the group pair storage units on the same active area are the same row of group pair storage units; the group of memory cells in the same column are correspondingly connected with the same group of bit lines.

Optionally, a well region is formed on the top of the substrate, the active region is located in the well region, and the depth of the well region is greater than the depth of the first trench and the depth of the isolation structure.

Optionally, the charge trap structure includes an oxide layer, a nitride layer, and an oxide layer sequentially stacked from bottom to top.

Optionally, the channel of the storage tube is a PN junction-free channel.

According to the NOR flash memory with the pairing structure and the manufacturing method thereof, the word lines are embedded in the word line grooves of the substrate, namely, the word lines are embedded in the substrate, so that side walls for isolation are not required to be arranged between the word lines, the word lines do not need to be tiled above the substrate in the same plane with the bit lines, the area of a storage unit of the flash memory can be greatly reduced, and the storage density of the NOR flash memory is improved; the storage tube comprises the first groove and the charge trap structure covering the inner surface of the first groove, so that the channel of the storage tube is longer, and the electric performance of the storage tube is improved; in addition, each group pair memory cell comprises two memory tubes of adjacent arranged group pairs in the active area, when one memory tube of the group pair memory cell is used for writing data or reading data, the other memory tube is used as a selection tube, so that the two memory tubes of the same group pair memory cell can be used for independently storing binary data, 1T memory density can be realized, a special selection tube is not required to be arranged, the area of the memory cell can be reduced, the memory density of the flash memory is improved, and when the group pair memory cell is used for writing data, the two bit lines of the same group can be applied with voltages of the same size, and the power consumption during data writing operation can be further reduced.

Drawings

Fig. 1 is a flowchart of a method for manufacturing a NOR flash memory with a pair structure according to an embodiment of the invention.

Fig. 2 to 10 are schematic block diagrams illustrating a method for manufacturing a pair-wise NOR flash memory according to an embodiment of the invention.

FIG. 11 is a layout diagram of a pair-wise structured NOR flash memory according to an embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view of a pair-wise structured NOR flash memory according to an embodiment of the present invention.

Reference numerals illustrate: 100-pairing memory cells; 101-a substrate; 102-an active region; 103-isolation structures; 104-a first trench; 105-a second trench; 106 a charge trap layer; 107-word line material layers; 107 a-word lines; 108-a charge trap structure; 109-lead-out area; 110-a contact plug; 111-bit lines.

Detailed Description

In order to reduce the area of a memory cell of the NOR flash memory and improve the memory density of the NOR flash memory, the invention provides a NOR flash memory with a pair structure and a manufacturing method thereof.

The NOR flash memory with the group pair structure and the manufacturing method thereof according to the present invention are described in further detail below with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

Fig. 1 is a flowchart of a method for manufacturing a NOR flash memory with a pair structure according to an embodiment of the invention. As shown in fig. 1, the method for manufacturing the NOR flash memory with the pairing structure provided in this embodiment includes:

step S1, providing a substrate, wherein the substrate comprises an isolation structure and an active area defined by the isolation structure;

step S2, forming a plurality of word line grooves in the substrate, wherein each word line groove comprises a first groove and a second groove which are mutually communicated, the first groove is embedded in the substrate of the active region, and the second groove is embedded in the isolation structure;

step S3, forming a plurality of charge trap structures on the substrate and forming word lines in each word line groove; one of the charge trap structures conformally covers an inner surface of one of the first trenches, and the word line covers at least a portion of the charge trap structure within the first trench; and

s4, forming a plurality of bit lines above the substrate, wherein every two adjacent bit lines are in a group; the NOR flash memory of the group pair structure comprises a plurality of group pair memory units, each group pair memory unit comprises two memory tubes which are adjacently arranged in the active area, each memory tube comprises a first groove and a charge trap structure in the first groove, and the two memory tubes of the group pair memory units are electrically connected through the active area below the charge trap structures of the two memory tubes; for two storage tubes of the same pair of storage units, the first sides of the two corresponding first grooves are close to each other, the second sides of the two corresponding first grooves are far away from each other, and the active areas of the second sides of the two corresponding first grooves are respectively and electrically connected with one of a group of bit lines; when data writing or data reading is performed on one storage tube of the group pair storage units, the other storage tube is used as a selection tube.

Fig. 2 to 10 are schematic views of a sub-step structure of a method for manufacturing a NOR flash memory with a pair structure according to an embodiment of the invention, wherein fig. 2, 4, 6 and 9 are schematic plan views, and fig. 3, 5, 7, 8 and 10 are schematic cross-sectional views. The method for manufacturing the NOR flash memory of the pair-wise structure of the present embodiment is described below with reference to fig. 2 to 10.

Fig. 2 is a schematic plan view of a substrate, and fig. 3 is a schematic cross-sectional view of the substrate along the dotted line of fig. 2. Referring to fig. 2 and 3, the substrate 101 may be provided to include an isolation structure 103 and an Active Area 102 (Active Area) defined by the isolation structure 103.

In this embodiment, the substrate 101 includes a plurality of active regions 102, and the plurality of active regions 102 are elongated along a first direction (X direction). The isolation structure 103 may be a Shallow Trench Isolation (STI) structure, but is not limited thereto.

In this embodiment, a well region may be formed on top of the substrate 101, and the plurality of active regions 102 may be located in the well region, which may be formed by ion implantation of the substrate 101 before forming the isolation structure 103. The well region may be a P-type well region (Pwell), for example. In other embodiments, the substrate 101 may be a P-type substrate, and the entire substrate is a P-type well region, and the well region is not required to be formed by an ion implantation process.

Fig. 4 is a schematic plan view of the substrate after forming the word line trench, and fig. 5 is a schematic cross-sectional view of the substrate along the dotted line of fig. 4. Referring to fig. 4 and 5, a plurality of word line trenches are formed in the substrate 101, each of the word line trenches including a first trench 104 and a second trench 105 that are mutually penetrated, i.e., each of the word line trenches is composed of the first trench 104 and the second trench 105 that are mutually penetrated, the first trench 104 is embedded in the substrate of the active region 102, and the second trench 105 is embedded in the isolation structure 103.

In this embodiment, the depth of the first trench 104 and the second trench 105 is smaller than the depth of the isolation structure 103. The depth of the isolation structure 103 is less than the depth of the well region.

Illustratively, the wordline trenches are elongated in a second direction (i.e., the Y-direction) that is perpendicular to the first direction. In this embodiment, the first direction is the column direction, and the second direction is the row direction.

Referring to fig. 4, each of the word line trenches spans the plurality of active regions 102, and each of the word line trenches includes a plurality of first trenches 104 and a plurality of second trenches 105 of the same row, the first trenches 104 and the second trenches 105 of the same word line trench being spaced apart in the second direction.

Fig. 9 is a schematic plan view of the substrate after forming word lines over the substrate, and fig. 10 is a schematic cross-sectional view of the substrate along the dashed line in fig. 9. Referring to fig. 9 and 10, a plurality of charge trap structures 108 are formed on the substrate 101 and a word line 107a is formed in each word line trench; a charge trapping structure 108 conformally covers an inner surface of a first trench 104 and a word line 107a covers at least a portion of the charge trapping structure 108 within the first trench 104.

Fig. 6 is a schematic plan view of a substrate after a charge trapping layer is formed thereon, and fig. 7 is a schematic cross-sectional view of the substrate along the dotted line of fig. 6. FIG. 8 is a schematic cross-sectional view of a substrate after a word line material layer is formed thereon. For example, a method of forming a plurality of charge trapping structures 108 on a substrate 101 and forming a word line 107a within each word line trench may include: forming a charge trap layer 106 on the substrate 101, the charge trap layer 106 covering the active region 102 and the isolation structure 103; as shown in fig. 6 and 7, the charge trap layer 106 on the isolation structure 103 is removed and the charge trap layer 106 on the active region 102 is left; as shown in fig. 8, a word line material layer 107 is formed on the substrate 101, the word line material layer 107 covering the substrate 101 and filling up the plurality of first trenches 104; as shown in fig. 9 and 10, the word line material layer 107 and the charge trap layer 106 on the top surface of the substrate 101 are removed by Chemical Mechanical Polishing (CMP) or the like, the word line material layer 107 and the charge trap layer 106 in the first trench 104 are reserved, the word line material layer 107 in the second trench 105 is reserved, the word line material layer 107 in the first trench 104 and the second trench 105 is used as a word line 107a, and the charge trap layer 106 in the first trench 104 is used as a charge trap structure 108.

In this embodiment, the charge trap layer 106 may include an oxide layer, a nitride layer, and an oxide layer sequentially stacked on the substrate 101. The oxide layer may be a silicon oxide layer, and the nitride layer may be a silicon nitride layer, but is not limited thereto.

In this embodiment, the material of the word line material layer 107 may be polysilicon. In other embodiments, the word line material layer 107 may also be a metal material layer.

Referring to fig. 10, in the present embodiment, the word line 107a covers the portion of the corresponding charge trapping structure 108 located at the bottom of the first trench 104, and covers the inner surface of the charge trapping structure 108 located in the first trench 104, and the top surface of the charge trapping structure 108 is exposed, but is not limited thereto.

FIG. 11 is a layout diagram of a pair-wise structured NOR flash memory according to an embodiment of the present invention. FIG. 12 is a schematic cross-sectional view of a pair-wise structured NOR flash memory according to an embodiment of the present invention. Fig. 12 is a cross-sectional view taken along the broken line of fig. 11.

Referring to fig. 11 and 12, a plurality of bit lines 111 (BL) are formed over the substrate 101, each adjacent two of the bit lines 111 are grouped, and the NOR flash memory of the group pair structure includes a plurality of group pair memory cells 100, each group pair memory cell 100 being correspondingly connected to one group of bit lines 111.

Referring to fig. 11 and 12, each pair of memory cells 100 includes two memory tubes arranged adjacent to each other in the same active region 102, and the memory tubes include a first trench 104 and a charge trap structure 108 in the first trench 104. The two memory tubes of the group pair memory cell 100 are electrically connected by an active region under the charge trapping structure 108 of the two memory tubes. Specifically, during a write, erase or read operation on the group pair memory cell 100, the active region under the charge trapping structure 108 of the two memory tubes of the group pair memory cell 100 may form a channel to electrically connect the two memory tubes of the group pair memory cell 100.

In this embodiment, referring to fig. 11 and 12, the memory tubes in the same active area 102 are the same column of memory tubes, the memory cells 100 in the same active area 102 are the same column of memory cells, and the memory tubes corresponding to one word line 107a are the same row of memory tubes. The group pair memory cells 100 of the same column are correspondingly connected to the same group bit line 111.

Illustratively, referring to FIG. 11, the bit lines BLm-2 and BLm-1 are a group and correspond to the first column of the group pair of memory cells 100; the bit lines BLm and blm+1 are a group and correspond to the group pair memory cells 100 of the second column; the bit lines blm+2 and blm+3 are a group and correspond to the group pair memory cells 100 of the third column.

Referring to fig. 12, the first trenches 104 of each memory cell have a first side and a second side, and for two memory cells of the same pair of memory cells 100, the first sides of the two first trenches 104 corresponding to the two memory cells are close to each other and the second sides are far away from each other, and the active regions of the second sides of the two first trenches 104 of the same pair of memory cells 100 are electrically connected to one of the set of bit lines 111, i.e., the active region of the second side of one first trench 104 is electrically connected to one of the set of bit lines 111, and the active region of the second side of the other first trench 104 is electrically connected to the other of the set of bit lines 111.

Referring to fig. 11 and 12, the layout of two adjacent pairs of memory cells in the same column is mirror symmetry. For convenience of explanation, one storage tube of the same group of the pair of storage units 100 is referred to as a first storage tube, and the other storage tube is referred to as a second storage tube; in two adjacent paired storage units in the same column, the arrangement sequence of the first storage tube and the second storage tube is opposite; for the same column of the group pair memory cells 100, the active regions on the second side of the first trench 104 of the first memory tube of the group pair memory cell 100 are electrically connected to the same bit line, and the active regions on the second side of the first trench 104 of the second memory tube of the group pair memory cell 100 are electrically connected to another bit line of the same group. Illustratively, the active areas of the second side of the first trench 104 of the first memory tube of the first column of the group-pair memory cells 100 are all electrically connected to the bit line BLm-2, and the active areas of the second side of the first trench 104 of the second memory tube of the first column of the group-pair memory cells 100 are all electrically connected to the bit line BLm-1.

In the present embodiment, when data writing (Program) or data reading (Read) is performed on one storage tube of the group pair storage unit 100, the other storage tube is used as a selection tube; one of the bit lines of the group of memory cells 100 may be the source line of the other bit line.

Referring to fig. 11 and 12, after forming a plurality of charge trap structures 108 on a substrate 101 and forming a word line 107a in each word line trench, before forming a plurality of bit lines 111 on the substrate 101, a plurality of contact plugs 110 are formed on the substrate 101, and the active regions 102 on the second side of the two first trenches 104 of the group memory cell 100 are electrically connected to the corresponding bit lines 111 through the contact plugs 110.

Referring to fig. 12, in the paired memory cell 100, channel currents of two memory tubes can flow from the second side of one first trench 104 to the second side of the other first trench 104 along the lower sides of the two charge trap structures 108. In this embodiment, referring to fig. 12, a first doped region 109 with high doping concentration may be formed on top of the active regions 102 on the second side of the two first trenches 104 of the memory cell 100, the contact plug 110 is connected to the first doped region 109, and the conductivity type of the first doped region 109 is opposite to that of the active region 102, so that a PN junction is formed between the active regions on the second side of the first trenches 104 and the first doped region 109, and thus the channel current of the memory tube may smoothly flow into the corresponding bit line 111 through the contact plug 110. Illustratively, the active region 102 is a P-doped region and the first doped region 109 is an N-doped region.

It should be noted that, in the embodiment, the active region between the two first trenches 104 in the paired memory cells 100 is a free region, and the channel current can flow from the lower portion of one charge trapping structure 108 to the lower portion of the other charge trapping structure 108 through the free region due to the smaller spacing between the two first trenches 104 or the two charge trapping structures 108. In other embodiments, taking the active region 102 as a P-type doped region as an example, an N-type doped material such as phosphorus may be implanted into the top of the active region between the two first trenches 104 to form an N-type doped region, so as to assist the current under one charge trap structure 108 to flow under another charge trap structure 108.

The embodiment also provides a NOR flash memory with a pair structure, which can be manufactured by using the manufacturing method of the NOR flash memory with the pair structure.

Referring to fig. 9, 11 and 12, the NOR flash memory of the pair structure provided in this embodiment includes: a substrate 101, a plurality of word line trenches, a plurality of charge trapping structures 108, a plurality of word lines 107a, and a plurality of bit lines 111.

The substrate 101 includes an isolation structure 103 and an active region 102 defined by the isolation structure 103. Each word line trench includes a first trench 104 and a second trench 105 that are interconnected, the first trench 104 being embedded in the substrate of the active region 102 and the second trench 105 being embedded in the isolation structure 103. Each charge trapping structure 108 conformally covers an inner surface of one of the first trenches 104. Each word line 107a fills one word line trench and covers at least a portion of the charge trapping structure 108 within the first trench 104 of that word line trench. Of the plurality of bit lines 111, every adjacent two bit lines 111 are a group.

The NOR flash memory with the pair structure comprises a plurality of pair memory cells 100, each pair memory cell 100 comprises two memory tubes which are adjacently arranged in the same active region 102, each memory tube comprises a first trench 104 and a charge trap structure 108 in the first trench 104, and the two memory tubes of the pair memory cell 100 are electrically connected through the active region 102 below the charge trap structure 108 of the two memory tubes; for two memory tubes of the same group of memory cells, the first sides of two first trenches 104 corresponding to the two memory tubes are close to each other, and the second sides of the two first trenches 104 are far away from each other, and the active areas 102 of the second sides of the two first trenches 104 are electrically connected to one of a group of bit lines 111 respectively; when data writing or data reading is performed on one memory tube of the group pair memory cell 100, the other memory tube serves as a selection tube.

Referring to fig. 9, 11 and 12, the substrate 101 includes a plurality of active regions 102, the active regions 102 are elongated in a first direction (i.e., X-direction), the word line trenches are elongated in a second direction (i.e., Y-direction), the second direction being perpendicular to the first direction, and each word line trench spans the plurality of active regions 102; each of the word line trenches includes a plurality of first trenches 104 and a plurality of second trenches 105 of the same row, the first trenches 104 and the second trenches 105 of the same word line trench being arranged at intervals in the second direction.

Referring to fig. 12, the cross section of the first groove 104 may be of an inverted trapezoid shape, but is not limited thereto. In other embodiments, the cross-section of the first trench 104 may also be rectangular or the like. The cross-sectional shape of the second trench 105 may be the same as the cross-sectional shape of the first trench 104. The cross-sectional shape of the word line 107a may also be rectangular or inverted trapezoidal, but is not limited thereto. When the cross section of the word line 107a is rectangular, the side wall of the word line 107a is parallel to the side wall of the active region on the side of the word line; when the cross section of the word line 107a is inverted trapezoid, the side wall of the word line 107a has a certain inclination angle.

The memory tubes on the same active region 102 are the same column of memory tubes, and the group pair memory cells 100 on the same active region 102 are the same column of group pair memory cells; the group pair memory cells 100 of the same column are correspondingly connected to the same group bit line 111.

In this embodiment, a well region, such as a P-type well region, may be formed on top of the substrate 101, where the active region 102 is located in the well region, and the depth of the well region is greater than that of the isolation structure 103; the depth of the first trench 104 may be the same as the depth of the second trench 105; the depth of the first trenches 104 and the depth of the second trenches 105 are both smaller than the depth of the isolation structures 103. In other embodiments, the substrate 101 may be a P-type substrate, and the entire substrate is a P-type well region, and the well region is not required to be formed by an ion implantation process.

In this embodiment, the charge trap structure 108 may include an oxide layer, a nitride layer and an oxide layer sequentially stacked from bottom to top, i.e., the charge trap structure 108 is an ONO layer, the oxide layer is, for example, a silicon oxide layer, and the nitride layer is, for example, a silicon nitride layer, but is not limited thereto.

In this embodiment, the storage tubes in the NOR flash memory with the paired structure are all charge trap type storage tubes, and the storage tubes perform writing and erasing operations based on FN tunneling. The channel of the storage tube is a PN junction-free channel. In writing, erasing, or reading the group pair memory cell 100, the active region under the charge trapping structure 108 of the two memory tubes of the group pair memory cell 100 forms a channel to electrically connect the two memory tubes of the group pair memory cell 100.

As shown in fig. 12, adjacent two pairs of memory cells 100 of the same active region 102 are connected by the active region 102 therebetween. In other embodiments, two adjacent pairs of memory cells 100 in the same active region 102 may be isolated by an isolation structure.

Note that in this embodiment, the word line 107a also serves as a gate of the memory tube, so that the gate of the memory tube is not separately disposed above the substrate 101, which is advantageous for reducing the vertical height of the flash memory.

In the NOR flash memory with the pairing structure and the manufacturing method thereof provided by the invention, the word line 107a is embedded in the word line groove of the substrate 101, namely, the word line 107a is embedded in the substrate 101, so that a side wall for isolation is not required to be arranged between the word line 107a and the word line 107a, and the word line 107a does not need to be tiled above the substrate 101 with the bit line 111 on the same plane, thereby greatly reducing the area of a storage unit of the flash memory and improving the storage density of the NOR flash memory; the memory tube comprises the first groove 104 and the charge trap structure 108 covering the inner surface of the first groove 104, so that the channel of the memory tube is longer, which is beneficial to improving the electrical property of the memory tube; in addition, each of the pair memory cells 100 includes two memory tubes of the pair adjacently arranged in the active region 102, when one memory tube of the pair memory cell 100 is subjected to data writing or data reading, the other memory tube is used as a selection tube, so that the two memory tubes of the same pair memory cell 100 can be used for independently storing binary data, 1T memory density can be realized, a special selection tube is not required, the area of the memory cell can be reduced, the memory density of the flash memory is improved, and when the pair memory cells are subjected to data writing, the two bit lines 111 of the same group can apply voltages of the same magnitude, so that the power consumption during data writing operation can be reduced.

It should be noted that, in the present description, the differences between the parts described in the following description and the parts described in the previous description are emphasized, and the same or similar parts are referred to each other.

The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a NOR flash memory with a pairing structure is characterized by comprising the following steps:

providing a substrate, wherein the substrate comprises an isolation structure and an active region defined by the isolation structure;

forming a plurality of word line grooves in the substrate, wherein each word line groove comprises a first groove and a second groove which are mutually communicated, the first groove is embedded in the substrate of the active region, and the second groove is embedded in the isolation structure;

forming a plurality of charge trap structures on the substrate and forming a word line within each of the word line trenches; one of the charge trap structures conformally covers the inner surface of one of the first trenches, the word line at least covers part of the charge trap structures in the first trench and is buried in the substrate, and a side wall for isolation is not required to be arranged between the word line and the word line;

forming a plurality of contact plugs on the substrate; and

forming a plurality of bit lines over the substrate, wherein every two adjacent bit lines are in a group;

the NOR flash memory of the group pair structure comprises a plurality of group pair memory units, each group pair memory unit comprises two memory tubes which are adjacently arranged in the active area, each memory tube comprises a first groove and a charge trap structure in the first groove, and the two memory tubes of the group pair memory units are electrically connected through the active area below the charge trap structures of the two memory tubes; for two storage tubes of the same group of paired storage units, the first sides of the two corresponding first grooves are close to each other, the second sides of the two corresponding first grooves are far away from each other, and the active areas of the second sides of the two corresponding first grooves are electrically connected with one of a group of bit lines through the contact plugs respectively; when data writing or data reading is performed on one storage tube of the group pair storage units, the other storage tube is used as a selection tube.

2. The method of claim 1, wherein the substrate comprises a plurality of the active regions, the active regions are elongated in a first direction, the word line trenches are elongated in a second direction, and each of the word line trenches spans the plurality of the active regions.

3. The method of fabricating a NOR flash memory of claim 1, wherein forming a plurality of charge trapping structures on said substrate and forming a word line in each of said word line trenches comprises:

forming a charge trap layer on the substrate, the charge trap layer covering the active region and the isolation structure;

removing the charge trap layer on the isolation structure;

forming a word line material layer on the substrate, the word line material layer covering the substrate and filling up the plurality of first trenches;

and removing the word line material layer and the charge trap layer on the top surface of the substrate, and reserving the word line material layer and the charge trap layer in the first groove, wherein the word line material layer reserved in the first groove is used as part of the word line, and the charge trap layer reserved in the first groove is used as the charge trap structure.

4. A NOR flash memory of a paired structure, comprising:

a substrate comprising an isolation structure and an active region defined by the isolation structure;

each word line groove comprises a first groove and a second groove which are mutually communicated, the first groove is embedded in the substrate of the active area, and the second groove is embedded in the isolation structure;

a plurality of charge trap structures, each of the charge trap structures conformally covering an inner surface of one of the first trenches;

a plurality of word lines, wherein each word line is filled in one word line groove and is buried in the substrate, the word line at least covers part of the charge trap structure in the first groove, and a side wall for isolation is not required to be arranged between the word line and the word line; and

a plurality of bit lines, wherein every two adjacent bit lines are in a group;

the NOR flash memory of the group pair structure comprises a plurality of group pair memory units, each group pair memory unit comprises two memory tubes which are adjacently arranged in the active area, each memory tube comprises a first groove and a charge trap structure in the first groove, and the two memory tubes of the group pair memory units are electrically connected through the active area below the charge trap structures of the two memory tubes; for two storage tubes of the same group of paired storage units, the first sides of the two corresponding first grooves are close to each other, the second sides of the two corresponding first grooves are far away from each other, and the active areas of the second sides of the two corresponding first grooves are electrically connected with one of a group of bit lines through contact plugs respectively; when data writing or data reading is performed on one storage tube of the group pair storage units, the other storage tube is used as a selection tube.

5. The NOR flash memory of claim 4 wherein said substrate includes a plurality of said active regions, said active regions each being elongated in a first direction, said word line trenches being elongated in a second direction, said second direction being perpendicular to said first direction, each of said word line trenches crossing a plurality of said active regions; each of the word line trenches includes a plurality of first trenches and a plurality of second trenches, the first trenches and the second trenches being arranged at intervals in the second direction.

6. The NOR flash memory of claim 4 wherein memory cells on the same active area are of the same column and memory cells on the same active area are of the same column; the group of memory cells in the same column are correspondingly connected with the same group of bit lines.

7. The NOR flash memory of claim 4 wherein said substrate has a well formed on top thereof, said active region being located within said well, said well having a depth greater than a depth of said first trench and a depth of said isolation structure.

8. The NOR flash memory of claim 4 wherein said charge trapping structure comprises an oxide layer, a nitride layer and an oxide layer stacked in sequence from bottom to top.

9. The NOR flash memory of any of claims 4-8 wherein the channel of the memory tube is a PN junction free channel.