CN116939134B

CN116939134B - HDMI system based on MIPIDPHY output

Info

Publication number: CN116939134B
Application number: CN202310719569.2A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Shenzhen Moorechip Technologies Co ltd
Current assignee: Shenzhen Moorechip Technologies Co ltd
Priority date: 2023-06-16
Filing date: 2023-06-16
Publication date: 2024-08-06
Anticipated expiration: 2043-06-16
Also published as: CN116939134A

Abstract

The application relates to the technical field of video data processing and discloses an HDMI system based on MIPIDPHY output, which comprises HDMI and MIPI, wherein the HDMI is connected with a coding module, the coding module is connected with a data stream conversion module, the data stream conversion module is connected with a DPHY module, the MIPI output end is connected with the DPHY module, the DPHY module output end is connected with hardware AC coupling, the hardware AC coupling is connected with hardware DC bias, the coding module comprises DC balance, the DC balance is connected with AUX management, the AUX management is connected with DDC control, the DDC control is connected with Audio coding, the data stream conversion module comprises a displacement Buffer, and the displacement Buffer is connected with time slot management. Through the mobile device platform main chip of current mainstream generally all does not have the HDMI interface, when the user wants to access the large screen expansion and display, all adopt the mode of WIFI with the screen basically, this scheme can bring high delay and loaded down with trivial details installation pairing link.

Description

HDMI system based on MIPIDPHY output

Technical Field

The invention relates to the technical field of video data processing, in particular to an HDMI system based on MIPIDPHY output.

Background

Along with the continuous improvement of the social informatization degree, the requirements of people on video processing are higher and higher, the data volume processed by a video processing system is also larger and larger, and in an embedded video processing system, the main current schemes are mainly 3: ARM-based, DSP-based, and FPGA-based. The FPGA is different from other two chips, is a semi-custom circuit, has a large number of logic units, can construct corresponding circuits to realize required functions by configuring the logic units, is widely applied to high-speed video processing systems because of the characteristics of hardware acceleration, is a full-digital video and sound transmission interface in interfaces of video processing systems, can transmit uncompressed audio and video signals, has the advantages of high bandwidth, small volume, high intelligence, content protection and the like, and is widely applied to high-definition displays and high-definition televisions.

The scheme has the defects that the LVDS differential pin of the FPGA or the Serdes pin is utilized to simulate the TMDS level of the HDMI to directly output the HDMI, the LVDS pin rate of the low-cost and small-volume FPGA can only support 1Gbps, the resolution of the HD (720 p) can be realized at maximum, the FPGA with the high-rate LVDS or the Serdes pin is very expensive in general price and correspondingly high in volume power consumption, the HDMI output is realized by utilizing the FPGA+ADV-Convert mode, the scheme has the defects of a double-chip scheme, high cost/volume/high power consumption and almost no value on the current mainstream wearing, moving and handheld equipment. With the rapid development of mobile devices, MIPI has been widely used as a physical layer interface for smart phone cameras and displays due to its cost-effective flexibility, high speed and low power consumption, and the specification has also been applied to various other applications such as unmanned aerial vehicles, artificial intelligence, ultra-large tablet computers, surveillance cameras and industrial robots, and automotive applications including camera sensing systems, anti-collision radar, car infotainment and dashboard display, so MIPI interfaces have also been used in recent years as military commander of the FPGA industry, from the very beginning soft core analog MIPI to the now various hard core MIPI interfaces supporting 2.5Gbps, which have gradually become standard interfaces for FPGA/CPLD, so we have attempted to implement HDMI output using MIPI interfaces, i.e., to perfectly solve the above HDMI interface problems in mobile devices.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides an HDMI system based on MIPIDPHY output, which solves the problem that large cost is required to be consumed to ensure the display effect when HDMI is output.

In order to achieve the above purpose, the invention is realized by the following technical scheme: the HDMI system based on MIPIDPHY output comprises HDMI and MIPI, wherein the HDMI is connected with a coding module, the coding module is connected with a data stream conversion module, the data stream conversion module is connected with a DPHY module, the MIPI output end is connected with the DPHY module, the MIPI input end is connected with the HDMI, the DPHY module output end is connected with hardware AC coupling, and the hardware AC coupling is connected with hardware DC bias;

The data stream conversion module comprises a displacement Buffer, wherein the displacement Buffer is used for shifting input data into 40Bit and caching the data for subsequent processing, and the displacement Buffer is connected with time slot management;

the time slot management is connected with a Bit Flip, wherein the Bit Flip is Bit exchange, the Bit is changed due to a series of shift, buffer and split operations at the front end, and Bit positions are required to be adapted according to the bottom driving mode of the chip to perform Bit exchange in consideration of different size end modes;

The Bit Flip is connected with a Fifo control, the Fifo control comprises a writing special area and a reading special area and is used for asynchronously performing reading operation and writing operation, the time slot management is used for calculating a time slot interval and inquiring the status of a Fifo counter to make timely adjustment, the Fifo control is connected with a link initialization lock, the link initialization lock is used for inquiring the link status in real time and resetting the whole system in time, and the link initialization lock is connected with rate matching;

The coding module comprises direct current equalization, wherein when the lowest bit of the 8-bit character is unchanged, 7 bits and the first 1 bit of the 7-bit character are coded through exclusive OR or exclusive NOR, a coding indication bit is added to generate 9-bit characters, and according to the number of 0 and 1 of transmitted data and the number of 0 and 1 of the current transmitted data, whether 8 data bits in 9-bit information generated in the first step are subjected to inversion operation is determined, and the 9-bit characters are converted into 10-bit direct current balance codes;

The direct current balance is connected with AUX management, the AUX management is used for inserting and encoding auxiliary information, the AUX management is connected with DDC control, and the DDC control is used for communication between a display and a host system and realizes a plug and play function;

The DDC control is connected with an Audio code, an Audio signal in the Audio code adopts a data packet structure, a check bit is added, 4-bit data is converted into 10 bits through TERC4 coding, and the relation between the transmission frequency of HDMI and the Audio sampling clock frequency is that:

128 xfs=video rate x N/CTS

Wherein fs is the audio sampling frequency, N and CTS are parameters to be transmitted by the audio clock reconstruction data packet, N and CTS are generated by signal source calculation, and the audio reconstruction data packet is transmitted to a receiver, so that the receiver achieves audio and video synchronization.

Working principle: the HDMI coding mode TMDS-Encoder outputs data Bit width of 10Bit, and the MIPI physical layer interface is 8Bit mode, therefore we can not simply call HDMI-IP integrated by chip, but we need to independently complete HDMI coding module realization, in TMDS-Transmitter module example, we finish basic coding function, then draw out 3x10Bit data stream to next stage module to transfer, data stream conversion firstly according to different rate, through PLL module to complete clock matching and shift buffer of input data, because of clock frequency difference, data need to write FIFO module to do cross-domain conversion, then read link layer state waiting Ready, time slot reads FIFO data out of package recombination to MIPI-DPHY module, MIPI electrical characteristic signal swing is 200mv, HDMI signal swing is 400mv, so in Device Constraint Editor (compiling tool option) of compiling tool to adjust pin IO attribute to increase and enhance driving current, HDMI physical layer is not only high-speed LPI signal but also has low-speed LPI signal superimposed signal but also has direct current bias added in hardware, MIPI direct current component is not need to be added, therefore, MIPI direct current component is not need to be directly coupled with DC component is removed by DC-DC component, but is not need to be coupled with DC component 1, therefore, MIPI is directly coupled with DC component is not need to be directly 1, and DC component is directly coupled with DC component, because of MIPI is not has a direct current 1, and has a direct current Coupling protocol, and is used by a direct current Coupling with a direct current 1, because the direct current Coupling protocol is used, and has a direct current 1, HDMI Data only has 3Lane, and we add a clock packet module of TMDS, and then transmit with the remaining one path of Data-Lane on MIPI.

The invention provides an HDMI system based on MIPIDPHY output. The beneficial effects are as follows:

The main chip of the mobile equipment platform of the current main stream is generally not provided with the HDMI interface, and when a user wants to access a large screen for expansion display, the WIFI mode is basically adopted, and the scheme can bring high delay and complicated installation pairing links, and the key point is that the frequency of the low-cost/small-volume FPGA or CPLD is generally low at present, the HDMI output of high resolution (1080 p) is almost impossible, but the MIPI-DPHY hard core is basically mature and quick in frequency.

Drawings

FIG. 1 is a schematic diagram of a TMDS-Transmitter module of the present invention;

FIG. 2 is a diagram of a hardware DC bias circuit of the present invention;

fig. 3 is a circuit diagram of the hardware conversion of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Examples

Referring to fig. 1, an embodiment of the invention provides an HDMI system based on MIPIDPHY output, which includes HDMI and MIPI, wherein the HDMI is connected with a coding module, the coding module is connected with a data stream conversion module, the data stream conversion module is connected with a DPHY module, an MIPI output end is connected with the DPHY module, an output end of the DPHY module is connected with a hardware ac coupling, and the hardware ac coupling is connected with a hardware dc bias.

The data Bit width output by the HDMI coding mode TMDS-Encoder is 10Bit, the physical layer interface of the MIPI is 8Bit mode, the realization of the HDMI coding module is required to be completed autonomously, and after the basic coding function is completed, 3x10Bit data stream is extracted and transmitted to the next-stage module for conversion; according to different rates, clock matching is completed through a PLL module and input data is shifted by a buffer, the electric characteristic signal swing of MIPI is 200mv, but the signal swing of HDMI is 400mv, so IO pin attribute is adjusted in Device Constraint Editor (compiling tool option) of a compiling tool to increase swing and enhance driving current, meanwhile direct current bias is added in hardware, MIPI physical layer is formed by overlapping high-speed signals and low-speed LP signals, HDMI does not have low-speed signals, so that an LP control module is needed to be added (LP and high-speed signals are overlapped and transmitted, and therefore, when the high-speed signals are in different states, the low-speed signals need to be matched with corresponding 0, 1 and high-impedance states so that high-speed transmission can not be influenced at all); the HDMI uses AC Coupling (DC Coupling is realized by DC blocking capacitive Coupling, direct current components are removed), and the MIPI uses DC Coupling (DC Coupling is realized by DC and AC together, and alternating current components are not removed), so that a hardware conversion circuit is added, the following clock of the HDMI is 1/10 of the data frequency, the following clock of the MIPI is 1/2 of the data, so that the clock channel of MIPI-DPHY cannot be directly used, but MIPI protocol data is 4Lane, HDMI data is only 3Lane, and the TMDS clock packet module is added.

The coding module comprises direct current balance, wherein the direct current balance is connected with AUX management, the AUX management is connected with DDC control, and the DDC control is connected with Audio coding.

The direct current equalization is that the 8-bit character is encoded by minimum change of exclusive OR or exclusive OR with the first 1 bit of the remaining 7 bits under the condition that the lowest bit is unchanged, and then the encoding instruction bit is added to generate 9-bit characters (the actual exclusive OR or exclusive OR is determined by the number of 1 contained in 8-bit data, the 9-bit mark adopts which conversion mode, and 0 represents exclusive OR and 1 represents exclusive OR). Then, according to the number of data 0 and 1 already transmitted and the number of data 0 and 1 currently transmitted, determining whether to invert 8 data bits in the 9-bit information generated in the first step (if more 1 is already transmitted and 1 of the current data is more than 0, then invert), and converting the data into a 10-bit direct current balance code (whether a 10-bit flag is inverted, wherein 1 indicates inversion and 0 indicates no inversion); AUX management: insert encoding of auxiliary information in the video stream, such as pixel format, color depth, resolution information, boundary characters, ECC check codes; DDC control: DDC (Display Data Channel) is a specification of a terminal display for informing information (such as resolution, scanning frequency, etc.) of a personal computer display, that is, a communication method between the display and a host system, and is mainly aimed at realizing Plug & Play (Plug & Play) functions; audio coding: the audio signal adopts a data packet structure, and a check bit is added to ensure the reliability of the audio signal, and 4-bit data is converted into 10 bits by TERC4 encoding. Since the video sampling clock and the audio sampling clock are different in frequency and the audio and video transmission frequencies are the same, synchronization of the audio and video clocks is maintained, that is, the relation between the transmission frequency of HDMI and the audio sampling clock frequency is to be determined, 128 xfs=video rate x N/CTS (fs is the audio sampling frequency, N and CTS are parameters to be transmitted by the audio clock reconstruction data packet), N and CTS are calculated by the signal source, and the audio and video synchronization is achieved by transmitting the audio reconstruction data packet to the receiver.

The data stream conversion module comprises a displacement Buffer, wherein the displacement Buffer is connected with time slot management, the time slot management is connected with a Bit Flip, the Bit Flip is connected with Fifo control, the Fifo control is connected with link initialization locking, and the link initialization locking is connected with rate matching.

Because of the difference of clock frequency, data is required to be written into the FIFO module to carry out cross-domain conversion, and then after the read link layer state waits for Ready, the data of the FIFO is read out in a time slot, packed and recombined and transmitted to the MIPI-DPHY module; buffer is a data Buffer, and the least common multiple of the input 10Bit data stream and the output 8Bit data stream is 40, so that the input data is required to be shifted into 40 bits and buffered for subsequent processing; FIFO is an abbreviation for First In/First Out, meaning First In First Out. The FIFO memory is divided into a writing special area and a reading special area, and the reading operation and the writing operation can be performed asynchronously, so that the FIFO memory can be controlled to be converted by a clock domain; the time slot management is that the input and output data bit width and the clock frequency are different, and the time slot interval needs to be calculated and the state of the FiFo counter is inquired to make timely adjustment under the condition that the data stream is not interrupted and the FiFo is not empty and full; link initialization locking: before data output, the link layer is required to be completely stable, otherwise abnormal initialization occurs, so that the situations such as black screen, splash screen and the like occur, the state of the link layer is required to be queried in real time, and once the lost locking is found, the whole system is required to be reset in time, so that the situation that errors cannot be recovered is prevented; bit Flip is Bit exchange, because the front end has a series of operations such as shifting, buffering, splitting and the like, the Bit has been changed, and the Bit positions need to be adapted according to the bottom driving mode of the chip due to the different size end modes;

HDMI includes the PLL module, and the PLL module is connected with the LP control module, and the LP control module is connected with the moderate package of TMDS.

Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. The HDMI system based on MIPIDPHY output comprises HDMI and MIPI, and is characterized in that the HDMI is connected with a coding module, the coding module is connected with a data stream conversion module, the data stream conversion module is connected with a DPHY module, the MIPI output end is connected with the DPHY module, the MIPI input end is connected with HDMI, the DPHY module output end is connected with hardware AC coupling, and the hardware AC coupling is connected with hardware DC bias;

128 xfs=video rate x N/CTS