CN116938154A

CN116938154A - Amplifier circuit, integrated circuit chip and electronic device

Info

Publication number: CN116938154A
Application number: CN202210354177.6A
Authority: CN
Inventors: 刘石生
Original assignee: Shenzhen Jingzhun Communication Technology Co ltd
Current assignee: Shenzhen Jingzhun Communication Technology Co ltd
Priority date: 2022-04-01
Filing date: 2022-04-01
Publication date: 2023-10-24

Abstract

The application relates to an amplifier circuit, an integrated circuit chip and an electronic device. The amplifier circuit includes: the transistor is provided with a first end, a second end and a third end, wherein a signal to be amplified is connected from the first end, an inverse amplified signal is generated at the second end after the signal is amplified by the transistor, and a follow amplified signal is generated at the third end; the first end of the first output impedance matching circuit is connected to the second end of the transistor, and the inverted amplified signal is output as a first amplified signal at the second end of the first output impedance matching circuit after passing through the first output impedance matching circuit; and a second output impedance matching circuit, wherein a first end of the second output impedance matching circuit is connected to a third end of the transistor, and the follow-up amplified signal passes through the second output impedance matching circuit and is output as a second amplified signal at a second end of the second output impedance matching circuit. By the embodiment of the application, the power consumption of the circuit can be reduced.

Description

Amplifier circuit, integrated circuit chip and electronic device

Technical Field

The present application relates to the field of electronic circuits, and more particularly, to an amplifier circuit, an integrated circuit chip, and an electronic device.

Background

The amplifier is used for amplifying signals and is a common device in the field of radio frequency technology, especially in the field of wireless communication and satellite communication. Amplifier power consumption, gain, etc. are important indicators for measuring the performance of an amplifier. In general, it is desirable for a power amplifier to have lower power consumption. With the development of communication technology, the number of amplifiers required in communication devices is increasing, and it is desired to provide a high-performance amplifier with low power consumption.

Disclosure of Invention

Embodiments of the present application provide an amplifier circuit, an integrated circuit chip, and an electronic device to provide an amplifier circuit with reduced power consumption.

According to an aspect of the present application, there is provided an amplifier circuit comprising:

a transistor having a first end, a second end and a third end, wherein a signal to be amplified is accessed from the first end of the transistor, an inverse amplified signal is generated at the second end of the transistor after the signal is amplified by the transistor, and a follow amplified signal is generated at the third end of the transistor;

the first output impedance matching circuit is used for matching the output impedance of the second end of the transistor to a first target impedance, the first target impedance is the output impedance of the second end of the first output impedance matching circuit, the first end of the first output impedance matching circuit is connected to the second end of the transistor, and the inverted amplification signal passes through the first output impedance matching circuit and is output as a first amplification signal at the second end of the first output impedance matching circuit; and

And the second output impedance matching circuit is used for matching the output impedance of the third end of the transistor to a second target impedance, the second target impedance is the output impedance of the second end of the second output impedance matching circuit, the first end of the second output impedance matching circuit is connected to the third end of the transistor, and the following amplified signal passes through the second output impedance matching circuit and is output as a second amplified signal at the second end of the second output impedance matching circuit.

According to another aspect of the present application, there is provided an integrated circuit chip comprising a substrate, and an amplifier circuit as described above located on the substrate.

According to yet another aspect of the present application, there is provided an electronic device comprising an integrated circuit chip as described above.

The technical scheme provided by the embodiment of the application can comprise the following beneficial effects:

in the amplifier circuit, the integrated circuit chip and the electronic device according to the embodiments of the present application, the transistor, the first output impedance matching circuit and the second output impedance matching circuit located at two ends thereof respectively form two amplifying links, amplify the input signal to be amplified respectively, and output two amplified signals. That is, two-way amplification is achieved using one transistor, so that the power consumption of the circuit is greatly reduced.

It is to be understood that both the foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Fig. 1 shows a schematic diagram of an amplifier circuit according to an embodiment of the application;

FIGS. 2A and 2B illustrate schematic diagrams of an amplifier circuit according to an embodiment of the application;

fig. 3 shows a schematic diagram of an amplifier circuit according to an embodiment of the present application, wherein the amplifier circuit 100 further comprises a first bias circuit 124, a second bias circuit 134, an input impedance matching circuit 141, and a third bias circuit 142;

FIGS. 4A and 4B show schematic structural diagrams of an amplifier circuit according to other embodiments of the present application;

FIG. 5A is a schematic diagram showing the phase difference between the first amplified signal and the second amplified signal before and after passing through the first and second output impedance matching circuits;

FIG. 5B is a schematic diagram showing waveforms of the first amplified signal and the second amplified signal after being superimposed;

fig. 6 shows a schematic structural diagram of an amplifier circuit according to an embodiment of the present application, in which examples of the composition of the first and second output impedance matching circuits, the input impedance matching circuit are specifically shown;

Fig. 7 shows a schematic configuration diagram of an amplifier circuit according to an embodiment of the present application, in which examples of the composition of the first and second bias circuits are specifically shown;

fig. 8 shows a schematic diagram of the structure of an amplifier circuit according to an embodiment of the present application, in which another example of the composition of the second bias circuit is specifically shown;

fig. 9 shows a schematic diagram of a structure of an amplifier circuit according to an embodiment of the present application, in which still another example of the composition of the second bias circuit is specifically shown;

fig. 10 shows a schematic structural diagram of an amplifier circuit according to an embodiment of the present application, in which an example of the composition of a third bias circuit is specifically shown;

fig. 11 shows a schematic structural diagram of an amplifier circuit according to an embodiment of the present application, in which another example of the composition of the third bias circuit is specifically shown;

FIG. 12 shows a schematic diagram of an integrated circuit chip according to an embodiment of the application;

fig. 13 shows a schematic diagram of an electronic device according to an embodiment of the application.

Fig. 14 shows a schematic layout of an inductor pair according to an embodiment of the present application.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.

In the following description, numerous specific details are set forth, such as examples of specific components, circuits, and processes, in order to provide a thorough understanding of the present disclosure. The term "connected" as used herein means directly connected or connected through one or more intermediate components or circuits, or connected in a coupled manner. Furthermore, in the following description and for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the embodiments of the present application. It will be appreciated, however, by one skilled in the art that such specific details may not be necessary to practice embodiments of the application. In some embodiments, well-known circuits and devices are shown in block diagram form in order not to obscure the present disclosure. In addition, the interconnections between circuit elements or software blocks may be shown as buses or as single signal lines. Each bus may alternatively be a single signal line, and each single signal line may alternatively be a bus, and a single line or bus may represent any one or more of a multitude of physical or logical mechanisms for communication between the components.

Fig. 1 is a schematic diagram of an amplifier circuit 100 according to an embodiment of the application. As shown in fig. 1, in this embodiment, the amplifier circuit 100 includes a transistor 110, a first output impedance matching circuit 123, and a second output impedance matching circuit 133. The transistor 110 is configured to amplify a signal to be amplified, and has a first end 111, a second end 112, and a third end 113, wherein the signal to be amplified is connected from the first end 111, an inverted amplified signal is generated at the second end 112 of the transistor 110 after the signal is amplified by the transistor 110, and a follow amplified signal is generated at the third end 113 of the transistor 110.

The first output impedance matching circuit 123 and the second output impedance matching circuit 133 are connected at the second terminal 112 and the third terminal 113 of the transistor 110, respectively. The first output impedance matching circuit 123 is configured to match an output impedance of the second terminal 112 of the transistor 110 to a first target impedance, where the first target impedance is an output impedance of the second terminal 112 of the first output impedance matching circuit 123, and the first terminal 121 of the first output impedance matching circuit 123 is connected to the second terminal 112 of the transistor 110. The inverted amplified signal generated at the second terminal 112 of the transistor 110 is output as a first amplified signal at the second terminal 122 of the first output impedance matching circuit 123 after passing through the first output impedance matching circuit 123.

The second output impedance matching circuit 133 is configured to match an output impedance of the third terminal 113 of the transistor 110 to a second target impedance, where the second target impedance is an output impedance of the second terminal 132 of the second output impedance matching circuit 133, and the first terminal 131 of the second output impedance matching circuit 133 is connected to the third terminal 113 of the transistor 110. The following amplified signal generated at the third terminal 113 of the transistor 110 is output as a second amplified signal at the second terminal 132 of the second output impedance matching circuit 133 after passing through the second output impedance matching circuit 133.

In one example, the signal to be amplified and the two amplified signals may both be radio frequency signals.

In the embodiment of the present application, the transistor 110 and the first output impedance matching circuit 123 form a first signal amplifying link, and the transistor 110 and the second output impedance matching circuit 133 form a second signal amplifying link, that is, the signal to be amplified is amplified into two amplified signals by the amplifier circuit 100: the first amplified signal and the second amplified signal, the amplifier circuit 100 forms two amplification links using a single transistor 110, respectively amplifying the signals to be amplified. Both amplification links use transistor 110 as a device for amplifying a signal.

In general, the power consumption of an amplifier mainly depends on the power consumption of a transistor as an amplifying device. In general, two paths of amplified signals need to be amplified by two corresponding transistors respectively, but in the embodiment of the application, two paths of amplified signals are generated by a single transistor, so that the number of transistors is reduced, and the power consumption of an amplifier circuit is greatly reduced.

Fig. 2A and 2B show schematic diagrams of the amplifier circuit 100, wherein fig. 2A shows schematic diagrams of the operation of generating a first amplified signal and fig. 2B shows schematic diagrams of the operation of generating a second amplified signal. In the embodiment of the present application, the operating principle of amplifying the signal to be amplified based on the transistor 100 may equivalently decompose the amplifier circuit 100 shown in fig. 1 into two radio frequency signal amplifiers, as shown in fig. 2A and 2B.

The "transistor" described herein is a transistor that can amplify a signal, and may be, for example, a field effect transistor, a triode, or the like. Although the transistor 100 is shown as a pattern of field effect transistors in the drawings herein, this is only one example of a transistor used in the amplifier of the present application, and the present application is not limited thereto.

In the case where the transistor 110 is a field effect transistor, the first terminal 111 of the transistor 110 is a gate, the second terminal 112 of the transistor 110 is a drain, and the third terminal 113 of the transistor 110 is a source, the amplifier circuit 100 can be equivalently decomposed into a common source amplifier and a source follower amplifier, as shown in fig. 2A and 2B, respectively. In the case where the transistor 110 is a triode, the first terminal 111 of the transistor 110 is a base, the second terminal 112 of the transistor 110 is a collector, and the third terminal 113 of the transistor 110 is an emitter, the amplifier circuit 100 can be equivalently decomposed into a common emitter amplifier and an emitter follower amplifier, as shown in fig. 2A and 2B, respectively.

As shown in fig. 2A, the transistor 110, the first output impedance matching circuit 123 and the source/emitter equivalent impedance Z1 form an equivalent common source/common emitter amplifier, wherein the equivalent impedance Z1 is the equivalent impedance of the first end 131 of the second output impedance matching circuit 133. In the example of fig. 2A, a first bias power supply signal is applied at the third terminal 125 of the first output impedance matching circuit 123 to provide a normal operating voltage/current for the transistor 110 of the common source/common emitter amplifier. The signal to be amplified is input from the first terminal 111 of the transistor 110, becomes an inverted amplified signal after passing through an equivalent common source amplifier/common emitter amplifier, and is output as a first amplified signal at the second terminal 122 of the first output impedance matching circuit 123.

As shown in fig. 2B, the transistor 110, the second output impedance matching circuit 133 and the drain/collector equivalent impedance Z2 form an equivalent source/emitter follower amplifier, wherein the equivalent impedance Z2 is the equivalent impedance of the first end 121 of the first output impedance matching circuit 123. In the example of fig. 2B, a second bias power supply signal is applied at the third terminal 135 of the second output impedance matching circuit 133 to provide a normal operating voltage/current for the transistor 110 of the source/emitter follower amplifier. The signal to be amplified, which is input from the first terminal 111 of the transistor 110, becomes a follower amplified signal after passing through an equivalent source/emitter follower amplifier, and is output as a second amplified signal at the second terminal 132 of the second output impedance matching circuit 133.

In one example, the first bias power signal and the second bias power signal may be appropriate voltage or current signals, respectively, to provide an appropriate dc operating current for the transistor 110 such that both the second terminal 112 and the third terminal 113 of the transistor 110 may perform amplification operations. The "applying the first/second bias power signals" as referred to herein may refer to providing a positive voltage signal, a negative voltage signal, or a ground signal, and may refer to providing a current signal. For example, the first bias power signal is a positive voltage signal and the second bias power signal is another, different positive voltage signal, or the first bias power signal is a positive voltage signal and the second bias power signal is a negative voltage signal or ground. In another example, a third bias power signal may also be coupled from the first terminal 111 of the transistor 110 to provide a bias power (voltage or current) to the first terminal 111, and the magnitudes (voltage or current values) of the first bias power signal, the second bias power signal, and the third bias power signal may be adjusted so that the transistor 110 has an appropriate second-first terminal voltage, and second-third terminal voltage, thereby placing the transistor 110 in a normal operating state.

Fig. 3 shows a schematic diagram of an amplifier circuit according to an embodiment of the application, wherein the amplifier circuit 100 further comprises a first bias circuit 124 and a second bias circuit 134. A first terminal 126 of the first bias circuit 124 is connected to a third terminal 125 of the first output impedance matching circuit 123 and is connected to a first bias power supply signal. The first bias circuit 124 is configured to provide a bias power source (e.g., bias voltage/current) to the second terminal 112 of the transistor 110, and may also provide a radio frequency signal ground to the third terminal 125 of the first output impedance matching circuit 123.

The first terminal 136 of the second bias circuit 134 is connected to the third terminal 135 of the second output impedance matching circuit 133 and is connected to the second bias power supply signal. The second bias circuit 134 is configured to provide a bias power (e.g., bias voltage/current) to the third terminal 113 of the transistor 110, and may also provide a radio frequency signal ground to the third terminal 135 of the second output impedance matching circuit 133.

In the example of fig. 3, the amplifier circuit 100 may further include an input impedance matching circuit 141 and a third bias circuit 142 connected at the first end 111 of the transistor 110. The input impedance matching circuit 141 has a first terminal 143 coupled to the signal to be amplified and a second terminal 144 coupled to the first terminal 111 of the transistor 110. The first terminal 146 of the third bias circuit 142 is connected to the third terminal 145 of the input impedance matching circuit 141. The input impedance matching circuit 141 is for implementing input impedance matching for the amplifier circuit 100. The third bias circuit 142 is configured to provide a bias power (e.g., bias voltage/current) to the first terminal 111 of the transistor 110, and may also provide a radio frequency signal ground to the third terminal 145 of the input impedance matching circuit 141.

In the embodiments described above, two amplified signals are available through the amplifier circuit 100: a first amplified signal and a second amplified signal. The two amplified signals can be used alone or in combination. Fig. 4A shows an example of the use of the first amplified signal and the second amplified signal in combination. As shown in fig. 4A, the amplifier circuit 100 includes a composite output terminal 103 for outputting a composite signal of the first amplified signal and the second amplified signal. In the example of fig. 4A, the amplifier circuit 100 further includes an output impedance transformation circuit 150, one end of which is connected to the combined signal of the first amplified signal and the second amplified signal, and the other end of which is connected to the combined output terminal for performing output impedance transformation for the combined signal. The output impedance transformation circuit 150 has the function of isolating direct current, and can be a lambda/4 impedance transformer or any impedance transformation circuit capable of realizing the requirements of the amplifier according to the embodiment of the application.

In fig. 4A, the combination of the first amplified signal and the second amplified signal is achieved by connecting the second terminal 122 of the first output impedance matching circuit 123 with the second terminal 132 of the second output impedance matching circuit 133. It will be appreciated that the first amplified signal and the second amplified signal may also be combined in other ways. For example, fig. 4B shows another example of using the first amplified signal and the second amplified signal in combination. The example of fig. 4B differs from that of fig. 4A in that the second terminal 122 of the first output impedance matching circuit 123 and the second terminal 132 of the second output impedance matching circuit 133 are not directly connected, but are both connected to the signal synthesizing device 151, i.e., the first amplified signal and the second amplified signal are input to the signal synthesizing device 151, and the first amplified signal and the second amplified signal are synthesized by the signal synthesizing device 151.

In the case of amplitude-amplifying a signal, when the first amplified signal and the second amplified signal are combined for use, in order to achieve an optimal gain, it is necessary to make the phase difference between peaks of the first amplified signal and the second amplified signal 2npi, where n is an integer. In an embodiment of the present application, the phase difference between the peaks of the first amplified signal and the second amplified signal may be made 2npi, where n is an integer, by configuring the first output impedance matching circuit 123 and the second output impedance matching circuit 133.

In the case of amplitude amplification of the signals, when the first amplified signal and the second amplified signal are combined for use, the circuit parameters of the first output impedance matching circuit 123 and the second output impedance matching circuit 133 may be adjusted for optimal noise or optimal power or optimal efficiency, at which time the phase difference between the peaks of the first amplified signal and the second amplified signal will be adjusted according to the performance optimization direction, but the phase difference is close to 2npi, where n is an integer.

Here, the first amplified signal that has not passed through the first output impedance matching circuit 123, i.e., the inverted amplified signal that is amplified through the second terminal 112 of the transistor 110 and is input to the first terminal 121 of the first output impedance matching circuit 123 is referred to as S1', the second amplified signal that has not passed through the second output impedance matching circuit 133, i.e., the following amplified signal that is amplified through the third terminal 113 of the transistor 110 and is input to the first terminal 131 of the second output impedance matching circuit 133 is referred to as S2', and the first amplified signal and the second amplified signal that are output from the second terminal 122 of the first output impedance matching circuit 123 and the second terminal 132 of the second output impedance matching circuit 133 are referred to as S1 and S2, respectively.

Fig. 5A shows a schematic diagram of the phase differences of the amplified signals S1', S2' that do not pass through the first output impedance matching circuit 123 and the second output impedance matching circuit 133 and the peaks of the first amplified signal S1 and the second amplified signal S2 that pass through the first output impedance matching circuit 123 and the second output impedance matching circuit 133. As shown in fig. 5A, if the first output impedance matching circuit 123 and the second output impedance matching circuit 133 are not present, or if the amplified signal does not pass through them, the phase difference of the inverted amplified signal S1 'and the following amplified signal S2' is pi. Such two signals S1 'and S2', if combined together, have peaks and valleys that overlap, resulting in a reduced or 0 amplitude of the combined signal, and thus a gain of 0 or very small.

The embodiment of the present application changes this effect by the first output impedance matching circuit 123 and the second output impedance matching circuit 133. The inverted amplified signal S1 'passes through the first output impedance matching circuit 123 to become a first amplified signal S1, and the following amplified signal S2' passes through the second output impedance matching circuit 133 to become a second amplified signal S2. The first output impedance matching circuit 123 changes the phase of the signal passing therethrough, assuming that the phase thereof is changed by ΔΦ1, that is, as shown in fig. 5A, the phase difference between S1' and S1 is ΔΦ1. Also, the second output impedance matching circuit 133 changes the phase of the signal passing therethrough, assuming that the phase thereof is changed by ΔΦ2, that is, as shown in fig. 5A, the phase difference between S2' and S2 is ΔΦ2. In order to make the phase difference between the peaks of S1 and S2 be 2npi so that their combined signals achieve the optimal gain, the values of ΔΦ1 and ΔΦ2 may be changed by adjusting the circuit parameters of the first output impedance matching circuit 123 and the second output impedance matching circuit 133 (for example, a series inductive device may cause phase lag, a series capacitance may cause phase lead, etc.), so that the absolute value of the difference between ΔΦ1 and ΔΦ2 is (2n—1pi), n is an integer, and after adding the initial phase difference pi between S1 'and S2', the phase difference between the peaks of S1 and S2 is 2npi. Fig. 5B shows a schematic diagram of the effect of the synthesized signal of the amplified signals S1 and S2 with a phase difference of 2npi. As shown in fig. 5B, after such two amplified signals are combined, the peaks and peaks of the signals are superimposed and the valleys and valleys are superimposed, thereby achieving the optimum gain. Ideally, the gain is twice the amplification gain of the second or third terminal of the transistor alone. In the present embodiment, gain multiplication is achieved using a single transistor, and power consumption is not increased (power consumption of a single transistor is still) so that the gain-to-power consumption ratio of the amplifier is improved.

Fig. 5A and 5B show only one cycle of the signal, it being understood that the signal to be amplified is a continuous signal comprising a plurality of cycles, and thus the signals S1', S1, S2', S2 are also continuous signals comprising a plurality of cycles.

Fig. 6 shows a schematic diagram of the structure of the amplifier circuit 100, in which an example of the composition of the first output impedance matching circuit 123, the second output impedance matching circuit 133, and the input impedance matching circuit 141 is specifically shown.

In the example of fig. 6, the first output impedance matching circuit 123 includes a first inductive device L1, a second inductive device L2, and a third inductive device L3, wherein a first end of the first inductive device L1 serves as a first end 121 of the first output impedance matching circuit 123, a second end of the first inductive device L1 is connected to a first end of the second inductive device L2, a second end of the second inductive device L2 serves as a third end 125 of the first output impedance matching circuit 123, and a first end of the third inductive device L3 is connected to a second end of the first inductive device L1 and a first end of the second inductive device L2, and a second end of the third inductive device L3 serves as a second end 122 of the first output impedance matching circuit 123.

The second output impedance matching circuit 133 includes a fourth inductive device L4, a fifth inductive device L5, and a first capacitor C1, where a first end of the fourth inductive device L4 serves as the first end 131 of the second output impedance matching circuit 133, a second end of the fourth inductive device L4 is connected to a first end of the fifth inductive device L5, a second end of the fifth inductive device L5 serves as the third end 135 of the second output impedance matching circuit 133, a first end of the first capacitor C1 is connected to a second end of the fourth inductive device L4 and a first end of the fifth inductive device L5, and a second end of the first capacitor C1 serves as the second end 132 of the second output impedance matching circuit 133.

As shown in fig. 6, the input impedance matching circuit 141 includes a sixth inductive device L6, a seventh inductive device L7, and a second capacitor C2, wherein a first end of the sixth inductive device L6 serves as the second end 144 of the input impedance matching circuit 141, a second end of the sixth inductive device L6 is connected to a first end of the seventh inductive device L7 and a second end of the second capacitor C2, a first end of the second capacitor C2 serves as the first end 143 of the input impedance matching circuit 141, and a second end of the seventh inductive device serves as the third end 145 of the input impedance matching circuit 141.

Herein, "inductive device" refers to any one of a microstrip line, an inductance, or a combination thereof. Each inductive device in the embodiments of the present application may be any one of a microstrip line, an inductance, or a combination thereof.

In one example, the first inductive device L1 and the second inductive device L2 may be configured as pairs of inductances in which the directions of the induced magnetic fields are opposite. In another example, the fourth inductive device L4 and the fifth inductive device L5 may be configured as pairs of inductances with opposite directions of the induced magnetic field. In yet another example, the sixth inductive device L6 and the seventh inductive device L7 may be configured as pairs of inductances with opposite directions of the induced magnetic field.

The pair of inductances in opposite directions of the induced magnetic field may be referred to as a "low-coupling inductance pair". The inductance in the low-coupling inductor pair may be a single-layer wiring spiral inductance or a multi-layer wiring spiral inductance. In some examples, some or all of the inductance pairs L1 and L2, L4 and L5, L6 and L7 may be arranged as low-coupling inductance pairs. In other examples, all of the inductance pairs may not be arranged as low-coupling inductance pairs.

When a signal is excited on the inductor, an induced magnetic field is generated, an induced electric field is generated by the induced magnetic field, and an induced eddy current is generated in the substrate of the chip by the induced electric field, so that energy loss is generated. Therefore, the inductances L1 and L2 also have induced magnetic fields, and an induced electric field generated by the induced magnetic fields generates induced eddy currents in the substrate of the chip, thereby generating energy loss. The directions of the induction magnetic fields of the two inductors of the low-coupling inductor pair are configured to be opposite, so that the directions of induction electric fields generated by the induction magnetic fields are also opposite, and the directions of induction eddy currents respectively generated by the two opposite induction electric fields are also opposite. The induced eddy currents in opposite directions can be partially or completely counteracted, so that the induced eddy currents are reduced or eliminated, the generated energy loss is reduced, and the energy loss of the circuit is reduced.

In addition, because the eddy currents generated by the two inductors of the low-coupling inductor pair can be offset, the two inductors can be arranged adjacently or closer to each other, so that the circuit structure is more compact, the size is reduced, and the cost is reduced.

In one example, the two inductors of an inductor pair may be configured to be positioned adjacent and such that the directions of the induced magnetic fields generated by the two inductors are opposite.

In one example, both inductances of an inductance pair are spiral inductances, which may be arranged in opposite spiral directions in the circuit. For example, the spiral direction of one inductor is clockwise and the other is counter-clockwise.

In one example, the two inductors are arranged in a circuit as mirror images of each other.

Fig. 14 shows a schematic diagram of the arrangement of an inductor pair in an amplifier circuit according to an embodiment of the application. Fig. 14 is a schematic diagram showing inductance versus schematic diagram of an amplifier circuit looking down from a direction perpendicular to the wiring layers of the amplifier circuit. In one example, the amplifier circuit may be an integrated circuit chip.

As shown in fig. 14, the pair 1400 includes two inductors, which are respectively composed of a first microstrip line 1410 and a second microstrip line 1420, and the first microstrip line 1410 is wound into a first spiral pattern S1 and the second microstrip line 1420 is wound into a second spiral pattern S2. The first end 1401 and the second end 1402 of the first microstrip line 1410 are respectively a first end and a second end of the first inductor. The first end 1403 and the second end 1402 of the second microstrip line 1420 serve as a first end and a second end of the second inductor, respectively. The second end 1402 of the first microstrip line 1410 and the second end 1402 of the second microstrip line 1420 are connected together to form a common end 1402 of the first inductor and the second inductor, and the first microstrip line 1410 and the second microstrip line 1420 form a combined microstrip line. The first end 1401 of the first inductor, the first end 1403 of the second inductor, the second end 1402 of the first inductor and the second inductor are connected to other parts of the radio frequency switching circuit by connecting lines, respectively.

The combined microstrip line (first/second microstrip line) of the embodiment of the present application may be composed of a single layer or multiple layers of metal materials. In one example, the merged microstrip line is composed of multiple layers of metallic materials, where each layer of metallic material is located in a different wiring layer of the radio frequency switching circuit. And multiple layers of metal materials positioned in different wiring layers are overlapped together to form a combined microstrip line, and the metal materials of the layers are connected through interlayer through holes. In another example, the merged microstrip line is composed of a single layer of metal material, which may be located in the same or different wiring layers of the radio frequency switch circuit. For example, a portion of the single layer of metal material is located in one wiring layer and the other portion is located in a different wiring layer or layers. Likewise, the single layers of metal material located in the different wiring layers are connected by vias.

In the example of fig. 14, both spiral patterns S1 and S2 comprise a plurality of turns, it being understood that they may also each comprise one turn, or one comprising a plurality of turns and the other comprising a plurality of turns.

As an example, the first microstrip line 1410 and the second microstrip line 1420 may be wound in opposite directions such that the spiral directions of the first spiral pattern S1 and the second spiral pattern S2 are opposite, so that the directions of induced magnetic fields caused by currents in the microstrip lines forming the two spiral patterns S1 and S2 are opposite when the pair of inductors is in an operating state. For example, one of S1 and S2 is made to spiral counterclockwise and the other is made to spiral clockwise. The direction from the first end of the first or second inductor to the common terminal may be referred to herein as a spiral direction, or the direction from the common terminal to the first end of the first or second inductor may be referred to herein as a spiral direction.

In the embodiment of fig. 14, the first microstrip line 1410 is wound in a first spiral pattern S1 in a counterclockwise direction from the first end 1401 to the common end 1402 (inner turn first and outer turn) while winding, and the second microstrip line 1420 is wound in a second spiral pattern S2 in a clockwise direction from the first end 1403 to the common end 1402 (inner turn first and outer turn) while winding. It will be appreciated that both may also be wound one inside-out, the other outside-in (outside-in turns then inside turns), or both. It will be appreciated that the microstrip line need not always be wound in an inside-out or outside-in direction when wound into a spiral pattern S1 or S2, but may be redirected one or more times. For example, it is first from inside to outside, and halfway from outside to inside, or vice versa.

In summary, each of the spiral patterns S1 and S2 may wind the microstrip line from the respective first end to the common end in one of the following manners:

from inside to outside;

from outside to inside;

a combination of the two.

In the embodiment of fig. 14, the two spiral patterns S1 and S2 do not overlap and are adjacent but at a distance D in a direction parallel to the wiring layer of the radio frequency switching circuit. In the embodiment of the present application, since the mutual coupling between the two inductors is low as described above, the two spiral patterns S1 and S2 can be arranged as close as possible (but without overlapping portions), thereby reducing the circuit size and the cost. In one example, the spacing between the two spiral patterns S1 and S2 (distance D as shown in fig. 14) may be at least about 3 microns. The "distance between two spiral patterns" as referred to herein refers to the distance between the microstrip lines of the two spiral patterns closest to each other. As shown in fig. 14, the distance D is the distance between adjacent outermost turns of S1 and S2. In practice, the minimum spacing between the two spiral patterns is determined by the chip manufacturing process.

In the example of fig. 14, the first microstrip line 1410 is equal in length to the second microstrip line 1420. That is, the common terminal 1402 is located at the midpoint of the combined microstrip line. It will be appreciated that the common terminal 1402 may be located at other locations than the midpoint of the combined microstrip line, such as closer to S1 or S2.

As shown in fig. 14, in this embodiment, the spiral patterns S1 and S2 are mirror images, both of which are mirror images, and are shown in fig. 14 as being axisymmetric. I.e. the spiral patterns S1 and S2 have the same configuration, e.g. the same number of turns, microstrip line linewidths, spacing between adjacent turns, etc., except that their patterns are reversed (winding wise reversed), both in a symmetrical/mirrored relationship with respect to a plane perpendicular to the wiring layer in between. S1 and S2 may not be arranged in mirror image, for example, S1 and S2 may have different configurations, for example, S1 and S2 may have different numbers of turns, microstrip line widths, or pitches between adjacent turns, so long as the induced magnetic fields of the wound spiral patterns S1 and S2 are opposite in direction.

It will be appreciated that the arrangement of the first spiral pattern S1 and the second spiral pattern S2 in fig. 14 is interchangeable.

In the inductor pair according to the above embodiment of the present application, the microstrip lines of the two inductors have a common end and are arranged in two spiral patterns with opposite spiral directions, so that the directions of induced magnetic fields generated by currents in the two spirals are opposite when an excitation signal is applied to the inductor pair in an operating state, thereby at least partially reducing mutual coupling/inductance between the two inductors.

In the above-described inductor pair embodiment, as shown in fig. 14, the inductor pair is arranged in an integrated circuit chip to have three terminals: a common terminal 1402, a head terminal 1401 which is a first branch terminal of the inductor pair, and a tail terminal 1403 which is a second branch terminal of the inductor pair. As previously described, the three ends of the pair of inductors may be connected to an excitation signal or other circuit portion by leads. For example, a radio frequency excitation signal may be accessed from the common terminal 1402 of the pair of inductors, the radio frequency excitation signal being split at the common terminal 1402 to a first microstrip line (first inductor) and a second microstrip line (second inductor). The radio frequency excitation signal is typically a periodically varying signal, for example a sinusoidal signal. Let the excitation signal accessed at common 1402 be i _com ＝I _com Sin ωt. The excitation signal splits at the common terminal 1402 into two branches, one flowing through the first spiral pattern S1 from the common terminal 1402 to the first branch terminal (head terminal) 1401 and the other flowing through the second spiral pattern S2 from the common terminal 1402 to the second branch terminal (tail terminal) 1403. Let the excitation signal in the first spiral pattern S1 be i ₁ (t) excitation in the first spiral pattern S1Excitation signal i ₂ (t) assuming no reflection of the signal, i ₁ (t)+i ₂ (t)＝I _com Sin ωt. If the common terminal is located at the midpoint of the combined microstrip line and S1 and S2 are axisymmetric patterns, the excitation signals in S1 and S2 are identical at any time, i.e Excitation signal i in an inductor pair ₁ (t) and i ₂ (t) is a periodically varying signal whose current magnitude varies periodically and thus the induced magnetic field produced is also periodically varying unevenly; the changing magnetic field in turn generates an electric field, thereby generating electromagnetic waves. In the case where the excitation signals in S1 and S2 are identical, since the spiral directions of S1 and S2 are opposite, the induced magnetic field generated at any time S1 is identical in magnitude and opposite in direction to the induced magnetic field generated at S2, and the corresponding induced electric field is also opposite in direction and periodically changes direction. Therefore, the induced magnetic fields generated by S1 and S2 are almost completely cancelled in many areas, and partially cancelled in some areas, so that the corresponding electric field or electromagnetic wave caused by the induced magnetic fields are cancelled, thereby reducing the loss of the inductance pair.

If the common terminal is not located at the midpoint of the combined microstrip line, or if the S1 and S2 are patterns with different configurations, it may not be ensured that the excitation signals in the S1 and S2 are identical, so that the degree of mutual cancellation of the induced magnetic fields of the S1 and S2 is reduced compared with the case that the excitation signals in the S1 and S2 are identical, but the induced magnetic fields generated by the S1 and S2 still partially cancel each other at any moment, so that the electromagnetic radiation intensity is weakened mutually, and the loss of the inductance pair is reduced to a certain extent.

It should be noted that, theoretically, the pair of inductors having three ports (the common port, the head end of the combined microstrip line as the first branch port, and the tail end of the combined microstrip line as the second branch port) as described above is a passive lossless network, and since the passive network has reciprocity, the loss of the pair of inductors and the transmission characteristics thereof are reciprocal regardless of which one of the three ports the excitation signal is input from.

The above description of the inductance pairs applies to all the inductance pairs L1 and L2, L4 and L5, L6 and L7 in the present application.

In the above embodiment, the first output impedance matching circuit 123 includes three inductive devices, the second output impedance matching circuit 133 includes two inductive devices and one capacitor, alternatively, the first output impedance matching circuit 123 may include two inductive devices and one capacitor, and the second output impedance matching circuit 133 includes three inductive devices, i.e., the third inductive device L3 and the first capacitor C1 are interchanged without affecting the normal operation of the respective amplifier circuit embodiments of the present application.

It should be understood that the above embodiments are merely examples of the composition of the first output impedance matching circuit 123, the second output impedance matching circuit 133, and the input impedance matching circuit 141, and those skilled in the art may construct other modified embodiments without performing inventive efforts on these examples, and these modified embodiments are equally applicable to the embodiments of the present application and fall within the scope of protection of the present application.

Fig. 7 shows a schematic diagram of the structure of the amplifier circuit 100, in which an example of the composition of the first bias circuit 124 and the second bias circuit 134 is specifically shown.

As shown in fig. 7, in this example, the first bias circuit 124 includes a sixth capacitor C6, where a first end of the sixth capacitor C6 serves as a first end 126 of the first bias circuit 124, i.e., is connected to (and connected to) a first bias power supply signal (e.g., the first bias power supply V1 shown in fig. 7), and a second end of the sixth capacitor C6 is grounded. The first terminal of the sixth capacitor C6 is further connected to the second inductive device L2.

In one example, the resonance point frequency of the sixth capacitor C6 is close to or the same as the center frequency of the operating frequency band of the amplifier circuit 100, so as to isolate the amplifier circuit 100 from the radio frequency ac signal of the first bias power supply V1, while providing the second terminal 125 of the second inductive device L2 with the radio frequency signal ground.

Fig. 7 also shows an example of the composition of the second bias circuit 134. In this example, the second bias circuit 134 includes a fourth capacitor C4, a first terminal of the fourth capacitor C4 is connected to a second bias supply signal (a second bias supply V2 as shown in fig. 7), and is connected as a first terminal 136 of the second bias circuit 134 to a second terminal 135 of the fifth inductive device L5, and a second terminal of the fourth capacitor C4 is grounded. In one example, the resonance point frequency of the fourth capacitor C4 is close to or the same as the center frequency of the operating frequency band of the amplifier circuit 100, so as to isolate the amplifier circuit 100 from the radio frequency ac signal of the second bias power supply V2, while providing the second terminal 135 of the fifth inductive device L5 with the radio frequency signal ground.

In the embodiment shown in fig. 7, the values of the first bias supply V1 and the second bias supply V2 may be adjusted to cause the transistor 110 to operate in a normal state such that both the second terminal 112 and the third terminal 113 of the transistor 110 may amplify the signal. For example, in fig. 8, the second bias supply V2 may be made directly a ground signal.

Fig. 8 and 9 show two other examples of the composition of the second bias circuit 134.

In the example of fig. 8, the second bias circuit 134 is ground (ground node), i.e. the second terminal 135 of the fifth inductive device L5 is directly grounded. In this way, when the first bias voltage V1 is a proper forward voltage, a proper dc operating current can be maintained between the second terminal 112 and the third terminal 113 of the transistor 110, so that the transistor 110 is in a normal operating state.

In the example of fig. 9, the second bias circuit 134 includes a fifth capacitor C5 and a first resistor R1, where a first end of the fifth capacitor C5 is connected to a first end of the first resistor R1 and serves as a first end 136 of the second bias circuit 134, and a second end of the fifth capacitor C5 and a second end of the first resistor R1 are grounded. In this example, the fifth capacitor C5 is configured to couple the signal output from the third terminal 113 of the transistor 110 and passing through the inductive devices L4 and L5 to ground, and provide the rf signal ground to the second terminal 135 of the fifth inductive device L5, so as to reduce the energy loss of the second bias circuit 134. In addition, the first resistor R1 is used for raising the potential of the third terminal 113 of the transistor 110, so that the voltages from the first terminal 111 to the third terminal 113 of the transistor 110 are negative, so as to maintain the normal operation of the amplifier circuit 100.

Fig. 10 and 11 show schematic structural diagrams of the amplifier circuit 100, in which two examples of the composition of the third bias circuit 142 are specifically shown, respectively.

In the example of fig. 10, the third bias circuit 142 includes a third capacitor C3, a first end of the third capacitor C3 is connected to a third bias power supply signal (e.g., a third bias power supply V3 as shown in fig. 10), and is connected as a first end 146 of the third bias circuit 142 to a second end 145 of the seventh inductive device L7, and a second end of the third capacitor C3 is grounded. In this example, the frequency of the resonance point of the third capacitor C3 is close to or the same as the center frequency of the operating frequency band of the amplifier circuit 100, so as to isolate the amplifier circuit 100 from the rf ac signal of the third bias power supply V3, and provide the second end 145 of the seventh inductive unit L7 with the rf signal ground.

In the example of fig. 11, the third bias circuit 142 is grounded (grounded node), that is, the second end 145 of the seventh inductive unit L7 is directly grounded.

In the examples of fig. 7-11, one example composition of the first bias circuit 124, three example compositions of the second bias circuit 134, and two example compositions of the third bias circuit 142 are provided. Wherein each of the example compositions of the second bias circuit 134 may be used in combination with any of the example compositions of the third bias circuit 142.

In addition, it should be understood that the foregoing only illustrates examples of the composition of the first bias circuit 124, the second bias circuit 134, and the third bias circuit 142, and that those skilled in the art, on the basis of these examples, may construct other modified embodiments without inventive effort, which are equally applicable to the embodiments of the present application and fall within the scope of the present application.

Three bias supplies are involved in the above embodiments: a first bias supply V1 at the second terminal 112 of the transistor 110, a second bias supply V2 at the third terminal 113 of the transistor 110, and a third bias supply V3 at the first terminal 111 of the transistor 110. In some embodiments of the present application, the power supply bias mode of the amplifier circuit 100 may include single power supply self bias, dual power supply bias, and three power supply bias. For example, the single power supply self-bias may refer to providing only the first bias power supply V1 from the outside; dual power bias may refer to providing a first bias power V1 and a third bias power V3 from the outside; the three-power bias may refer to providing the first, second, and third bias power sources V1, V2, and V3 from the outside. The single power supply self-bias power supply is simple, the double power supply bias can exert better power performance, the three power supply bias is beneficial to energy conservation, and the power supply bias mode can be configured according to practical application.

It should be understood that any control signal/voltage referred to herein may be a separate control signal/voltage or may be a shared/common control signal/voltage in any combination. It should be understood that any electrical ground referred to herein may be a separate ground connection/node, or may be a shared/common ground node in any combination (ground may also refer to a relative ground, a floating ground, or some desired potential difference).

Embodiments of the present application also provide an integrated circuit chip including an amplifier circuit as described above, and an electronic device including such an integrated circuit chip. Fig. 12 and 13 show schematic views thereof, respectively. As shown in fig. 12, the integrated circuit chip 300 may include a substrate 200, and an amplifier circuit 100 located on the substrate 200, wherein the amplifier circuit 100 may be any embodiment of the amplifier circuits described above. One amplifier circuit 100 may be used alone, or a plurality of amplifier circuits 100 may be used in cascade. In an example, the integrated circuit chip 300 may include one or more amplifier circuits 100, and the plurality of amplifier circuits 100 may be a plurality of amplifier circuits used alone or a plurality of amplifier circuits used in cascade. The integrated circuit chip 300 may also be a multi-function or system chip in which the amplifier circuit 100 is integrated with other circuits.

An integrated circuit chip comprising an embodiment of the amplifier circuit of the application may be used in an electronic device. As shown in fig. 13, the electronic device 400 includes the integrated circuit chip 300 shown in fig. 12. The electronic device 400 may be a wireless device or any other electronic device that may use an amplifier circuit.

For example, the wireless device may be a User Equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a base station, or the like. The wireless device may also be a cellular telephone, a smart phone, a tablet computer, a wireless modem, a Personal Digital Assistant (PDA), a handheld device, a laptop computer, a smart book, a netbook, a cordless telephone, a Wireless Local Loop (WLL) station, a bluetooth device, etc. The wireless device may be capable of communicating with a wireless communication system, may be capable of receiving signals from a broadcast station, signals from one or more satellites, and the like. A wireless device may support one or more wireless communication technologies (e.g., 5G, LTE, CDMA2000, WCDMA, TD-SCDMA, GSM, 802.11, millimeter waves, etc.).

Those of skill in the art would understand that information and signals may be represented and processed using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. It should also be noted that the types and techniques of transistors may be replaced, rearranged or otherwise modified to achieve the same results. For example, a circuit shown as utilizing PMOS transistors may be modified to use NMOS transistors, and vice versa. Thus, the amplifiers disclosed herein may be implemented using a variety of transistor types and technologies, and are not limited to those shown in the figures. For example, transistor types such as BJT of Si, gallium arsenide pHEMT or HBT, MOSFET of Si, HBT or BiCMOS of germanium silicon, HEMT of gallium nitride, HBT or pHEMT of indium phosphide, or any other transistor technology may be used.

As used herein, a phrase referring to "at least one" in a list of items refers to any combination of those items (including individual members). For example, "at least one of a, b, or c" is intended to encompass: a. b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b-c, c-c, and c-c-c, or any other order of a, b, and c).

It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

Throughout the specification and claims, unless the context requires otherwise, the words "comprise", "comprising", and the like will be construed in a generic and descriptive sense and not for purposes of exclusivity or exhaustion; that is, it is meant to "include, but not limited to. Conditional language, such as "may," "for example," and the like, as used herein is generally intended to mean that some embodiments include, but not other embodiments include, some features, elements, and/or states unless expressly specified otherwise or otherwise dependent upon the context in which they are used. Furthermore, the words "herein," "above," "below," and words of similar importance, when used in this disclosure, shall refer to the entire disclosure, rather than any particular portion of the disclosure. Where the context allows, words in the singular or plural form may also be used in the above detailed description to include the plural or singular, respectively.

It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. An amplifier circuit, comprising:

2. The amplifier circuit of claim 1, further comprising a first bias circuit, a first end of the first bias circuit connected to a third end of the first output impedance matching circuit.

3. The amplifier circuit of claim 2, wherein the third terminal of the first output impedance matching circuit and the first terminal of the first bias circuit are connected to a first bias power supply signal.

4. The amplifier circuit of claim 1, further comprising a second bias circuit, a first terminal of the second bias circuit being connected to a third terminal of the second output impedance matching circuit.

5. The amplifier circuit of claim 4, wherein the third terminal of the second output impedance matching circuit and the first terminal of the second bias circuit are connected to a second bias power supply signal.

6. The amplifier circuit of claim 1, wherein:

the transistor is a field effect transistor, the first end of the transistor is a grid electrode, the second end of the transistor is a drain electrode, and the third end of the transistor is a source electrode; or alternatively

The transistor is a triode, the first end of the transistor is a base, the second end of the transistor is a collector, and the third end of the transistor is an emitter.

7. The amplifier circuit of claim 1, further comprising a composite output for outputting a composite of the first amplified signal and the second amplified signal.

8. The amplifier circuit of claim 1, wherein the first output impedance matching circuit and the second output impedance matching circuit are configured such that a phase difference between peaks of a first amplified signal and a second amplified signal is 2npi, where n is an integer.

9. The amplifier circuit of claim 1, wherein the first output impedance matching circuit comprises a first inductive device, a second inductive device, and a third inductive device, wherein a first end of the first inductive device is used as a first end of the first output impedance matching circuit, a second end of the first inductive device is connected to a first end of the second inductive device, a second end of the second inductive device is used as a third end of the first output impedance matching circuit, a first end of the third inductive device is connected to a second end of the first inductive device and a first end of the second inductive device, and a second end of the third inductive device is used as a second end of the first output impedance matching circuit.

10. The amplifier circuit of claim 1, wherein the second output impedance matching circuit comprises a fourth inductive device, a fifth inductive device, and a first capacitor, wherein the first terminal of the fourth inductive device is used as the first terminal of the second output impedance matching circuit, the second terminal of the fourth inductive device is connected to the first terminal of the fifth inductive device, the second terminal of the fifth inductive device is used as the third terminal of the second output impedance matching circuit, the first terminal of the first capacitor is connected to the second terminal of the fourth inductive device and the first terminal of the fifth inductive device, and the second terminal of the first capacitor is used as the second terminal of the second output impedance matching circuit.

11. The amplifier circuit of claim 9, wherein the first inductive device and the second inductive device are configured as pairs of inductances in opposite directions of the induced magnetic field.

12. The amplifier circuit of claim 10, wherein the fourth inductive device and the fifth inductive device are configured as pairs of inductances in opposite directions of the induced magnetic field.

13. The amplifier circuit of claim 1, further comprising an input impedance matching circuit connected at a first terminal of the transistor, wherein the signal to be amplified is coupled from the first terminal of the input impedance matching circuit, and wherein a second terminal of the input impedance matching circuit is connected to the first terminal of the transistor.

14. The amplifier circuit of claim 13, further comprising a third bias circuit connected at a first terminal of the transistor, the first terminal of the third bias circuit connected to a third terminal of the input impedance matching circuit.

15. The amplifier circuit of claim 13, wherein the input impedance matching circuit comprises a sixth inductive device, a seventh inductive device, and a second capacitor, wherein the first terminal of the sixth inductive device is the second terminal of the input impedance matching circuit, the second terminal of the sixth inductive device is connected to the first terminal of the seventh inductive device and the second terminal of the second capacitor, the first terminal of the second capacitor is the first terminal of the input impedance matching circuit, and the second terminal of the seventh inductive device is the third terminal of the input impedance matching circuit.

16. The amplifier circuit of claim 15, wherein the sixth inductive device and the seventh inductive device are configured as pairs of inductances of opposite directions of the induced magnetic field.

17. The amplifier circuit of claim 14, wherein the third bias circuit is one of the following structures:

A third capacitor, wherein a first end of the third capacitor is connected to a third bias power supply signal and is used as a first end of the third bias circuit, and a second end of the third capacitor is grounded; or (b)

And (3) ground.

18. The amplifier circuit of claim 4, wherein the second bias circuit is one of the following structures:

a fourth capacitor, wherein a first end of the fourth capacitor is connected to a second bias power supply signal and is used as a first end of the second bias circuit, and a second end of the fourth capacitor is grounded;

a fifth capacitor and a first resistor, wherein a first end of the fifth capacitor is connected with a first end of the first resistor and is used as a first end of the second bias circuit, and a second end of the fifth capacitor and a second end of the first resistor are grounded; or (b)

And (3) ground.

19. The amplifier circuit of claim 2, wherein the first bias circuit comprises a sixth capacitor having a first terminal as the first terminal of the first bias circuit and a second terminal connected to ground.

20. The amplifier circuit of claim 9, 10 or 15, wherein the inductive device is any one of a microstrip line, an inductance or a combination thereof.

21. An integrated circuit chip comprising a substrate, and the amplifier circuit of any of claims 1-20 on the substrate.

22. An electronic device comprising the integrated circuit chip of claim 21.