CN116932435B - A hierarchical order preservation method for multi-source requests based on PCIE interface - Google Patents

Abstract

The present invention provides a multi-source request hierarchical order preservation method based on a PCIE interface. A data instruction carries an instruction body, a channel number, a configuration, a read/write flag, and selectively carries an RO flag. The RO flag is a flag defined in the PCIE specification. The PCIE interface divides the data instruction into a read request, a write request, a read response, and a write response according to the read/write flag; the PCIE interface hierarchically processes the data instruction according to the read/write flag and the RO flag. A three-level order preservation process is performed for the data instruction carrying the RO flag; a second-level order preservation process is performed for the write request and the write response in the data instruction without the RO flag; and a first-level order preservation process is performed for the read request and the read response in the data instruction without the RO flag. The request and response method based on the PCIE interface of the present invention performs hierarchical order preservation on multi-source requests and improves the response speed of the PCIE interface.

Description

Multi-source request hierarchical order-preserving method based on PCIE interface

Technical Field

The invention relates to a request and response method based on a PCIE interface, in particular to a multi-source request hierarchical order-preserving method based on the PCIE interface.

Background

PCIE (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, which is a widely used bus protocol for implementing interconnection interfaces of a CPU and various devices. PCIE belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, connected equipment allocates exclusive channel bandwidth, does not share bus bandwidth, mainly supports functions such as active power management, error reporting, end-to-end reliability transmission, hot plug and quality of service (QOS), and the like, and PCIE specifications prescribe strict requirements of various request response sequences.

In implementing PCIE interfaces, in addition to implementing order requirements specified by PCIE specifications, order requirements for implementing multiple requests by IP functions and logic functions need to be satisfied.

At present, for the implementation of PCIE order, there are few specific implementation technical details.

The PCIE interface adopts AXI (Advanced eXtensible Interface) bus protocol design mode, and is generally implemented by a standard interface, and there is little description about how the sequence is handled internally in the disclosure material.

Disclosure of Invention

The invention aims to provide a request and response method based on a PCIE interface, which is used for carrying out hierarchical order preservation on multi-source requests and improving the response speed of the PCIE interface.

The invention relates to a multi-source request grading order keeping method based on a PCIE interface, wherein a data instruction carries an instruction main body, a channel number (Chanel), configuration (Type) and a read/write mark, and also selectively carries an RO mark, wherein the RO mark is a mark defined by PCIE standard, and the PCIE interface divides the data instruction into a read request, a write request, a read response and a write response according to the read/write mark;

the PCIE interface is provided with a sequence preserving buffer, a re-sequence buffer and a receiving buffer;

Performing three-level order preservation processing on a data instruction carrying an RO mark, performing two-level order preservation processing on a write request and a write response in the data instruction without the RO mark, and performing one-level order preservation processing on a read request and a read response in the data instruction without the RO mark;

And carrying out three-level order-preserving processing on the data instruction carrying the RO mark in the following way:

The order-preserving buffer is used for temporarily storing and processing data instructions carrying RO marks, wherein,

The read/write request carrying the RO mark directly enters the order-preserving buffer temporary storage;

The read/write response carrying the RO mark directly enters the order-preserving buffer and is matched with the read/write instruction temporarily stored in the order-preserving buffer, so that the read/write response carrying the RO mark can be efficiently transmitted, and the data instruction carrying the RO mark can be rapidly processed;

for a write request and a write response in a data instruction without an RO mark, performing secondary order preservation processing in the following manner:

the reorder buffer is used for temporarily storing and processing a write request and a write response in a data instruction without an RO mark;

writing a re-sequencing buffer into a write request without an RO mark according to a channel number and configuration, carrying a current tail mark (re-sequencing buffer flag) of the re-sequencing buffer, unpacking the write request, and registering the unpacking number into a corresponding entry of the re-sequencing buffer;

Writing the write response without the RO mark into a re-sequencing buffer according to the channel number and configuration until the unpacked write request in the re-sequencing buffer is completed corresponding to the write response, wherein the write response in the re-sequencing buffer is activated and can be sent;

for a read request and a read response in a data instruction without an RO mark, performing primary order preservation processing in the following manner:

Writing a read request without an RO mark into a receiving buffer according to a channel number, carrying a channel flag mark, setting a channel flag tag +1, preparing to receive the next read request, and sending the read request carrying the channel flag mark;

and writing the read response without the RO mark into a receiving buffer according to the channel number, carrying a channel flag mark by the read response, carrying out matching processing on the read response and the read request in the receiving buffer, sequentially sending the read response which is matched from the channel flag mark=0 to the last channel flag, setting a channel flag label +1, and preparing for receiving the next read response.

Preferably, during the first order preserving process, the read request and the read response are matched in the following manner:

receiving a buffered read request, splitting the read request into a plurality of requests according to a request address and a length, respectively suspending and buffering, wherein each read request carries a channel flag mark and a suspending and buffering number;

The read response of the receiving buffer carries a channel flag mark and a suspension buffer number, and the read response is matched with the read request according to the channel flag mark and the suspension buffer number.

More preferably, the maximum value of the read request length is set to be 2KB, and in PCIE IP, the transmission performance can be improved by setting the maximum value of the read request length, and because the access request in the chip is set to be 64B/128B according to the Cache line, the optimal transmission performance can be obtained by setting the maximum value of the read request length to be 2 KB.

More preferably, the PCIE interface is provided with a configuration register, the first order preserving process is provided with configuration logic, and the configuration logic is stored in the configuration register and is used for recording whether the first order preserving process is performed on different types of read requests;

When different types of read requests are sent from different channels, the read requests carry different channel numbers, and configuration logic screens the read requests meeting the storage conditions to perform primary order-preserving processing;

the read response corresponding to the read request that does not satisfy the save condition may be returned.

Preferably, the re-sequencing buffer is a trigger FIFO, and the use of the trigger FIFO can respond quickly compared to other triggering methods because the information required for sequence preservation is not much.

Preferably, the RO tag is a 1bit tag, which is implemented by using 1bit in the PCIE IP manual, and the RO tag is more universal by using the 1bit tag. The RO flag is 1bit, and the flip-flop implementation is used because the number of control information bits required is not large, and a memory array is not required.

Preferably, the RO flag bits are random and can be configured according to application requirements, so that the requirements on order retention are not strict, and the transmission speed can be improved by relaxing the order retention requirements.

Preferably, the PCIE interface is provided with an order-preserving buffer, the order-preserving buffer is provided with a buffer depth, the buffer depth is set according to the imitative memory delay, and because all read/write requests carrying the RO mark enter the buffer, if the order-preserving buffer queue is full, blocking can be formed, and the buffer depth is set according to the memory delay, so that the pipelined transmission of the memory request can be ensured.

More preferably, the RO flag has optional values of 0 and 1, and the read/write request and the read/write response are matched in the following manner during the three-level order-preserving process:

Identifying a read/write request with the RO mark of 0 as a strong order-preserving mode, wherein the read/write request with the RO mark of 0 can be sent only by the head of an order-preserving buffer queue, and the read/write request with the RO mark of 0 can be listed from the order-preserving buffer queue after corresponding read/write response is collected;

Recognizing the read/write request with RO mark 1 as loose sequence, the read/write request with RO mark 1 can be sent out immediately after the read/write request with RO mark 1 is sent out, if the package sending is finished, the request with RO mark 0 is not blocked by the preamble, and the queue can be listed from the order-preserving buffer queue immediately.

Drawings

Fig. 1 is a schematic diagram of a hierarchical order-preserving process of a multi-source request hierarchical order-preserving method based on PCIE interface according to the present invention

FIG. 2 is a diagram illustrating a structure of several data instructions

FIG. 3 is a schematic diagram illustrating classification of data instructions

FIG. 4 is a data instruction 5 before fifo writing

FIG. 5 is a data instruction 6 after fifo writing

Detailed Description

For clarity of description of the present invention, the present invention is further described with reference to the accompanying drawings and examples, in which a multi-source request hierarchical order keeping method based on PCIE interfaces is provided.

Fig. 1 is a schematic diagram of a hierarchical order-preserving process of a multi-source request hierarchical order-preserving method based on PCIE interfaces according to the present invention.

As shown in fig. 2, several examples of data instructions, where the data instructions carry an instruction body, a channel number (Chanel), a configuration (Type), a read/write flag, and optionally an RO flag, where the RO flag is a random 1bit flag defined by PCIE specification, and the maximum value of the read request length is set to 2KB.

As shown in fig. 3, which is a schematic diagram of classifying data instructions, the PCIE interface classifies the data instructions into read requests, write requests, read responses, and write responses according to read/write flags, and the PCIE interface classifies the data instructions according to the read/write flags and RO flags. Wherein:

And carrying out three-level order-preserving processing on the data instruction carrying the RO mark in the following way:

the PCIE interface is provided with an order-preserving buffer for temporarily storing and processing data instructions carrying RO marks, wherein,

The read/write request carrying the RO mark directly enters the order-preserving buffer temporary storage, and the buffer depth of the order-preserving buffer is 6;

The read/write response carrying the RO mark directly enters the order-preserving buffer and is matched with the read/write instruction temporarily stored in the order-preserving buffer, and the mode enables the read/write response carrying the RO mark to be efficiently transmitted, so that the data instruction carrying the RO mark can be rapidly processed.

For example, there are 6 requests with RO flags selectable to 0, 1, with the read/write request with RO flag 0 being strongly ordered, and the read/write request with RO flag 1 being loosely ordered:

1) Write request 0, ro=1;

2) Write request 1, ro=0;

3) Write request 2, ro=1;

4) Read request 0, ro=1;

5) Write request 3, ro=1;

6) Read request 1, ro=0;

1) write request 0 is in loose order, the queue head has no preamble blocking, and the queue is sent and dequeued;

The updated queue state is:

1) Write request 1, ro=0;

2) Write request 2, ro=1;

3) Read request 0, ro=1;

4) Write request 3, ro=1;

5) Read request 1, ro=0;

the current 1 st one is the upper surface, i.e. 2 nd one of the original data);

the current 1 st write request 0 is a strong order-preserving one, the corresponding write response is not collected at the head of the queue, and the write request 1 is sent without dequeuing;

The updated queue state is:

1) Write request 1, ro=0, has been sent

2) Write request 2, ro=1, queue head

3) Read request 0, ro=1;

4) Write request 3, ro=1;

5) Read request 1, ro=0;

the current 2) write request 2 is in loose order, the head of the queue, send, and cannot dequeue;

The updated queue state is:

1) Write request 1, ro=0, send, no dequeue

2) Write request 2, ro=1, send, unable dequeue

3) Read request 0, ro=1, queue head

4) Write request 3, ro=1;

5) Read request 1, ro=0;

The current 3 rd) read request 0 is in loose order, the head of the queue, and the queue cannot be dequeued;

The updated queue state is:

1) Write request 1, ro=0, send, no dequeue

2) Write request 2, ro=1, send, unable dequeue

3) Read request 0, ro=1, send, unable dequeue

4) Write request 3, ro=1, queue head

5) Read request 1, ro=0;

The current 4) write request 3 is in loose order, the head of the queue, and the queue cannot be dequeued;

The updated queue state is:

1) Write request 1, ro=0, send, no dequeue

2) Write request 2, ro=1, send, unable dequeue

3) Read request 0, ro=1, send, unable dequeue

4) Write request 3, ro=1, send, unable dequeue

5) Read request 1, ro=0, queue head

The current 5 th read request 1 is a strong order-preserving, not a true queue head, not sent and not dequeued;

Waiting 1) after the matched write response of the write request 1 is completed, dequeuing the write request 1, the write request 2, the read request 0 and the write request 3 are all sent, and the RO is 1, and dequeuing all the write responses, wherein the queue state is as follows:

1) Read request 1, ro=0, queue head

The current read request 1 is that the true queue head can send and dequeue after waiting for a response to return.

The invention discloses a multi-source request hierarchical order-preserving method based on PCIE interface, which carries out secondary order-preserving processing on write requests and write responses in data instructions without RO marks in the following way:

Writing a write request without an RO mark into a re-sequencing buffer according to a channel number and configuration, wherein the re-sequencing buffer is a FIFO memory, so that the write request carries a current tail mark (re-sequencing buffer flag) of the re-sequencing buffer, unpacking the write request, and registering the unpacking number into corresponding items of the re-sequencing buffer;

And writing the write response without the RO mark into a re-sequencing buffer according to the channel number and the configuration until all the unpacked write requests in the re-sequencing buffer correspond to the write response, wherein the write response in the re-sequencing buffer is activated and can be sent.

For example, receiving a write request 1 (data instruction 5 before fifo is written as shown in fig. 4) input by Chanel 0, where Chanel has a buffer tail pointer of 0, where write request 1 carries a tail pointer tp=0 (data instruction 6 after fifo is written as shown in fig. 5, data instruction 6 has no Tp flag, tp is a queue tail pointer of the control queue), write request 1 enters the following logic, and Channel 0 has a buffer tail pointer of 1 and tp=1;

Then, receiving a write request 2 input by Chanel 0, wherein the Chanel re-sequencing buffer tail pointer is 2, the write request 2 carries a tail pointer tp=1, the write request 1 enters the subsequent logic, and the Channel 0 re-sequencing buffer tail pointer is added with 1, tp=2;

The write request is split and sent, and the write end receives a write response returned out of order:

The write response of the write request 2 of Channel 0 is firstly collected, but at this time, the write request 2 carries a tail pointer tp=1, is not on the queue head of the resequencing buffer, cannot be dequeued, and cannot be sent;

Then, the write response of the write request 1 of Channel0 is collected, and at this time, the write request 1 carries a tail pointer tp=0, and on the queue head of the resequencing buffer, the queue can be dequeued, the write response 1 is sent out, and the queue head pointer+1;

Finally, the write request 2 of Channel 0 carries the tail pointer tp=1 as the head of the queue of the reorder buffer, which can be dequeued, and the write response 2 is issued.

The invention discloses a multi-source request hierarchical order-preserving method based on PCIE interface, which carries out primary order-preserving processing on read requests and read responses in data instructions without RO marks in the following way:

writing the read request without the RO mark into a receiving buffer according to the channel number, splitting the read request into a plurality of requests to be respectively hung and buffered according to the request address and the length, setting a channel flag label +1 for each read request carrying the channel flag mark and hanging the buffer number, preparing to receive the next read request, and sending the read request carrying the channel flag mark;

And writing the read response without the RO mark into a receiving buffer according to the channel number, wherein the read response carries a channel flag mark and a hanging buffer number, carrying out matching processing on the read response according to the channel flag mark and the hanging buffer number and the read request, sequentially sending the read response which is matched from the channel flag mark=0 to the last channel flag, setting a channel flag label +1, and preparing for receiving the next read response.

When the channel flag of the channel number=0, the channel is idle.

For example, when the initial state channel 0 requests a flag of 0 and the channel 0 inputs a read request 1, the read request 1 carries a flag=0 to enter the subsequent logic, chanel 0 requests a flag+1, and Chanel requests a flag update of 1;

In the subsequent logic, chanel's read request 1 is split into read requests 1-0, read requests 1-1..the group of read requests 1 carries a flag of 0;

Chanel 0 continues to input a read request 2, wherein the read request 2 carries flag=1 and is sent to subsequent logic, chanel requests flag to be added with 1, and Chanel requests flag to be updated to 2 at the moment;

In the subsequent logic, the reading request 2 of Chanel 0 is split into reading requests 2-0, and the reading requests 2-1.

Thereafter, the read response returns out of order:

chanel 0 read request 2-1

Chanel 0 read request 1-0

......

Chanel0 read request 2-0, to which read response 2 matching read request 2 of Chanel was registered prior to read response 1. Because the read responses with complete matching need to be sequentially sent from the flag=0 to the last channel flag, the current channel 0 can only send the read response 1 with the flag of 0, so that the read response 2 (with the flag of 1) matched with the Chanel read request 2 cannot be sent, and the read response 1 matched with the Chanel read request 1 must be waited for to be collected and sent;

the read response continues to return:

chanel 0 read request 1-2

Chanel 0 read request 1-0

At this point, read response 1 of Chanel 0 read request 1 is queued, sent, read response flag +1 of Chanel 0 matches the response flag of Chanel request 1, and Chanel 0 request 1 response is sent.

The first-level order-preserving processing can further carry out logic configuration, a PCIE interface is provided with a configuration register, the first-level order-preserving processing is provided with configuration logic, and the configuration logic is stored in the configuration register and is used for recording whether reading requests of different types are subjected to the first-level order-preserving processing or not;

When different types of read requests are sent from different channels, the read requests carry different channel numbers, and configuration logic screens the read requests meeting the storage conditions to perform primary order-preserving processing;

the read response corresponding to the read request that does not satisfy the save condition may be returned.

Claims (9)

1. A multi-source request grading order keeping method based on PCIE interface is characterized in that a data instruction carries an instruction main body, a channel number Chanel, a configuration Type and a read/write mark, and also selectively carries an RO mark, wherein the RO mark is a mark defined by PCIE standard, and the PCIE interface divides the data instruction into a read request, a write request, a read response and a write response according to the read/write mark;

the PCIE interface is provided with a sequence preserving buffer, a re-sequence buffer and a receiving buffer;

Performing three-level order preservation processing on a data instruction carrying an RO mark, performing two-level order preservation processing on a write request and a write response in the data instruction without the RO mark, and performing one-level order preservation processing on a read request and a read response in the data instruction without the RO mark;

And carrying out three-level order-preserving processing on the data instruction carrying the RO mark in the following way:

The order-preserving buffer is used for temporarily storing and processing data instructions carrying RO marks, wherein,

The read/write request carrying the RO mark directly enters the order-preserving buffer temporary storage;

the read/write response carrying the RO mark directly enters the order-preserving buffer and is matched with the read/write instruction temporarily stored in the order-preserving buffer, so that the read/write response carrying the RO mark can be efficiently transmitted, and the data instruction carrying the RO mark can be rapidly processed;

for a write request and a write response in a data instruction without an RO mark, performing secondary order preservation processing in the following manner:

the reorder buffer is used for temporarily storing and processing a write request and a write response in a data instruction without an RO mark;

Writing a write request without an RO mark into a resequencing buffer according to a channel number and configuration, carrying a current tail mark of the resequencing buffer, unpacking the write request, and registering the unpacking number into corresponding entries of the resequencing buffer;

Writing the write response without the RO mark into a re-sequencing buffer according to the channel number and configuration until the unpacked write request in the re-sequencing buffer is completed corresponding to the write response, wherein the write response in the re-sequencing buffer is activated and can be sent;

for a read request and a read response in a data instruction without an RO mark, performing primary order preservation processing in the following manner:

Writing a read request without an RO mark into a receiving buffer according to a channel number, carrying a channel flag mark, setting a channel flag tag +1, preparing to receive the next read request, and sending the read request carrying the channel flag mark;

And writing the read response without the RO mark into a receiving buffer according to the channel number, carrying a channel flag mark by the read response, carrying out matching processing on the read response and the read request in the receiving buffer, sequentially sending the read response which is matched from the channel flag mark=0 to the last channel flag, setting a channel flag label +1, and preparing for receiving the next read response.

2. The PCIE interface-based multi-source request hierarchical order preservation method of claim 1 wherein, during the primary order preservation processing, the read request and the read response are matched in the following manner:

receiving a buffered read request, splitting the read request into a plurality of requests according to a request address and a length, respectively suspending and buffering, wherein each read request carries a channel flag mark and a suspending and buffering number;

The read response of the receiving buffer carries a channel flag mark and a suspension buffer number, and the read response is matched with the read request according to the channel flag mark and the suspension buffer number.

3. The multi-source request hierarchical order-preserving method based on PCIE interface of claim 1, wherein the PCIE interface is provided with a configuration register, the primary order-preserving process is provided with configuration logic, the configuration logic is stored in the configuration register and is used for recording whether the read requests of different types are subjected to the primary order-preserving process;

When different types of read requests are sent from different channels, the read requests carry different channel numbers, and configuration logic screens the read requests meeting the storage conditions to perform primary order-preserving processing;

the read response corresponding to the read request that does not satisfy the save condition may be returned.

4. The PCIE interface-based multi-source request hierarchical order preservation method of claim 1 wherein the re-order buffer is a trigger FIFO.

5. The PCIE interface-based multi-source request hierarchical order preservation method of claim 1 wherein a length of the read request is set to a maximum of 2KB.

6. The PCIE interface-based multi-source request hierarchical order preservation method of claim 1 wherein the PCIE interface is provided with an order preservation buffer, the order preservation buffer is provided with a buffer depth, and the buffer depth is set according to a copy delay.

7. The PCIE interface-based multi-source request hierarchical order preservation method of claim 1 wherein the RO flags are 1bit flags.

8. The PCIE interface-based multi-source request hierarchical order preservation method of claim 1 wherein the RO flags are random and configurable according to application requirements.

9. The PCIE interface-based multi-source request hierarchical order keeping method of claim 1 wherein the RO flag selectable value is 0, 1, and the read/write request and the read/write response are matched during three-level order keeping processing in the following manner:

Identifying a read/write request with the RO mark of 0 as a strong order-preserving mode, wherein the read/write request with the RO mark of 0 can be sent only by the head of an order-preserving buffer queue, and the read/write request with the RO mark of 0 can be listed from the order-preserving buffer queue after corresponding read/write response is collected;

Recognizing the read/write request with RO mark 1 as loose sequence, the read/write request with RO mark 1 can be sent out immediately after the read/write request with RO mark 1 is sent out, if the package sending is finished, the request with RO mark 0 is not blocked by the preamble, and the queue can be listed from the order-preserving buffer queue immediately.