CN116913886A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents

Abstract

The present disclosure provides a semiconductor device, including: a capacitor disposed in a back end of line (BEOL) layer; and an inductor disposed in a Far back end of line (Far-BEOL) layer over the back end of line layer, wherein the inductor is stacked over and electrically connected to the capacitor. The semiconductor device realizes single-chip stacking integration of the capacitor and the inductor, wherein the capacitor and the inductor can occupy the same chip area, so that technical effects of compact design, high integration level, simple manufacturing process and the like can be obtained.

Description

Semiconductor device

Technical field

The present disclosure relates to the field of semiconductor technology, and in particular, the present disclosure relates to a semiconductor device having a capacitor and an inductor stacked and integrated within a single chip.

Background technique

With the trend of miniaturization of electronic devices such as mobile phones and tablet computers, there is a need for miniaturization of power supply systems. Rectifier circuit is an important component in the power system. However, the output voltage of the rectifier circuit is not a pure DC voltage. In order to obtain a more ideal DC voltage, it is necessary to use a filter circuit composed of reactive components (such as capacitors and inductors) with energy storage function to filter out the rectifier circuit output voltage. The pulsating component is used to obtain the DC voltage. The commonly used LC filter is a filter circuit designed using a combination of inductors and capacitors.

Therefore, achieving compact integration of high-density capacitors and inductors at the chip level is an inevitable trend and necessary means for the development of miniaturization of power systems. However, the manufacturing process of high-density inductors and capacitors is not easily compatible with traditional CMOS processes.

The above information disclosed in this Background section is only for understanding of the background of the inventive concept and therefore it may contain information that does not constitute the prior art.

Contents of the invention

In order to solve the above problems existing in the prior art, the present disclosure proposes a new type of semiconductor device having capacitors and inductors stacked and integrated in a single chip.

According to an aspect of the present disclosure, a semiconductor device is provided, which may include: a capacitor disposed in a back-end-of-line (BEOL) layer; and an inductor disposed in a far-back-end-of-line (BEOL) layer above the back-end-of-line (BEOL) layer. BEOL) layer, where the inductor is stacked over the capacitor and electrically connected to the capacitor.

According to embodiments of the present disclosure, the direction of the magnetic field of the inductor may be parallel to the surface of the semiconductor device.

According to embodiments of the present disclosure, the backend process layer may be separated from the far backend process layer by a polyimide film.

According to embodiments of the present disclosure, the capacitor may be a metal-oxide-metal (MOM) capacitor or a metal-insulator-metal (MIM) capacitor provided in a back-end process layer.

According to embodiments of the present disclosure, the first electrode and the second electrode of the capacitor may be formed to have an interdigitated structure.

According to embodiments of the present disclosure, the first electrode and the second electrode of the capacitor may be formed in one or more metal layers.

According to embodiments of the present disclosure, an oxide selected from at least one of silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, and aluminum oxide may be filled between the first electrode and the second electrode of the capacitor.

According to an embodiment of the present disclosure, the inductor may include: a first metal line; a second metal line disposed above the first metal line; a dielectric layer disposed between the first metal line and the second metal line; a magnetic core, disposed in the dielectric layer and electrically insulated from the first metal line and the second metal line; and a first contact plug disposed in the dielectric layer to connect the first metal line and the second metal line to form a spiral coil of the inductor.

According to embodiments of the present disclosure, the dielectric layer may be formed of polyimide.

According to embodiments of the present disclosure, one end of the inductor may be electrically connected to the first electrode or the second electrode of the capacitor through a second contact plug, and the second contact plug may be disposed in a far backend process layer.

The semiconductor device according to the present disclosure realizes the single-chip stack integration of the capacitor and the inductor by arranging the capacitor in the back-end process layer and the inductor in the far back-end process layer above the back-end process layer, where the capacitor and the inductor are It can occupy the same chip area, thereby achieving technical effects such as compact design, high integration, and simple manufacturing process.

However, the effects of the present disclosure are not limited to the above-described effects, and can be variously expanded without departing from the spirit and scope of the present disclosure. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the present disclosure as claimed.

Description of the drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the inventive concepts.

1 is a partial cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

2 is a top view showing a capacitor included in a semiconductor device according to an embodiment of the present disclosure.

3 is a top view showing an inductor included in a semiconductor device according to an embodiment of the present disclosure.

4A and 4B are schematic circuit diagrams showing an LC filter according to embodiments of the present disclosure.

Detailed ways

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments of the disclosure. As used herein, an "embodiment" is a non-limiting example of an apparatus or method employing one or more of the inventive concepts disclosed herein. It will be apparent, however, that the exemplary embodiments may be practiced without these specific details or with one or more equivalent configurations. Furthermore, various exemplary embodiments may be different, but are not necessarily exclusive. For example, specific features of other exemplary embodiments may be used or implemented in some exemplary embodiments without departing from the inventive concept.

Unless otherwise stated, the described exemplary embodiments are to be understood as providing exemplary features with varying details of some of the ways in which the inventive concepts may be practiced in practice. Accordingly, unless otherwise stated, features, components, modules, regions and/or aspects of various embodiments (hereinafter individually or collectively referred to as "elements") may be referred to without departing from the inventive concept. Additionally combined, separated, interchanged and/or reconfigured.

For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of Any combination of two or more of , Y and Z, such as XYZ, XYY, YZ and ZZ. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one feature from another. Accordingly, the first element discussed below may be referred to as a second element without departing from the teachings of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when used in this specification, the terms "comprising" and/or "comprising" mean that the presence of stated features, steps, operations, elements, parts and/or groups thereof does not exclude the presence or addition of one or Many other features, steps, operations, components, parts and/or groups thereof. It should also be noted that, as used herein, the terms "substantially," "about," and other similar terms are used as terms of approximation rather than terms of degree, and are therefore intended to account for measurements recognized by those of ordinary skill in the art, Inherent bias in calculated and/or supplied values.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries shall be construed to have a meaning consistent with their meaning in the context of the relevant field and shall not be construed in an idealized or overly formal sense unless expressly qualified herein.

Various embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. The same reference numbers refer to the same elements throughout. Furthermore, in the drawings, components are not necessarily drawn to ratio, and the ratios and dimensions of components may be exaggerated for clarity of illustration.

FIG. 1 illustrates a partial cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, the semiconductor device 100 may include a capacitor 101 disposed in a back-end-of-line (BEOL) layer 110 and an inductor disposed in a far-back-end-of-line (Far-BEOL) layer 120 above the back-end-of-line (BEOL) layer 110 Device 102.

As known to those skilled in the art, the integrated circuit manufacturing process can generally be divided into front-end process (FEOL) and back-end process (BEOL) according to the order of process steps performed. The front-end process is used to manufacture devices such as transistors, mainly Including the formation process of isolation, gate structure, source and drain regions, contact holes, etc., and the back-end process is used to form interconnection lines that transmit electrical signals to various devices manufactured through the front-end process, mainly including interlayer dielectric deposition of interconnection lines, Processes such as forming metal lines and drawing out pads. In addition, the integrated circuit manufacturing process can also include far-backend process (Far-BEOL), which is used to provide interconnection between chips or between chips and substrates (packages), mainly including under-bump-metal. , the formation process of redistribution layer (RDL), through silicon via (TSV), etc.

As shown in FIG. 1 , according to an embodiment of the present disclosure, the semiconductor device 100 may include a front-end process layer 130 , a back-end process layer 110 , and a far-end process layer 120 from bottom to top. According to an embodiment of the present disclosure, a device such as a transistor may be provided in the front-end process layer 130 , a capacitor 101 may be provided in the back-end process layer 110 , and an inductor 102 may be provided in the far back-end process layer 120 .

In addition, as shown in FIG. 1 , according to an embodiment of the present disclosure, the backend process layer 110 may be separated from the far backend process layer 120 by a polyimide (Polymide) film 103 . As shown in FIG. 1 , according to an embodiment of the present disclosure, an insulating layer 104 may be provided between the polyimide film 103 and the second metal layer M2 , in which a rewiring layer and a through silicon via may be provided to respectively implement Electrical extension in a direction parallel to the surface of the semiconductor device 100 and in a direction perpendicular to the surface of the semiconductor device 100 .

As shown in FIG. 1 , inductor 102 may be stacked over capacitor 101 and electrically connected to capacitor 101 in accordance with embodiments of the present disclosure.

FIG. 2 shows a top view of the capacitor 101 included in the semiconductor device 100 according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, the capacitor 101 may be a metal-oxide-metal (MOM) capacitor provided in the back-end process layer 110 . Although the embodiments of the present disclosure are described in FIGS. 1 and 2 by taking the capacitor 101 as a MOM capacitor as an example, those skilled in the art will realize that according to alternative embodiments of the present disclosure, the capacitor 101 may also be disposed later. Metal-insulator-metal (MIM) capacitors in segment process layer 110 . The MOM capacitor uses the metal pattern of the same layer to simultaneously form two electrodes with opposite polarities, so its capacitance value can include the capacitance formed by the same conductor layer. In contrast, MIM capacitors use metal patterns located on the same layer or on different layers to form the same electrode, and their capacitance values are mainly composed of capacitances formed by different conductor layers.

As shown in FIG. 2 , the capacitor 101 may include a first electrode 1011 and a second electrode 1012 formed in the same metal layer (eg, the first metal layer M1 and the second metal layer M2 shown in FIG. 1 ). That is, the first electrode 1011 and the second electrode 1012 of the capacitor 101 may be formed of metal.

In addition, as shown in FIG. 2 , according to embodiments of the present disclosure, the first electrode 1011 and the second electrode 1012 of the capacitor 101 may be in the same metal layer (for example, the first metal layer M1 and the second metal layer M1 shown in FIG. 1 The layer M2) is formed to have a comb-shaped structure respectively, so that the first electrode 1011 and the second electrode 1012 can form an interdigitated structure together. According to an embodiment of the present disclosure, the polarities of the first electrode 1011 and the second electrode 1012 of the capacitor 101 may be opposite, and the respective comb-shaped structures of the first electrode 1011 and the second electrode 1012 may have electrode strips arranged in opposite and staggered directions. , thereby forming a capacitance between the electrode strips of the first electrode 1011 and the second electrode 1012 . According to an embodiment of the present disclosure, the capacitance value of the capacitor 101 may be equal to the sum of the capacitances formed by these electrode strips. This design method of the capacitor 101 helps to increase the capacitance per unit area, thereby helping to reduce the area occupied by the capacitor 101, thereby helping to improve the integration level of the semiconductor device 100.

In addition, in order to increase the capacitance value, as shown in FIG. 1 , the capacitor 101 can have a stacked structure, so that its total capacitance can be equal to the sum of the capacitance of the same layer, the capacitance between different layers, and the capacitance between each electrode strip and the through hole. . In other words, according to embodiments of the present disclosure, the first electrode 1011 of the capacitor 101 may be formed in one or more metal layers (eg, the first metal layer M1 and the second metal layer M2 shown in FIG. 1 ), and the capacitor The second electrode 1012 of 101 may also be formed in one or more of the same metal layer (eg, the first metal layer M1 and the second metal layer M2 shown in FIG. 1 ). Although the embodiment of the present disclosure is described in FIG. 1 by taking the example that the first electrode 1011 and the second electrode 1012 of the capacitor 101 are formed in the two metal layers M1 and M2, those skilled in the art will realize that according to the present disclosure In alternative embodiments, the first electrode 1011 and the second electrode 1012 of the capacitor 101 may also be formed in one metal layer or three or more metal layers.

According to an embodiment of the present disclosure, an oxide selected from at least one of the following: silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, and aluminum oxide may be filled between the first electrode 1011 and the second electrode 1012 of the capacitor 101 . As the capacitive medium 1013 of the capacitor 101. Furthermore, when the capacitor 101 has a stacked structure, disposed between metal layers (for example, the first metal layer M1 and the second metal layer M2 shown in FIG. 1 ) in which the first electrode 1011 and the second electrode 1012 are formed. There is an insulating layer 1014. Furthermore, according to embodiments of the present disclosure, when the first electrode 1011 and the second electrode 1012 are formed in different metal layers (for example, the first metal layer M1 and the second metal layer M2 shown in FIG. 1 ), different The first electrode 1011 and the second electrode 1012 in the metal layer may be connected to each other through metal through holes 1015. Those skilled in the art should realize that although in FIGS. 1 and 2 , the metal through holes 1015 are only in the first electrode portions of the first electrode 1011 and the second electrode 1012 except for the electrode strips (ie, the finger portions). is formed between the metal layer M1 and the second metal layer M2, but the present disclosure is not limited thereto. According to an embodiment of the present disclosure, the metal through hole 1015 may also be formed between the first metal layer M1 and the second metal layer M2 of the staggered electrode strips (ie, interdigitated portions) of the first electrode 1011 and the second electrode 1012 .

FIG. 3 is a top view showing the inductor 102 included in the semiconductor device 100 according to an embodiment of the present disclosure.

As shown in FIGS. 1 and 3 , according to embodiments of the present disclosure, the inductor 102 may include first metal lines 1021 (light-colored lines shown in FIG. 3 ) patterned in the third metal layer M3 and a third metal layer The patterned second metal lines 1022 (dark lines shown in Figure 3) in the fourth metal layer M4 above M3. As shown in FIG. 3 , according to an embodiment of the present disclosure, the first metal lines 1021 and the second metal lines 1022 of the inductor 102 may be formed into a pattern having a plurality of lines parallel to each other.

Furthermore, as shown in FIG. 1 , according to an embodiment of the present disclosure, the inductor 102 may include a dielectric layer 1023 disposed between the first metal line 1021 and the second metal line 1022 . According to embodiments of the present disclosure, the dielectric layer 1023 may be formed of, for example, polyimide.

Furthermore, as shown in FIGS. 1 and 3 , according to embodiments of the present disclosure, the inductor 102 may include a magnetic core 1024 disposed in the dielectric layer 1023 and electrically insulated from the first and second metal lines 1021 and 1022 . According to embodiments of the present disclosure, the magnetic core 1024 may be formed of, for example, cobalt zirconium tantalum (CZT), nickel iron (NiFe), or iron nitride (FeN).

Furthermore, as shown in FIGS. 1 and 3 , according to embodiments of the present disclosure, the inductor 102 may include a first contact plug 1025 disposed in the dielectric layer 1023 to connect the first metal line 1021 and the second metal line 1022 , Thereby, the spiral coil of the inductor 102 can be formed by interconnecting the first metal lines 1021 and the second metal lines 1022 with each other.

As shown in FIGS. 1 and 3 , according to embodiments of the present disclosure, the direction of the magnetic field of the inductor may be parallel to the surface of the semiconductor device.

As described above, inductor 102 may be stacked over capacitor 101 according to embodiments of the present disclosure. Specifically, as shown in FIG. 1 , according to an embodiment of the present disclosure, one end of the inductor 102 (for example, as shown in FIG. 1 , the end of the first metal line 1021 of the inductor 102 disposed in the third metal layer M3 ) may be electrically connected to the second electrode 1012 of the capacitor 101 through the second contact plug 1026 . As shown in FIG. 1 , according to embodiments of the present disclosure, the second contact plug 1026 may also be disposed in the far backend process layer 120 .

In fact, according to the embodiment of the present disclosure, any end of the inductor 102 (which can be the end of the first metal line 1021 or the end of the second metal line 1022) provided in the far backend process layer 120 can pass through The second contact plug 1026 is electrically connected to any one of the first electrode 1011 and the second electrode 1012 of the capacitor 101, thereby forming different circuit topologies of the LC filter.

4A and 4B are schematic circuit diagrams showing an LC filter according to embodiments of the present disclosure. The LC filter as shown in FIGS. 4A and 4B may include the capacitor 101 and the inductor 102 described above with reference to FIGS. 1 to 3 .

4A shows a circuit diagram of an LC filter used as a low-pass filter according to an embodiment of the present disclosure. As shown in FIG. 4A , node N1 may refer to the second contact plug 1026 , which is the connection point of the capacitor 101 and the inductor 102 . Load resistor R may be electrically connected to node N1 and connected in parallel with capacitor 101 .

4B shows a circuit diagram of an LC filter used as a high-pass filter according to another embodiment of the present disclosure. As shown in FIG. 4B , node N1 may refer to the second contact plug 1026 , which is the connection point of the capacitor 101 and the inductor 102 . Load resistor R may be electrically connected to node N1 and in parallel with inductor 102 .

The semiconductor device according to the present disclosure realizes the single-chip stack integration of the capacitor and the inductor by arranging the capacitor in the back-end process layer and the inductor in the far back-end process layer above the back-end process layer, where the capacitor and the inductor are It can occupy the same chip area, thereby achieving technical effects such as compact design, high integration, and simple manufacturing process. Furthermore, according to embodiments of the present disclosure, the manufacturing process of the inductor and the capacitor is easily compatible with the traditional CMOS process.

For purposes of illustration, a limited number of possible implementations of the present disclosure have been presented above. Although the present disclosure has been described with reference to embodiments thereof, those skilled in the art will understand that various modifications may be made to the various embodiments of the disclosure without departing from the spirit and scope of the disclosure as disclosed in the appended claims. modifications and changes.

Although this document contains many details, these details should not be construed as limitations on the scope of the disclosure or what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described herein in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Furthermore, although features may be described above as functioning in certain combinations, and even originally claimed as such, in certain circumstances one or more features in the combination may be deleted from the claimed combination , and the claimed combination may involve sub-combinations or variations of sub-combinations.

Claims (10)

1. A semiconductor device, comprising: Capacitors, disposed in the back-end process BEOL layer; and An inductor, arranged in the Far-BEOL layer of the far back-end process above the back-end process layer, wherein the inductor is stacked over the capacitor and electrically connected to the capacitor. 2. The semiconductor device of claim 1, wherein the direction of the magnetic field of the inductor is parallel to a surface of the semiconductor device. 3. The semiconductor device according to claim 1, wherein the backend process layer is separated from the far backend process layer by a polyimide film. 4. The semiconductor device according to any one of claims 1 to 3, wherein the capacitor is a metal-oxide-metal MOM capacitor or a metal-insulator-metal MIM capacitor provided in the back-end process layer . 5. The semiconductor device according to any one of claims 1 to 3, wherein the first electrode and the second electrode of the capacitor are formed to have an interdigitated structure. 6. The semiconductor device according to any one of claims 1 to 3, wherein the first and second electrodes of the capacitor are formed in one or more metal layers. 7. The semiconductor device according to claim 4, wherein an oxide selected from at least one of silicon oxide, tantalum oxide, hafnium oxide, and zirconium oxide is filled between the first electrode and the second electrode of the capacitor. and aluminum oxide. 8. The semiconductor device according to any one of claims 1 to 3, wherein the inductor includes: First metal line; A second metal line is arranged above the first metal line; A dielectric layer disposed between the first metal line and the second metal line; a magnetic core disposed in the dielectric layer and electrically insulated from the first metal line and the second metal line; and A first contact plug is provided in the dielectric layer to connect the first metal line and the second metal line to form a spiral coil of the inductor. 9. The semiconductor device according to claim 8, wherein the dielectric layer is formed of polyimide. 10. The semiconductor device according to claim 8, wherein one end of the inductor is electrically connected to the first electrode or the second electrode of the capacitor through a second contact plug, and Wherein, the second contact plug is provided in the far back process layer.