CN116909495B

CN116909495B - Storage device and control method thereof

Info

Publication number: CN116909495B
Application number: CN202311181419.7A
Authority: CN
Inventors: 祖旭; 王守磊
Original assignee: Hefei Kangxinwei Storage Technology Co Ltd
Current assignee: Hefei Kangxinwei Storage Technology Co Ltd
Priority date: 2023-09-14
Filing date: 2023-09-14
Publication date: 2023-12-15
Anticipated expiration: 2043-09-14
Also published as: CN116909495A

Abstract

The invention provides a storage device and a control method thereof, wherein the storage device comprises: the storage unit comprises a plurality of storage blocks and the storage blocks comprise a plurality of storage pages, wherein problem pages are acquired according to the number of error bits of the storage pages, and the storage blocks to be recovered are acquired according to the number of the problem pages; the mode switching module is used for switching the storage device from the working mode to the idle mode when the duration of the storage device waiting for the host command is greater than a first time threshold; the scanning detection module starts a scanning process of the storage unit when the storage device is in an idle mode and the scanning interval time of the storage device is longer than a second time threshold value, and acquires a problem page and a storage block to be recovered; and the garbage collection module starts a garbage collection process for the storage unit when the storage device is in an idle mode. The invention provides a storage device and a control method thereof, which can improve the performance and the service life of the storage device.

Description

Storage device and control method thereof

Technical Field

The present invention relates to the field of storage technologies, and in particular, to a storage device and a control method thereof.

Background

The memory cell is a nonvolatile memory, and electrons in the memory cell can be stored for a long period of time even when no voltage is externally applied. However, as the storage time of electrons increases or the use temperature of the memory increases, the possibility of electrons escaping from the memory cell increases. When the number of electrons escaping exceeds the error correction capability of the memory device, bad blocks are caused, and the service life of the memory device is affected. The scanning process of the memory cell can solve the problem of electron escape, but can also have the phenomenon of read interference.

In addition, as long as the storage device is in a power-on state, power consumption can be generated, and excessive power consumption can lead to the temperature rise of the storage unit, so that the possibility of electron escape and the occurrence of a read interference phenomenon are further increased. Therefore, in the limited chip area, the solution to the problems of electron escape, read interference, memory power consumption, etc. greatly affects the performance and lifetime of the memory device and determines the quality of one memory device.

Disclosure of Invention

The invention aims to provide a storage device and a control method thereof, which can improve the performance and the service life of the storage device.

In order to solve the technical problems, the invention is realized by the following technical scheme:

the present invention provides a storage device including:

the storage unit comprises a plurality of storage blocks and a plurality of storage pages, wherein a problem storage page is acquired according to the number of error bits of the storage pages, and the storage blocks to be recycled are acquired according to the number of the problem storage pages;

a mode switching module, which switches the storage device from a working mode to an idle mode when the duration of the storage device waiting for the host command is greater than a first time threshold;

the scanning detection module starts a scanning process of the storage unit and acquires the problem storage page and the storage block to be recycled when the storage device is in the idle mode and the scanning interval time of the storage device is longer than a second time threshold; and

and the garbage recycling module starts a garbage recycling process of the storage unit when the storage device is in the idle mode.

In an embodiment of the invention, the scan detection module includes a timing module, and the timing module is electrically connected to the scan detection module and the mode switching module, so as to output a first start signal and a second start signal to the scan detection module, and output the first start signal to the mode switching module.

In an embodiment of the present invention, the timing module includes a command interval timing unit, when the operation commanded by the host is finished, the command interval timing unit starts timing and obtains a first timing duration, and when the first timing duration reaches the first timing duration threshold, the timing module outputs the first start signal.

In an embodiment of the present invention, the timing module includes a scan interval timing unit, when a scan process of the storage unit is finished, the scan interval timing unit starts to count and obtain a second timing duration, and when the second timing duration reaches the second duration threshold, the timing module outputs the second start signal.

In an embodiment of the present invention, the scan detection module includes a scan process flag, and when the scan detection module receives the first start signal and the second start signal, the scan process flag is set, and the scan process flag is stored in the storage device.

In an embodiment of the invention, the storage device includes a recycling start module, the recycling start module is electrically connected to the garbage collection module, and when the number of empty storage blocks is smaller than a storage capacity threshold, the recycling start module outputs a third start signal to the garbage collection module.

In an embodiment of the present invention, the storage device includes a command query module, and an execution time node of the command query module is configured to complete the scanning process for the storage block and complete the garbage collection process for the storage block to be collected.

In an embodiment of the present invention, the storage device includes a main controller, where the main controller is electrically connected to the storage unit and the host, and the main controller is divided into a sleep power-down area and a sleep non-power-down area according to whether a device area of the main controller is powered down in a sleep mode.

In one embodiment of the present invention, in the memory block, when the number of the problem memory pages exceeds a reclamation threshold, the memory block is marked as a memory block to be reclaimed.

The invention provides a control method of a storage device, which comprises the following steps:

when the interval time of the host command is greater than a first time threshold, switching the storage device from a working mode to an idle mode;

in the idle mode, when the scanning interval time of the storage unit reaches a second duration threshold, enabling the scanning process of the storage unit, and acquiring a problem storage page according to the error bit number of the storage page;

In the idle mode, when the storage allowance of the storage unit is insufficient or when the storage unit is provided with a storage block to be recycled, starting a garbage recycling process of the storage unit; and

and when the host command is received, interrupting the scanning process and the garbage collection process, and switching the storage device from the idle mode to the working mode.

In an embodiment of the present invention, the storage device includes a main controller, and in the idle mode, when the scanning process and the garbage collection process are finished, data of the main controller is transferred to the storage unit or a sleep non-power-down area, and the storage device is switched to a sleep mode.

In one embodiment of the present invention, the step of interrupting the scanning process includes:

after the storage block is read, judging whether the storage device receives the host command or not;

when the storage device receives a host command, marking the read storage block as an interrupt storage block, and switching the storage device to the working mode; and

after reverting back to the idle mode, the scanning process is performed starting from the next one of the interrupted memory blocks.

In one embodiment of the present invention, the step of interrupting the garbage collection process includes:

after recovering part of the storage pages, judging whether the storage device receives the host command or not; and

and when the storage device receives a host command, interrupting the garbage collection process and switching the storage device to the working mode.

In an embodiment of the present invention, when a storage block to be recycled is not obtained in the scanning process, before executing the garbage recycling process, the storage blocks are sequentially read, and a part of the storage pages in the storage blocks are read, so as to obtain the storage block to be recycled.

As described above, the present invention provides a storage apparatus and a control method thereof, which can reduce resource waste caused by waiting for a host command for a long time. According to the storage device and the control method thereof, the possibility of electron escape can be reduced, the safety, stability and accuracy of data storage are improved, the problem of electron escape is solved, meanwhile, data disorder caused by read interference is reduced, and the power consumption of the storage device is reduced. According to the storage device and the control method thereof, the hardware resources of the storage device can be reasonably allocated through the firmware, the performance of the storage device is improved, and the timely response to the host command can be considered, so that the storage device has good response performance. According to the storage device and the control method thereof, the problem of bad blocks caused by electron escape can be avoided as much as possible, and the service life of the storage device is prolonged. According to the storage device and the control method thereof provided by the invention, the adjustment can be performed based on the real-time parameters of the storage device, so that the frequency allocation of the garbage collection process and the scanning process is more efficient.

Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a memory device according to an embodiment of the invention.

Fig. 2 is a schematic structural diagram of a main controller according to an embodiment of the invention.

FIG. 3 is a schematic diagram of a memory cell according to an embodiment of the invention.

Fig. 4 is a schematic diagram of a timing module according to an embodiment of the invention.

Fig. 5 is a schematic structural diagram of a control firmware according to an embodiment of the invention.

Fig. 6 is a schematic structural diagram of a scan detection module according to an embodiment of the invention.

Fig. 7 is a schematic structural diagram of a recovery start module according to an embodiment of the invention.

Fig. 8 is a schematic diagram of a sleep preparation module 507 according to an embodiment of the invention.

FIG. 9 is a flowchart illustrating a control method of a memory device according to an embodiment of the invention.

Fig. 10 is a flowchart of step S10 in an embodiment of the invention.

Fig. 11 is a flowchart of step S20 in an embodiment of the invention.

Fig. 12 is a flowchart of step S30 in an embodiment of the invention.

Fig. 13 is a flowchart of step S34 in an embodiment of the invention.

Fig. 14 is a flowchart of step S50 in an embodiment of the invention.

Fig. 15 is a schematic block diagram of an electronic device.

Fig. 16 is a schematic block diagram of a computer-readable storage medium.

In the figure: 10. a storage device; 20. a main controller; 21. sleep power-down areas; 22. the sleeping area is not powered down; 201. a microprocessor; 202. a host interface controller; 203. a cache controller; 204. a buffer; 205. a memory cell controller; 206. an error correction module; 207. a timing module; 2071. a command interval timing unit; 2072. a scanning interval timing unit; 30. a storage unit; 301. a storage module; 302. a storage block; 303. storing pages; 40. a memory; 50. control firmware; 501. initializing a module; 502. a mode switching module; 503. a command query module; 504. a scanning detection module; 5041. a start signal receiving unit; 5042. a scanning process marking unit; 5043. a detection unit; 5044. a recovery page acquisition unit; 5045. an interrupt marking unit; 505. a recovery starting module; 5051. a storage space judging unit; 5052. a recovery page judging unit; 5053. a recovery start unit; 506. a garbage collection module; 507. a sleep preparation module; 5071. a data brushing unit; 5072. a data transfer unit; 5073. a signal emitting unit; 60. a host; 601. a processor; 70. computer instructions; 701. computer readable storage media.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 1, a memory device 10 according to the present invention includes a main controller 20, a memory unit 30, and a memory 40. Wherein the storage device 10 is a solid state disk. The memory unit 30 is a NAND flash memory based memory such as an SM memory flash Card, a CF Card, a multimedia Card (MMC), a secure digital Card (Secure Digital Card, SD Card), a memory stick, a micro hard disk, and the like. The memory 40 may be dynamic random access memory (Dynamic Random Access Memory, DRAM), erasable programmable read only memory (Erasable Programmable Read Only Memory, EPROM) or electrically erasable programmable read only memory (Electrically Erasable Programmableread only memory, EEPROM). Control firmware 50 is stored in memory 40. Wherein the hardware resources of the storage device 10 are regulated by the control firmware 50. Specifically, during the operation of the storage device 10, the main controller 20 reads out and operates the control firmware 50 from the memory 40. The main controller 20 calls hardware resources according to the content of the control firmware 50, and executes machine actions corresponding to the control firmware 50. The main controller 20 is electrically connected to the host 60 to receive host instructions and host data of the host 60.

Referring to fig. 1 and 2, in one embodiment of the present invention, a host controller 20 microprocessor 201, a host interface controller 202, a buffer controller 203, a buffer 204, and a memory cell controller 205, and an error correction module 206 are provided. Wherein the microprocessor 201 is a reduced instruction system computer (Reduced Instruction System Computer, RISC) and in particular an ARM processor. The microprocessor 201 is electrically connected to the host interface controller 202, the cache controller 203, and the memory unit controller 205. The host interface controller 202 is electrically connected to the host 60 through an interface to receive instructions and data of the host 60 and feed back data of the host controller 20. The connection interface between the host 60 and the host controller 20 may be SATA hard disk, high speed serial computer expansion bus interface (Peripheral Component Interconnect express, PCIe), SAS interface. The buffer controller 203 is electrically connected to the memory 40 and the buffer 204 to control the transfer and storage of data. In this embodiment, the memory cell controller 205 is electrically connected to the error correction module 206 to correct the data read out from the memory cell 30 during the reading process of the memory cell 30. Wherein the error correction module 206 may perform error checking and correction of the memory cells 30 by low density parity Check codes (LDPC).

Referring to fig. 1 and 2, in one embodiment of the present invention, a memory device 10 includes a sleep mode, an operational mode, and an idle mode. Wherein, when the host controller 20 receives a host command of the host 60, the storage device 10 enters an operation mode, and responds and processes the host command. In the event that the storage device 10 is powered up and the host 60 does not send host instructions to the host controller 20, the storage device 10 is in an idle mode or sleep mode. Specifically, in the idle mode, the memory device 10 is in a standby state, and the devices of the main controller 20 are still in an on state. In idle mode, the storage device 10 may immediately enter an operational mode when it receives a host command. In the sleep mode, part of the devices of the main controller 20 are turned off and stopped. When the storage apparatus 10 receives a host command, the main controller 20 enters an operation mode after restarting the turned-off device. Wherein the sleep mode, the operational mode, and the idle mode are all modes of the memory device 10 after power up. And, the power consumption of the operation mode is higher than that of the idle mode, and the power consumption of the sleep mode is higher than that of the sleep mode. In the present embodiment, the main controller 20 is divided into a sleep power-down area 21 and a sleep power-non-down area 22 according to whether the device is turned off in the sleep mode. Wherein after the sleep mode is turned on, data of the sleep power-down area 21 is lost and the sleep power-down area 22 remains. In this embodiment, a part of the storage area of the buffer 204 may be divided into the sleep power-down area 21 and a part of the storage area may be divided into the sleep power-non-power-down area 22. The device allocation of the sleep power-down area 21 and the sleep power-non-down area 22 can be regulated according to different storage requirements, and the invention is not limited in particular.

Referring to fig. 1 and 3, in an embodiment of the present invention, the memory unit 30 includes a plurality of memory modules 301, wherein the memory modules 301 have unique device numbers, and the plurality of memory modules 301 may be arranged in the order of the device numbers. The memory module 301 includes a plurality of memory blocks 302, wherein the memory blocks 302 are physical blocks (blocks) of a NAND flash memory. Wherein the memory blocks 302 have unique device numbers and the plurality of memory blocks 302 may be arranged in the order of the device numbers. Wherein the memory block 302 comprises a plurality of memory pages 303. Wherein the memory pages 303 have unique device numbers and the plurality of memory pages 303 may be arranged in the order of the device numbers. In this embodiment, the memory block 302 includes a number of reads and a number of erasures, and when the memory page 303 is read, the error correction module 206 corrects the error of the memory page 303 by itself and records the number of error bits of the memory page 303. Wherein the number of error bits is the number of error bits (error bits) obtained during error checking correction (Error Checking and Correcting, ECC).

Referring to fig. 1 to 4, in an embodiment of the present invention, the main controller 20 includes a timing module 207. The timing module 207 includes a command interval timing unit 2071 and a scan interval timing unit 2072. Wherein the command interval timer unit 2071 records the point in time when the host controller 20 receives a host command. Also, the command interval timing unit 2071 has a first time length threshold. When the host controller 20 receives a host command, the command interval timing unit 2071 starts timing. And when the timing duration of the command interval timing unit 2071 reaches the first time duration threshold, the command interval timing unit 2071 generates the first mode conversion signal. The first mode transition signal is used to transition the memory device 10 from an operating mode to an idle mode. The scanning interval timing unit 2072 records a time node at which the scanning process starts, and the scanning interval timing unit 2072 has a second time period threshold. Specifically, when the scanning-interval timing unit 2072 finishes the scanning process, the scanning-interval timing unit 2072 starts timing. And when the timing duration of the scanning interval timing unit 2072 reaches the second duration threshold, the scanning interval timing unit 2072 is ready to start the scanning process. When the storage device 10 is in the idle mode and the timing duration of the scanning interval timing unit 2072 reaches the second duration threshold, the scanning process to the storage unit 30 is started.

Referring to fig. 1 to 4, in an embodiment of the present invention, a second duration threshold is used to define a scan interval duration. In this embodiment, the second duration threshold is not a nominal value, but is a variable. Specifically, the second duration threshold varies with the number of erasures of the memory unit 30, the error correction strength of the error correction module 206, and the operating temperature of the memory unit 30. And combining the influence factors of the second time length threshold value, and dynamically acquiring the second time length threshold value through a mathematical modeling algorithm. The invention is not limited to a particular model for obtaining the second duration threshold. The scanning interval timing unit 2072 thus algorithmically acquires the second duration threshold while timing.

Referring to fig. 1 to 5, in an embodiment of the present invention, the control firmware 50 includes an initialization module 501, a mode switching module 502, a command query module 503, a scan detection module 504, a recycling start module 505, a garbage recycling module 506, and a sleep preparation module 507. The initialization module 501 may be used to activate a device of the main controller 20 when the storage device 10 is powered up, and may also be used to activate a device of the main controller 20 that is turned off after the storage device 10 is switched from the sleep mode to the operation mode. The initialization module 501 may also be used to allocate global parameters, and the specific content of the initialization of the storage device 10 is not limited in the present invention. The mode switching module 502 is configured to switch a usage mode of the storage device 10. Specifically, when the mode switching module 502 receives the first mode switching signal, the storage device 10 is switched from the operating mode to the idle mode. When the mode switching module 502 receives the second mode switching signal, the storage device 10 is switched from the idle mode to the operating mode. When the mode switching module 502 receives the third mode transition signal, the storage device 10 is switched from the idle mode to the sleep mode. When the mode switching module 502 receives the fourth mode transition signal, the storage device 10 is transitioned from the sleep mode to the operation mode. When the storage device 10 is powered up, the storage device 10 is in the operation mode by default. The command query module 503 is configured to query whether the host interface controller 202 receives a host command. And when the host controller 20 receives a new host command, the command query module 503 generates the second mode switching signal and sends the second mode switching signal to the mode switching module 502.

Referring to fig. 1 to 5, in an embodiment of the invention, the scan detection module 504 is configured to traverse the memory block 302 and the memory page 303 in the read memory unit 30 to stabilize the storage of electrons and reduce the escape risk of electrons. The scan detection module 504 is electrically connected to the scan interval timing unit 2072. When the timing duration of the scanning interval timing unit 2072 reaches the second duration threshold, a first start signal is sent to the scanning detection module 504 to prepare to start the scanning detection module 504. Wherein the scan detection module 504 is electrically connected to the command interval timing unit 2071. When the timing duration of the command interval timing unit 2071 reaches the first time duration threshold, the command interval timing unit 2071 transmits a second start signal to the scan detection module 504. When the scan detection module 504 receives the first start signal and the second start signal, a scan process is started for the memory unit 30. It should be noted that, if the scan detection module 504 receives only the first start signal or the second start signal, the scan process is not started.

Referring to fig. 1 to 6, in an embodiment of the present invention, the scan detection module 504 includes a start signal receiving unit 5041, a scan process marking unit 5042, a detection unit 5043, a recovery page acquiring unit 5044, and an interrupt marking unit 5045. Wherein the start signal receiving unit 5041 is configured to receive the first start signal and the second start signal. The scan process flag unit 5042 is configured to set a scan process flag when the scan detection module 504 is started. The scanning process mark is a global variable, and the invention does not limit the establishment position of the scanning process mark. The detection unit 5043 is used for reading the storage data of the storage unit 30. Specifically, in the present embodiment, the detection unit 5043 sequentially reads the memory blocks 302 according to the device number order of the memory blocks 302 until the memory blocks 302 of the memory unit 30 are traversed. And the detection unit 5043 sequentially reads the memory pages 303 according to the device number sequence of the memory pages 303 until the memory pages 303 in the memory block 302 are traversed, so that the reliability of the stored data is improved, and the risk of electronic escape in the memory pages 303 is reduced. In other embodiments of the present invention, the scan process may also be performed by selecting the memory page 303 with a longer memory duration from the memory block 302, so as to improve the scan efficiency. Wherein the selection of the memory page 303 to be read may be defined by setting a memory duration threshold. During the execution of the scanning process by the detection unit 5043, the error correction module 206 corrects the error of the memory page 303 and obtains the number of error bits. Wherein the recycle page fetch unit 5044 has an error correction threshold. When the number of error bits of the memory page 303 is greater than the error correction threshold, the reclamation page acquisition unit 5044 marks the corresponding memory page 303 as the memory page 303 to be reclaimed. In the present embodiment, the detection unit 5043 operates only in the idle mode. Wherein when the scanning process of the detecting unit 5043 is interrupted, the interruption marking unit 5045 marks the position where the scanning process is interrupted. Specifically, the interrupt flag 5045 is electrically connected to the command query module 503 to receive the second mode switching signal. The interrupt marking unit 5045 receives the second mode switching signal, the interrupt marking unit 5045 interrupts the scanning process of the detecting unit 5043, and marks the memory page 303 read by the pre-interrupt detecting unit 5043 as an interrupt memory page 303.

Referring to fig. 1 to 5 and 7, in an embodiment of the present invention, the recovery start module 505 includes a storage space judging unit 5051, a recovery page judging unit 5052 and a recovery start unit 5053. The storage space determining unit 5051 is configured to determine the remaining storage space of the storage unit 30. Specifically, the storage space judging unit 5051 has a storage capacity threshold. When the number of the blank memory blocks 302 is smaller than the memory capacity threshold, the memory space judging unit 5051 sends a third start signal to the reclamation starting unit 5053. The recycle page judging unit 5052 is configured to judge whether or not there is a marked problem memory page 303 in the memory unit 30. Specifically, the recycle page judging unit 5052 traverses the memory blocks 302 in the order of the numbers of the memory blocks 302, obtaining the problem memory page 303. When the problem memory pages 303 are checked and the number of the problem memory pages 303 exceeds the reclamation threshold, the reclamation page judgment unit 5052 marks the corresponding memory block 302 as the memory block 302 to be reclaimed. Next, the recovery page judging unit 5052 sends a fourth start signal to the recovery starting unit 5053. When the recovery start unit 5053 receives the third start signal or the fourth start signal, the recovery start unit 5053 starts the garbage collection process of the garbage collection module 506. In this embodiment, the garbage collection module 506 is configured to perform a garbage collection process of the storage unit 30.

Referring to fig. 1 to 5 and 8, in an embodiment of the present invention, the sleep preparation module 507 includes a data swipe unit 5071, a data transfer unit 5072, and a signal emitting unit 5073. Wherein when the garbage collection process and the scanning process are finished, the data swiping unit 5071 transfers the address mapping table and the host data stored in the main controller 20 to the storage unit 30. And data transfer unit 5072 copies data that facilitates initialization module 501 to complete the initialization process to sleep non-powered down region 22. For example, the data transfer unit 5072 can acquire the location of the memory page 303 where the host data is located, and transfer the location of the memory page 303 to the sleep power-down area 22, so that after returning to the operation mode, the main controller 20 can quickly start up the device and then write the data. Wherein the data swipe unit 5071 and the data transfer unit 5072 may operate simultaneously. The signal sending unit 5073 is electrically connected to the data pushing unit 5071 and the data transferring unit 5072, and sends a third mode switching signal to the mode switching module 502. The memory device 10 transitions from the idle mode to the sleep mode until the memory device 10 is powered down or the mode switch module 502 receives a fourth mode transition signal.

Referring to fig. 1 to 9, the present invention provides a control method of a memory device 10, based on the memory device 10. Wherein the control method of the storage device 10 includes steps S10 to S50.

Step S10, when the interval time of the host command is greater than the first time threshold, the storage device is switched from the working mode to the idle mode.

In the idle mode, when the scanning interval time length reaches the second time length threshold, the scanning process of the storage unit is started, and the problem storage page and the storage block to be recovered are acquired according to the error bit number of the storage page.

Step S30, starting a garbage collection process for the storage unit in the idle mode.

Step S40, when a host command is received, the scanning process and the garbage collection process are interrupted, and the storage device is switched from an idle mode to a working mode.

In the idle mode, when the scanning process and the garbage collection process are finished, the data of the main controller is transferred to the storage unit or the sleep non-power-down area, and the storage device is switched to the sleep mode.

Referring to fig. 1 to 10, in step S10, step S10 is implemented based on the initialization module 501, the mode switching module 502 and the command query module 503 in an embodiment of the present invention. Step S10 includes steps S11 to S18.

Step S11, powering up the storage device.

Step S12, the storage device is switched to an operating mode.

Step S13, executing a first initialization process.

Step S14, executing a second initialization process.

Step S15, after the first initialization process, judging whether a host command is received.

Step S16, after receiving the host command or executing the second initialization process, executing the operation corresponding to the host command, and ending the process of executing the operation.

Step S17, judging whether the waiting time is larger than a first time length threshold value.

Step S18, when the waiting time is larger than the first time threshold, the storage device is switched from the working mode to the idle mode.

Referring to fig. 1 to 10, in an embodiment of the invention, the starting condition of step S10 may be step S11 or step S12. In step S11, the storage device 10 is changed from the power-off state to the power-on state. Thus, after step S11, step S13, the first initialization process is performed. In a first initialization process, various components in the storage device 10 are activated for performing operations corresponding to host commands. After step S13, step S15 is performed to determine whether a host command is received. Wherein, when the host controller 20 receives the host command, step S16 is performed. In step S16, the corresponding operation of the host command is performed until the operation process ends. In the present invention, after step S50 is completed, the storage device 10 enters the sleep mode. In the sleep mode, when the host controller 20 receives the host command again, step S12 is started. In step S12, the storage device 10 is switched from the sleep mode to the operation mode. And step S14 is performed after step S12. In step S14, a second initialization process is performed. In a second initialization process, devices and regions that were turned off in sleep mode are started. After step S14, step S16 is performed. In the present embodiment, after step S16, step S17 is performed. In step S17, the waiting time after the end of the execution of the host command is acquired by the command interval timer unit 2071. Specifically, when the timing duration of the command interval timing unit 2071 is greater than the first time duration threshold, step S18 is performed. In step S18, the storage device 10 is switched from the operation mode to the idle mode. And in the idle mode, steps S20 to S50 are then performed. In step S17, when the timing duration of the command interval timing unit 2071 is less than the first duration threshold and a new host command is received, the process returns to step S15 and step S16.

Referring to fig. 1 to 11, in step S10, the memory device 10 enters an idle mode from an operating mode, and then steps 20 and S40, and steps S30 and S40 are performed. Wherein step S20 includes steps S21 to S210.

And S21, judging whether the scanning interval duration is greater than or equal to a second duration threshold.

And S22, when the scanning interval time length is greater than or equal to a second time length threshold value, setting a scanning progress mark.

Step S23, after the scanning process mark is set, the scanning process is sequentially executed on the storage blocks.

And step S24, judging whether a scanning process flag is set or not when the scanning interval duration is smaller than a second duration threshold.

Step S25, when the scanning process flag is set, acquiring a scanning interrupt storage block, and executing a scanning process on the next storage block of the scanning interrupt storage block.

Step S26, judging whether the error bit number of the memory page exceeds an error correction threshold.

Step S27, when the number of error bits of the memory pages exceeds the error correction threshold, marking the memory pages as problem memory pages, and acquiring the memory blocks to be recycled according to the number of the problem memory pages 303.

Step S28, judging whether the scanning process of the current storage block is finished, and returning to step S23 if the scanning process of the current storage block is not finished.

Step S29, judging whether the scanning process of the storage unit is finished.

Step S210, when the scanning process of the storage unit is finished, the scanning process flag is cleared.

Referring to fig. 1 to 5, and fig. 9 to 11, in step S18, the memory device 10 enters the idle mode when the waiting time is greater than the first time threshold. In idle mode, steps S20 and S30 are initiated. Specifically, in step S21, the timing time of the scanning interval timing unit 2072 is acquired and used as the scanning interval duration, where the second duration threshold is, for example, 24h. When the scanning interval time is longer than the second time period threshold, step S22 is performed. In step S22, the set scanning progress flag is a global variable. After step S22, step S23 is performed. In step S23, the memory blocks 302 may be sequentially scanned and read in the order of the numbers of the memory blocks 302 in the memory unit 30. Specifically, in the scanning process, the data in the memory pages 303 are sequentially read in the order of the numbers of the memory pages 303. Wherein the data of the memory page 303 can be read according to the address mapping table. The invention is not limited to the specific details of the scanning process. In step S21, when the scanning interval duration is smaller than the second duration threshold, step S24 is performed. In step S24, it is determined whether the scan progress flag has been set. When the scan progress flag has been set, step S25 is performed. In step S25, the scan-interruption memory block 302 is acquired, and the scan process is performed starting from the next memory block 302 of the scan-interruption memory block 302. It should be noted that, in the present invention, the content of one memory block 302 is read every time the scanning process. And the memory block 302 that is executing or has just performed the scanning process is defined as the current memory block 302. After step S23 and after step S25, step S26 is performed. It should be noted that, in the scanning process, each time one memory page 303 is read, step S26 is performed until the current memory block 302 is read. In step S26, if the number of error bits of the memory page 303 exceeds the error correction threshold, step S27 is executed. In step S27, the memory page 303 whose number of error bits exceeds the error correction threshold is marked as a problem memory page 303, and then step S28 is performed. In step S26, if the number of error bits in the memory page 303 is equal to or less than the error correction threshold, step S28 is executed to continue reading the next memory page 303. In step S28, if the scanning process of the current memory block 302 is not completed, the process returns to step S23 or step S24 to read the next memory page 303. In the present embodiment, the process of reading the memory page 303 and marking the memory page 303 is repeated until the current memory block 302 is read.

Referring to fig. 1 to 5, and fig. 9 to 11, in an embodiment of the present invention, between step S28 and step S29, steps S41 to S43 may be performed.

Step S41, judging whether the main controller receives a host command.

And step S42, when the main controller receives a host command, marking the currently read storage block as a scanning interrupt storage block.

Step S43, switching the storage device from the idle mode to the working mode.

Referring to fig. 1 to 5, and fig. 9 to 11, in an embodiment of the present invention, after step S28, the current memory block 302 has already performed the scanning process. Step S41 is then performed. In step S41, if the host controller 20 does not receive the host command, step S29 is executed. In step S29, if the scanning process of the storage unit 30 is completed, step S210 is executed. When the scanning process is completed for the memory block 302 corresponding to the last numbered sequence, the scanning process of the memory unit 30 is considered to be ended. After the scanning process of the storage unit 30 is finished, the timing time of the scanning interval timing unit 2072 may be cleared and the timing may be restarted. In another embodiment of the present invention, the timing time of the scan interval timing unit 2072 may be cleared and restarted after a new scan is started, for example, while the scan progress flag is set. In step S210, the scan progress flag is cleared. In step S41, when the host controller 20 receives a host command, step S42 is performed. In step S42, the current memory block 302 is marked as a scan-interrupted memory block 302, and then step S43 is performed to switch the memory device 10 from the idle mode to the operating mode. In step S25, the acquired scan interrupt memory block 302 is the scan interrupt memory block 302 marked in step S42. In the event that the scanning process of the memory unit 30 is interrupted by a host command, the scanning process flag is not cleared. Therefore, in the middle part S24, the process of judging whether the scanning process flag is set can confirm whether the previous scanning process is interrupted, so as to reasonably arrange the scanning process, balance resource allocation and improve the accuracy of the scanning process. In the present invention, the end of the scanning process of the storage unit 30 is identified by clearing the scanning process flag.

Referring to fig. 1 to 12, in step S18, the memory device 10 enters an idle mode in an embodiment of the present invention. At step S18, step S31 is performed while step S21 is performed. In step S31, it is determined whether the number of empty white memory blocks 302 in the memory unit 30 is smaller than the memory capacity threshold. If the number of blank memory blocks 302 is smaller than the memory capacity threshold, the memory margin of the memory unit 30 is insufficient, and step S32 is performed. In step S32, a garbage collection process is performed on the storage unit 30. In the garbage collection process of the storage unit 30, the selected source block has a priority that the non-closed storage block 302 is higher than the storage block 302 to be collected, the priority of the storage block 302 to be collected is higher than the storage block 302 selected in the balanced wear condition, and the priority of the storage block 302 selected in the balanced wear condition is higher than the storage block 302 with the least effective data number. It should be noted that the specific steps of the garbage collection process are not limited in the present invention. The goal of the garbage collection process is to sort and transfer the valid data of a portion of the memory blocks 302 into another memory block 302, thereby creating a new blank memory block 302. Wherein in the case where the scanning interval duration has not reached the second duration threshold, step S20 and step S30 are parallel steps. In the case where the scanning interval duration reaches the second duration threshold, in the present embodiment, step S31 and step S21 are parallel steps. The step S32 has a higher priority than the step S22 or the step S24, and the operable space is sorted out in the storage unit 30 to ensure that the host command can be executed normally. And steps S22 to S210 have higher priority than steps S32 to S36. The problem memory page 303 is acquired by the scanning process of the memory unit 30 to save the resource occupation of the garbage collection process. The step S30 specifically includes steps S31 to S36.

Step S31, judging whether the storage margin of the storage unit is insufficient.

And step S32, executing a garbage collection process on the storage unit when the storage allowance of the storage unit is insufficient.

Step S33, judging whether the storage unit has the storage block to be recovered or not when the storage allowance of the storage unit is sufficient.

Step S34, when no storage block to be recycled exists in the storage unit, the storage blocks are scanned in sequence, and part of storage pages of the storage blocks are scanned each time, so that the storage blocks to be recycled are obtained.

Step S35, judging whether the storage block to be recycled is obtained in step S34.

And S36, executing a garbage collection process on the storage blocks to be collected when the storage blocks to be collected exist in the storage units or the storage blocks to be collected are obtained.

Referring to fig. 1 to 13, in an embodiment of the present invention, after the garbage collection process of the storage unit 30 is completed, the process returns to step S31 to re-determine whether the storage margin of the storage unit 30 is insufficient. Step S31 and step S32 are repeated until the number of empty white memory blocks 302 in the memory unit 30 is greater than or equal to the memory capacity threshold, and step S33 is performed. In step S33, if the storage unit 30 has the storage block 302 to be reclaimed, step S36 is performed. If there is no memory block 302 to be reclaimed in the memory unit 30, step S34 is executed to determine whether the memory block 302 to be reclaimed can be obtained. The step S34 and the step S35, and the step S27 involve the step of acquiring the memory block 302 to be reclaimed. The method for obtaining the storage block 302 to be recycled is consistent, and the invention is described herein in detail. Taking step S34 as an example, the step of acquiring the memory block 302 to be reclaimed includes steps S341 to S343.

Step S341, sequentially reading the memory blocks of the memory cells, and acquiring the problem memory pages in the memory blocks.

Step S342, judging whether the number of the problem memory pages in the memory block is larger than a reclamation threshold.

And S343, when the number of the problem memory pages is larger than the reclamation threshold, marking the corresponding memory block as the memory block to be reclaimed.

Referring to fig. 1 to 13, in one embodiment of the present invention, in step S341, and in step S27, when the number of error bits of the read memory page 303 exceeds the error correction threshold, the read memory page 303 is marked as a problem memory page. In the present embodiment, in step S27, the scanning process is to read each memory page 303 in the memory unit 30. In step S341, a partial memory page 303 is selected from the memory block 302 as the memory page 303 to be read. The selected memory pages 303 may be a plurality of memory pages 303 with specific numbers, and the memory pages 303 selected by each memory block 302 are the same in number and number. For example, memory pages 303 numbered 01, 02, and 03 are read from memory block 1, and memory pages 303 numbered 01, 02, and 03 are read from memory block 2. Wherein the number of selected memory pages 303 is set by the tester. The memory pages 303 read in step S341 may be determined by, for example, experimentally determining which memory pages 303 the series of products most likely receive read disturbances are at. In the present embodiment, the number of memory pages 303 read in the memory block 302 is greater than the reclamation threshold. For example, the reclamation threshold is 2, the number of memory pages 303 read is at least 3. In step S342, step S343, and step S27, in the memory block 302, when the number of problem memory pages is greater than the reclamation threshold, the corresponding memory block 302 is marked as a memory block 302 to be reclaimed.

Referring to fig. 1 to 13, in step S30, each garbage collection process takes a unit of a memory block 302, and defines the memory block 302 being collected or just collected as the current memory block 302. After the garbage collection process is completed on the storage block 302 to be collected, the mark of the storage block 302 to be collected is removed, and the storage block 302 to be collected is changed into a common blank storage block 302. In the garbage collection process for the memory block 302, valid data may be sequentially transferred in the order of the numbers of the memory pages 303. Step S41 is performed once every time one memory page 303 is reclaimed, or a plurality of memory pages 303 are reclaimed. If the host controller 20 does not receive the host command in step S41, the process returns to step S33 to collect garbage from the next memory block 302. If the host command is received, step S43 is executed to switch the storage device 10 to the operation mode. It should be noted that, in the case of having the mark to be recycled, it is not necessary to repeat the mark of the interrupt position of garbage collection. It should be noted that, the execution frequency of step S30 is much higher than the execution frequency of step S20. Therefore, step S34 can increase the frequency of acquiring the memory block 302 to be recycled, and also consider less resource occupation, thereby improving the data storage accuracy of the memory unit 30 and the lifetime of the memory device 10.

Referring to fig. 1 to 3 and fig. 11 to 14, in an embodiment of the present invention, the step of determining the recycling object is involved in the scanning process and the garbage recycling process. The reclamation object may be one or more memory pages 303 in the memory block 302, or may be the memory block 302. In another embodiment of the present invention, as shown in FIG. 14, a reclamation threshold is set. Wherein the reclamation threshold is used to define the number of problem memory pages 303 in each memory block 302. For example, the reclamation threshold is set to 2. When the number of the problem storage pages 303 is greater than 2, the storage block 302 where the problem storage pages 303 are located is directly marked as a storage block 302 to be recycled, and the whole storage block 302 to be recycled is recycled, so that the safety of data storage is improved.

Referring to fig. 1 to 14, in one embodiment of the present invention, in the scanning process, the scanning process flag is cleared, and the scanning interval duration does not reach the second duration threshold, which marks the end of the scanning process. In the garbage collection process, when the problem memory page 303 is not present in the memory unit 30 and the memory margin of the memory unit 30 is sufficient, the end of the garbage collection process is marked. In step S50, after the scanning process and the garbage collection process are ended, a preliminary sleep process is performed. Step S50 includes steps S51 to S55.

Step S51, transferring the address mapping information and the host data in the main controller to a storage unit.

Step S52, transferring the initialization data of the main controller to the sleep power-down-free area.

Step S53, judging whether the host controller receives a host command.

Step S54, when the host controller receives the host command, the storage device is switched from the idle mode to the working mode.

Step S55, when the host controller does not receive the host command, the storage device is switched from the idle mode to the sleep mode.

Referring to fig. 1 to 3, and fig. 8, 9 and 14, in step S51, the host data of the host controller 20 and the address mapping information corresponding to the host data are transferred to the storage unit 30 according to an embodiment of the present invention. In step S52, the initialization data corresponds to the start-up data required at the second initialization process. For example, the location of the data transfer prior to the power down of the region. In the second initialization process, data required for initialization may be directly acquired from the sleep non-power-down region 22, so that the second initialization process is completed quickly. After step S52, step S53 is performed. In step S53, it is determined whether the host controller 20 receives a host command. When the host controller 20 receives the host command, step S54 is performed to switch the storage device 10 to the operation mode, and then the control method provided in steps S10 to S50 is repeated. When the host controller 20 does not receive the host command, step S55 is executed, and the host command is not waited for, so as to directly switch the storage device 10 to the sleep mode, thereby saving energy consumption.

Referring to fig. 15, the present invention further provides an electronic device, which includes a processor 601 and a storage device 10, wherein the storage device 10 stores program instructions, and the processor 601 executes the program instructions to implement the control method of the storage device. The processor 601 is disposed in the host 60, and the processor 601 may be a general-purpose processor including a central processing unit (Central Processing Unit, abbreviated as CPU), a network processor (Network Processor, abbreviated as NP), and the like; but also digital signal processors (Digital Signal Processing, abbreviated as DSP), application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components; the Memory device 10 includes a random access Memory (Random Access Memory, simply referred to as RAM), and may also include a Non-Volatile Memory (Non-Volatile Memory), such as at least one magnetic disk Memory. The memory device 10 may also be an internal memory of the random access memory (Random Access Memory, RAM) type, and the processor 601, the memory device 10 may be integrated into one or more separate circuits or hardware, such as: an application specific integrated circuit (Application SpecificIntegrated Circuit, ASIC). It should be noted that the computer program in the storage device 10 may be implemented in the form of a software functional unit and may be stored in a computer readable storage medium when sold or used as a separate product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, an electronic device, or a network device, etc.) to perform all or part of the steps of the method of the various embodiments of the present invention.

Referring to fig. 16, the present invention further provides a computer readable storage medium 701, where the computer readable storage medium 701 stores computer instructions 70, and the computer instructions 70 are configured to cause a computer to execute the above-mentioned method for controlling a storage device. The computer readable storage medium 701 may be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system or propagation medium. The computer-readable storage media 701 may also include semiconductor or solid state memory, magnetic tape, removable computer diskette, random Access Memory (RAM), read-only memory (ROM), rigid magnetic disk and optical disk. Optical discs may include compact disc-read only memory (CD-ROM), compact disc-read/write (CD-RW), and DVD.

The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims

1. A memory device, comprising:

the storage unit comprises a plurality of storage blocks and a plurality of storage pages, wherein a problem page is acquired according to the number of error bits of the storage pages, and the storage blocks to be recycled are acquired according to the number of the problem pages;

the scanning detection module starts a scanning process of the storage unit and acquires the problem page and the storage block to be recycled when the storage device is in the idle mode and the scanning interval time of the storage device is longer than a second time threshold;

the garbage collection module starts a garbage collection process for the storage unit if the storage allowance in the storage unit is insufficient or the storage unit is provided with the storage block to be collected, wherein the garbage collection process is higher than the scanning process when the storage allowance of the storage unit is insufficient, the scanning process is higher than the garbage collection process when the allowance of the storage unit is sufficient, the selected source block is higher than the storage block to be collected in the garbage collection process for the storage unit, the priority of the selected source block is higher than that of the storage block to be collected in the garbage collection process for the storage unit, the priority of the storage block to be collected is higher than that of the storage block to be collected in the balanced abrasion condition, and the priority of the selected storage block is higher than that of the storage block with the least effective data number in the balanced abrasion condition; and

The main controller is electrically connected with the storage unit and the host, and is divided into a sleep power-down area and a sleep non-power-down area according to whether the device area of the main controller is powered down in the sleep mode.

2. The memory device of claim 1, wherein the scan detection module comprises a timing module electrically connected to the scan detection module and the mode switch module to output a first start signal and a second start signal to the scan detection module and to output the first start signal to the mode switch module.

3. The memory device of claim 2, wherein the timing module includes a command interval timing unit that starts timing and obtains a first timing duration when the operation of the host command is ended, and outputs the first start signal when the first timing duration reaches the first timing duration threshold.

4. The memory device according to claim 2, wherein the timing module includes a scan interval timing unit, the scan interval timing unit starts timing and obtains a second timing duration when a scan process of the memory unit is finished, and the timing module outputs the second start signal when the second timing duration reaches the second duration threshold.

5. The memory device of claim 2, wherein the scan detection module includes a scan process flag, wherein when the scan detection module receives the first enable signal and the second enable signal, the scan process flag is set and the scan process flag is stored in the memory device.

6. The memory device of claim 1, wherein the memory device comprises a recycling start module electrically connected to the garbage collection module, and the recycling start module outputs a third start signal to the garbage collection module when the number of empty memory blocks is less than a memory capacity threshold.

7. The storage device of claim 1, wherein the storage device includes a command query module, an execution time node of the command query module is configured to complete the scanning process for the storage block and to complete the garbage collection process for the storage block to be collected.

8. A memory device according to claim 1, characterized in that in the memory blocks, when the number of problem pages exceeds a reclamation threshold, the memory blocks are marked as memory blocks to be reclaimed.

9. A method for controlling a storage device, comprising the steps of:

in the idle mode, when the scanning interval time of the storage unit reaches a second duration threshold, enabling the scanning process of the storage unit, and acquiring a problem page according to the error bit number of the storage page;

in the idle mode, when the storage margin of the storage unit is insufficient or when the storage unit is provided with a storage block to be recycled, starting a garbage recycling process of the storage unit, wherein when the storage margin of the storage unit is insufficient, the priority of the garbage recycling process is higher than that of the scanning process, and when the storage unit margin is sufficient, the priority of the scanning process is higher than that of the garbage recycling process, wherein in the garbage recycling process of the storage unit, the selected source block has a priority that an unclosed storage block is higher than that of the storage block to be recycled, the priority of the storage block to be recycled is higher than that of the storage block selected under the condition of balanced abrasion, and the priority of the selected storage block under the condition of balanced abrasion is higher than that of the storage block with the least effective data number;

When the host command is received, the scanning process and the garbage collection process are interrupted, and the storage device is switched from the idle mode to the working mode; and

and the storage device comprises a main controller, and in the idle mode, when the scanning process and the garbage collection process are finished, the data of the main controller is transferred to the storage unit or the sleep non-power-down area, and the storage device is switched to a sleep mode.

10. The method of claim 9, wherein interrupting the scanning process comprises:

11. The method of claim 9, wherein interrupting the garbage collection process comprises:

12. The control method according to claim 9, wherein when a memory block to be reclaimed is not obtained in the scanning process, the memory blocks are sequentially read and a part of the memory pages in the memory blocks are read to obtain the memory block to be reclaimed before the garbage reclamation process is performed.