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CN116895611A - 裸晶封装、集成电路封装及其制造方法 - Google Patents

裸晶封装、集成电路封装及其制造方法 Download PDF

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Publication number
CN116895611A
CN116895611A CN202310300468.1A CN202310300468A CN116895611A CN 116895611 A CN116895611 A CN 116895611A CN 202310300468 A CN202310300468 A CN 202310300468A CN 116895611 A CN116895611 A CN 116895611A
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CN
China
Prior art keywords
package
die
passive component
semiconductor die
contact pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310300468.1A
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English (en)
Inventor
唐和明
卢超群
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Quanxin Semiconductor Heterointegration Co ltd
Etron Technology Inc
Original Assignee
Quanxin Semiconductor Heterointegration Co ltd
Etron Technology Inc
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Filing date
Publication date
Application filed by Quanxin Semiconductor Heterointegration Co ltd, Etron Technology Inc filed Critical Quanxin Semiconductor Heterointegration Co ltd
Publication of CN116895611A publication Critical patent/CN116895611A/zh
Pending legal-status Critical Current

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Abstract

一种裸晶封装包括一半导体裸晶、一被动元件、一模封化合物及一重布层。半导体裸晶包括一第一接触垫。被动元件包括一第二接触垫。模封化合物包覆半导体裸晶及被动元件。重布层配置于半导体裸晶及被动元件上方，其中重布层电性连接第一接触垫与第二接触垫。半导体裸晶与被动元件系垂直地重叠。

Description

裸晶封装、集成电路封装及其制造方法
技术领域
本发明是有关于一种裸晶封装、集成电路封装及其制造方法。
背景技术
请参照图1A～1C，其绘示习知技艺的多个半导体封装10、20及30的示意图。
如图1A所示，习知的功率调节(power regulation)解决方案基于高性能应用，需要许多分离元件在外部支援用覆晶(flip chip)键合于基板的处理器(processor)系统单芯片(System-On-Chip,SoC)11。在习知解决方案中，DC-DC功率转换器(power converter)或例如是降压转换器的稳压器将功率从高电压转换为低电压，以适用于各种使用功率转换元件的微电子应用(microelectronics applications)，其中功率转换元件包含是安装在印刷电路板15上且相距处理器SoC芯片11长距离的电源管理/控制IC(integratedcircuit)12、电源开关、大型电感器13及大型电容器14。由于热传导损耗(＝I2R，其中I是电流，R是线路电阻)，长距离会消耗功率转换器的功率，并在从印刷电路板到处理器的连线中产生显著的功率损耗，且大交流阻抗会导致处理器功耗动态变化，因此需要电源供应增益以确保足够高的电压实现处理器有效率地运作。
如第1B～1C图所示，关于共封装(co-packaging)在基板上的SoC芯片11与动态随机存取存储器(Dynamic Random-Access Memory,DRAM)21，此处的封装可以是如图1B所示基于BGA(ball grid array)的有机层压基板(organic laminate substrate)封装的并排(side-by-side)封装形式，或如图1C所示的堆叠裸晶封装(stacked-die packaging)，其中22表示重布层(redistribution layer,RDL)、23表示固化的裸晶附贴(die attach,DA)，而24表裸晶附贴膜(die attach film,DAF)。此处的封装也可以使用基于QFP(quad flatpack)的低成本金属导线架(leadframe)基板。图1B的重布层22用以将中央DRAM接触垫(bonding pad)重新布线到DRAM裸晶边缘，以缩短DRAM和SoC之间的导线距离，从而获得更好的性能。
除了图1A～1C所示的封装，堆叠封装(package-on-package,PoP)是另一传统封装，其具有安装在SoC封装的顶部的DRAM封装，而SoC封装又安装在印刷电路板上。裸晶之间及底部裸晶与层压基板之间的互连通常以焊料接合(solder bonding)实现。PoP广泛用于手机(cell phone)的封装应用处理器。通常，即使基于导线架的PoP可以在市面上买到，反而是层压基板较导线架常用于支持更高的数据速率。然而，PoP结构仍面临功率损耗及大的交流阻抗问题。
发明内容
根据一实施例，提供了一种裸晶封装。裸晶封装包括一半导体裸晶、一被动元件、一模封化合物及一重布层。半导体裸晶具有一第一接触垫。被动元件具有一第二接触垫。模封化合物包覆半导体裸晶及被动元件。重布层位于半导体裸晶及被动元件上方，其中重布层电性连接第一接触垫与第二接触垫。其中，半导体裸晶与被动元件系垂直地重叠。
根据另一个实施例，半导体裸晶的第一接触垫与被动元件的第二接触垫垫系垂直地重叠。
根据另一个实施例，裸晶封装更包括位于被动元件下方的一间隔件(spacer)，半导体裸晶的高度实质上等于被动元件的高度与间隔件的高度之和。
根据另一实施例，被动元件为一分离的电容、一分离的电感或一分离的电阻。
根据另一实施例，被动元件为分离的电感，且一共形屏蔽材料环绕分离的电感的至少一表面。
根据另一个实施例，裸晶封装，更包括一在半导体裸晶及被动元件下方的散热器，且半导体裸晶及被动元件透过一导热附贴材料附贴于散热器。
根据另一个实施例，提供了一种裸晶封装。裸晶封装包括一半导体裸晶、一被动元件、一模封化合物及一重布层。半导体裸晶具有一第一接触垫。被动元件具有一第二接触垫。模封化合物包覆半导体裸晶及被动元件。重布层位于半导体裸晶及被动元件上方，其中重布层电性连接第一接触垫与第二接触垫。其中，半导体裸晶与被动元件系水平地重叠。
根据另一个实施例，模封化合物包括一电性连接到第二接触垫与重布层的模通孔(through-mold via)。
根据另一个实施例，半导体裸晶附贴在被动元件上。
根据另一个实施例，裸晶封装更包括另一被动元件位于重布层上且接合于重布层。
根据另一个实施例，被动元件为一分离的电感，且一共形屏蔽(conformalshield)材料环绕分离的电感的至少一表面。
根据另一实施例，裸晶封装更包括一位于半导体裸晶及被动元件下方的散热器，且半导体裸晶及被动元件透过一导热附贴材料附贴于散热器
根据另一个实施例，提供了一种裸晶封装。裸晶封装包括一半导体裸晶、一被动元件、一模封化合物及一重布层。半导体裸晶具有一第一接触垫及一在半导体裸晶中的硅通孔。被动元件具有一第二接触垫。模封化合物包覆封装半导体裸晶。重布层位于半导体裸晶上方，其中重布层电性连接于第一接触垫。半导体裸晶具有一空腔(cavity)，被动元件位于空腔内，且第二接触垫与硅通孔电性连接。
根据另一个实施例，空腔位于半导体裸晶的一背面(backside)，使硅通孔透过空腔露出。
根据另一个实施例，裸晶封装更包括一填充在空腔的多个壁与被动元件的间的封装材料。
根据另一实施例，裸晶封装更包括一位于半导体裸晶及被动元件下方的散热器，且半导体裸晶及被动元件透过一导热附贴材料附贴于散热器。
根据另一个实施例，提供了一种IC封装。IC封装包括如上所述的裸晶封装以及一半导体元件。半导体元件布置于裸晶封装下方。
根据另一实施例，半导体元件为一系统单芯片(System-On-Chip,SoC)，SoC芯片透过多个焊料凸块电性连接于裸晶封装。
根据另一实施例，IC封装，更包括一位于SoC芯片下方的层压基板，SoC芯片透过一打线接合或一焊料接合电性连接于层压基板
根据另一个实施例，半导体元件是一SoC芯片，且裸晶封装的半导体芯片是一动态随机存取存储器(DRAM)芯片。
根据另一个实施例，半导体元件是另一如权利要求1、7或13所述的裸晶封装。
根据另一个实施例，裸晶封装的半导体芯片是一DRAM芯片，且半导体元件的半导体芯片是另一DRAM芯片。
根据另一个实施例，另一裸晶封装包括一硅通孔或一模通孔。
根据另一个实施例，裸晶封装透过多个焊料凸块直接接合到半导体元件。
根据另一个实施例，多个虚设凸块(dummy bump)位于裸晶封装与半导体元件之间。
根据另一个实施例，裸晶封装与半导体元件部分垂直地重叠，且一支撑间隔件(supporting spacer)位于裸晶封装下方且邻近半导体元件。
根据另一个实施例，提供了一种裸晶封装的制造方法。制造方法包括以下步骤：提供包括一第一接触垫的一半导体裸晶及包括一第二接触垫的一被动元件在一载体上，其中半导体裸晶与被动元件系垂直地重叠；以一重布层连接第一接触垫与第二接触垫；以及，形成一模封化合物包覆半导体裸晶及被动元件。
根据另一个实施例，提供了一种裸晶封装的制造方法。制造方法包括以下步骤：提供包括一第一接触垫的一半导体裸晶及包括一第二接触垫的一被动元件在一载体上，其中半导体裸晶与被动元件系水平地重叠；以一重布层连接第一接触垫与第二接触垫；以及，形成一模封化合物包覆半导体裸晶及被动元件。
根据另一个实施例，提供了一种裸晶封装的制造方法。制造方法包括以下步骤：提供包括一第一接触垫及一硅通孔的一半导体裸晶在一载体上，其中半导体裸晶具有一空腔，被动元件位于空腔内，且被动元件包括一第二接触垫电性连接于硅通孔；以一重布层连接第一接触垫；以及，形成一模封化合物包覆半导体裸晶。
在阅读了以下各种附图中所示的优选实施例的详细描述之后，本发明的这些目标对于本领域中具有通常知识者来说无疑将变得显而易见。
附图说明
图1A～1C绘示习知技艺的多个半导体封装的示意图。
图2A绘示依照本发明一实施例的裸晶封装的示意图。
图2B绘示本发明另一实施例的裸晶封装的示意图。
图3绘示本发明另一实施例的裸晶封装的示意图。
图4绘示本发明另一实施例的裸晶封装的示意图。
图5绘示本发明另一实施例的裸晶封装的示意图。
图6绘示本发明另一实施例的裸晶封装的示意图。
图7绘示本发明另一实施例的IC封装的示意图。
图8绘示本发明另一实施例的IC封装的示意图。
图9绘示本发明另一实施例的IC封装的示意图。
图10绘示本发明另一实施例的IC封装的示意图。
图11A～11F绘示导致图2A的裸晶封装的制造过程的示意图。
图12A～12F绘示导致图2B的裸晶封装的制造过程的示意图。
图13A～13F绘示导致图2A的裸晶封装的制造过程的示意图。
图14A～14G绘示导致图6的半导体裸晶及被动元件整合成单件的制造过程示意图。
附图标记说明
1,3,280:载体
2,270:离型层
10,11,20,30:半导体封装
12:电源管理/控制
13:大型电感器
14:大型电容器
15:印刷电路板
21:动态随机存取存储器
22,130,621,721,922:重布层
23:芯片附贴
24:芯片附贴膜
100,100′,200,300,400,500:裸晶封装
110,510:半导体裸晶
110u,120u,140u,220u,320u,513u:第一表面
110b,120b,140b,513b:第二表面
110s:第一侧面
111,511:第一接触垫
112,133,516:保护层
112a:开口
120,220,320,520:被动元件
120s:第二侧面
121,321,521:第二接触垫
122:电极
131:介电层
131a,133a:开口
132:导电层
134:导电垫
140,140′,650:模封化合物
150,630:接点
155:虚设焊料凸块
260:间隔件
261,263:芯片附贴膜
262:间隔物
390,512,722,921:导电通孔
480:电子元件
490,660,760,970:底部填充物
510r:空腔
513:硅基板
513a:孔洞
514:FEOL层
515:BEOL层
516a:开口
530:封装材料
600,700,800,900:IC封装
610,724:基板
620,820,920:半导体元件
640:线
670:芯片附贴
740:焊料凸块
723:第二重布层
720,920:半导体元件
890:间隔件
H1,H21,H22:高度
SP1:空间
C1:切割道
具体实施方式
在下文的实施方式中，出于解释的目的，阐述了许多具体细节以便提供对所揭示的实施例的透彻理解。然而，显而易见的是可以在没有这些具体细节的情况下实施一个或多个实施例。在其他情况下，为了简化附图，示意性地绘示已知的结构和装置。
图2A绘示依照本发明一实施例的裸晶封装100的示意图，图2B绘示本发明另一实施例的裸晶封装100′的示意图。
如图2A所示，裸晶封装100包括至少一半导体裸晶110、至少一个被动元件120、重布层130、模封化合物(molding compound)140及至少一接点(contact)150。半导体裸晶110具有至少一第一接触垫(bonding pad)111。被动元件120具有至少一第二接触垫121。模封化合物140包覆半导体裸晶110及被动元件120。重布层130配置在半导体裸晶110及被动元件120上方。重布层130电性连接第一接触垫111与第二接触垫121。由于垂直于一垂直轴(例如，在裸晶上或封装厚度方向上的z轴)的不同水平线穿过半导体裸晶110与被动元件120二者，半导体裸晶110垂直地重叠于被动元件120。在另一视角中，半导体裸晶110与被动元件120水平间隔开来。在RDL制程中，被动元件120尽可能地靠近半导体裸晶110配置，因此可以有效地降低杂讯(noise)且可显著减小裸晶封装100的尺寸(长度、宽度及厚度)。
在本实施例中，半导体裸晶110可以是例如DRAM、SoC芯片、电源管理IC(PowerManagement IC,PMIC)、整合稳压器(Integrated Voltage Regulator,IVR)等。
如图2A所示，半导体裸晶110还具有第一表面110u、相对于第一表面110u反面的第二表面110b以及第一侧面110s，而被动元件120具有第一表面120u反面、相对于第一表面120u的第二表面120b及第二侧面120s。模封化合物140包围(或模装)半导体裸晶110的第一侧面110s及被动元件120的第二侧面120s，并露出半导体裸晶110的第一表面110u和被动元件的第一表面120u。重布层130形成于第一表面110u及第一表面120u上。
如图2A所示，半导体裸晶110更包括一保护层(passivation layer)112，保护层112具有一露出第一接触垫111的开口112a。
如图2A所示，被动元件120可以是分离的(discrete)电容、分离的电感或分离的电阻。被动元件120更包括至少一电极122。在一实施例中，电极122形成于被动元件120的相对二侧。二电极122分别电性连接二第二接触垫121。被动元件120透过第二接触垫121电性连接重布层130。在本实施例中，被动元件120例如为多层陶瓷电容(Multi-Layer CeramicCapacitor,MLCC)。
如图2A所示，重布层130延伸超出半导体裸晶110的第一侧面110s及被动元件120的第二侧面120s，以形成扇出结构(fan-out structure)。重布层130可包括至少一介电层131、至少一导电层132、至少一保护层133及至少一导电垫134。介电层131形成于模封化合物140上且具有多个露出半导体裸晶110的第一接触垫111的开口131a。导电层132形成于介电层131上且横向(或侧向)延伸超出半导体裸晶110的第一侧面110s及被动元件120的第二侧面120s。导电层132进一步延伸至开口131a，以电性连接半导体裸晶110与被动元件120。保护层133覆盖导电层132及至少一露出导电层132的开口133a。各导电垫134形成于对应的开口133a内，以透过对应的开口133a电性连接于导电层132。此外，导电垫134包括一第一层1341及一第二层1342，其中第一层例如由钛(titanium)、钛/钨(titanium/tungsten)或镍-钒(nickel-vanadium)等材料形成，而第二层例如由铜、镍、钯、金或其组合等材料形成。导电垫134用于焊线接合(wire-bonding)或覆晶接合封装(flip chip assembly)。
如图2A所示，多个接点150例如是焊球(solder ball)、导电柱(conductivepillar)、导电凸块(conductive bump)等。各接点150形成在对应的导电垫134上。在另一实施例中，多个接点150可以是微型柱体(micro-pillar)或微型金属垫(micro-metal-pad)，并且相对地可增大或减小接点150的尺寸。
如图2A所示，模封化合物140可以由环氧树脂(epoxy)、树脂(resin)、可模塑聚合物(moldable polymer)等形成。模封化合物140可在基本上呈液态时被施加，然后可透过化学反应固化，例如在环氧树脂或树脂中。在一些实施例中，模封化合物140可以是紫外线(ultraviolet)或热固化聚合物，其可以胶状(gel)或可延展固体(malleable solid)形式配置在半导体裸晶周围，然后可透过紫外线或热固化工艺进行固化。模封化合物140可透过各种封装技术形成，例如是压缩成型(compression molding)、注射成型(injectionmolding)或移转成型(transfer molding)。
如图2A所示，第一表面140u、第一表面110u与第一表面120u实质上彼此对齐(例如齐平)。此外，模封化合物140更覆盖于半导体裸晶110的第二表面110b与被动元件120的第二表面120b。然而，此非用以限制本发明实施例。
如图2B所示，裸晶封装100′包括至少一半导体裸晶110、至少一个被动元件120、重布层130、模封化合物140′及至少一接点150。裸晶封装100′包括类似或同于裸晶封装100的技术特征，除了模封化合物140′露出半导体裸晶110的第二表面110b及被动元件120的第二表面120b外。模封化合物140′具有与第一表面140u相对的第二表面140b，其中第二表面110b、第二表面120b与第二表面140b透过研磨制程(grinding process)彼此基本对齐。
图3绘示本发明另一实施例的裸晶封装200的示意图。
如图3所示，裸晶封装200包括至少一半导体裸晶110、至少一被动元件220、重布层130、模封化合物140、至少一接点150、间隔件(spacer element)260、离型层(releaselayer)270及载体280。裸晶封装200包括类似或同于裸晶封装100的技术特征，除了被动元件220与半导体裸晶110在高度上不同外，且裸晶封装200更包括间隔件260、离型层270及载体280。
如图3所示，间隔件260配置于被动元件220下方，用以提高被动元件220的高度，使半导体裸晶110的第一表面110u与被动元件220的第一表面220u位于同一水平面上。此外，半导体裸晶110的高度H1实质上等于被动元件220的高度H21与间隔件260的高度H22的总和。在一实施例中，间隔件260例如包括一芯片附贴膜261、间隔物262及芯片附贴膜263，其中间隔物262配置于芯片附贴膜261与芯片附贴膜263之间。
如图3所示，离型层270配置于载体280与模封化合物140之间。离型层270例如为离型层或离型/黏着(adhesive)层。载体280例如是玻璃载体。
图4绘示本发明另一实施例的裸晶封装300的示意图。
如图4所示，裸晶封装300包括至少一半导体裸晶110、至少一被动元件320、重布层130、模封化合物140、至少一接点150、离型层270、载体280及至少一导电通孔390。裸晶封装300包括与裸晶封装100相似或相同的特征，除了被动元件320(如图4所示)及被动元件120(如图2A所示)不同且裸晶封装300更包括至少一个导电通孔390。
如图4所示，半导体裸晶110附贴在(attach)被动元件320上。由于垂直于水平轴(例如，x轴)的不同垂直线穿过半导体裸晶110与被动元件320，半导体裸晶110与被动元件320系水平地重叠。在另一视角中，半导体裸晶110与被动元件320垂直地间隔开来。
如图4所示，被动元件320例如是一分离的电感。被动元件320包括至少一第二接触垫321并具有第一表面320u。第二接触垫321形成于第一表面320u上且相对第一表面320u突出。
如图4所示，各导电通孔390例如是模通孔(Through Mold Via,TMV)。各导电通孔390由第一表面140u延伸至被动元件320。多个导电通孔390电性连接第二接触垫321与重布层130。重布层130形成在模封化合物140的第一表面140u及半导体裸晶110上且透过重布层130的导电层132电性连接于导电通孔390及半导体裸晶110的第一接触垫111。半导体裸晶110及被动元件320透过重布层130及导电通孔390电性连接。
在另一实施例中，裸晶封装300更包括共形屏蔽材料(conformal shieldmaterial)(未绘示)，其至少包围被动元件320的一表面。
在另一实施例中，裸晶封装300更包括位于半导体裸晶110及被动元件320下方的散热器(heat spreader)(未绘示)，其中半导体裸晶110及被动元件320透过至少一导热附贴材料(thermal conducting die attach material)(未绘示)附贴于散热器。
图5绘示本发明另一实施例的裸晶封装400的示意图。
如图5所示，裸晶封装400包括至少一半导体裸晶110、至少一被动元件320、重布层130、模封化合物140、至少一接点150、离型层270、载体280、至少一导电通孔390、至少一电子元件480及底部填充物(underfill)490。裸晶封装400包括与裸晶封装300相似或相同的特征，除了裸晶封装400更包括至少一电子元件480及底部填充物490。在裸晶朝上(如第12B12图所示)的情况下，被动元件320先接合(bonded)到离型层270，然后半导体裸晶110再附贴到被动元件320。导电通孔390系在模封(molding)及模塑研磨(mold grinding)后透过雷射穿孔形成技术(laser via hole formation)、钛/铜种子层沉积、铜电镀及以聚合物及导电材料(例如焊料(solder))填塞穿孔(via hole)而形成。
如图5所示，电子元件480例如是另一被动元件或主动芯片(active chip)。电子元件480透过至少一接点150接合到重布层130。底部填充物490形成在电子元件480与重布层130之间且封装多个接点150以保护接点150。
在另一实施例中，裸晶封装400更包括共形屏蔽材料(未绘示)，其包覆被动元件320的至少一表面。
在另一实施例中，裸晶封装400更包括位于半导体裸晶110及被动元件320下方的散热器(未绘示)，其中半导体裸晶110及被动元件320透过一导热附贴材料(conductingdie attach material)(未绘示)附贴于散热器。
图6绘示本发明另一实施例的裸晶封装500的示意图。裸晶封装500包括至少一半导体裸晶510、至少一被动元件520、重布层130、模封化合物140、离型层270及载体280。裸晶封装500包括与裸晶封装200类似或相同的特征，除了半导体裸晶510与被动元件520整合为一体之外。如此，被动元件520可尽可能地靠近半导体裸晶510设置，以有效地降低杂讯，且裸晶封装500的尺寸(长度、宽度及厚度)可显著地缩小。
如图6所示，半导体裸晶510包括半导体裸晶510中的至少一第一接触垫511及至少一个导电通孔512。被动元件520包括至少一第二接触垫521。模封化合物140包覆半导体裸晶510。重布层130配置在半导体裸晶510上方且电性连接于第一接触垫511。半导体裸晶510具有一空腔510r，被动元件520位于空腔510r中，第二接触垫521电性连接于导电通孔512。
导电通孔512例如是硅通孔(Through Silicon Via,TSV)。半导体裸晶510更包括硅基板513、前端制程(Front-End-of-the-Line,FEOL)层514、后端制程(Back-End-of-the-Line,BEOL)层515及保护层516。导电通孔512可从BEOL层515延伸到空腔510r，于将被动元件520电性连接到BEOL层515。硅基板513具有第一表面513u以及与第一表面513u相对的第二表面513b。BEOL层515及FEOL层514形成在硅基板513上及内部。保护层516覆盖BEOL层515且具有至少一个开口516a露出第一接触垫511。
如图6所示，空腔510r位于半导体裸晶510的背面，使导电通孔512透过空腔510r露出。此外，空腔510r从第二表面513b往第一表面513u延伸，但未一路延伸至第一表面513u。
如图6所示，裸晶封装500更包括封装材料(encapsulating material)530，其填满在空腔510r的多个壁与被动元件520之间。
在另一实施例中，裸晶封装500更包括在被动元件320下方的散热器(未绘示)，其中被动元件320透过导热附贴材料(未绘示)附贴于散热器。
图7绘示本发明另一实施例的IC封装600的示意图。
IC封装600包括裸晶封装100、基板610、半导体元件620、至少一接点630、至少一金属线640、模封化合物650、底部填充物660及芯片附贴(die attach)670。半导体元件620配置在裸晶封装100下方。在另一实施例中，裸晶封装100或半导体元件620可以是裸晶封装200～500中任何一者。
基板610例如是层压基板。基板610配置于半导体元件620下方，半导体元件620透过至少一金属线640电性连接基板610。
如图7所示，半导体元件620例如是DRAM、SoC芯片等。半导体元件620透过至少一接点150(例如，焊料凸块(solder bump))电性连接至裸晶封装100。裸晶封装100的半导体裸晶(未绘示)例如是DRAM芯片。
如图7所示，半导体元件620透过芯片附贴670配置在基板610上，并透过金属线640电性连接到基板610。裸晶封装100透过接点150配置在半导体元件620上并电性连接于半导体元件620。此外，半导体元件620包括一重布层621，并且裸晶封装100通过多个接点150电性连接于半导体元件的重布层621。在本实施例中，裸晶封装100更包括至少一虚设焊料凸块(dummy solder bump)155，其配置于裸晶封装100与半导体元件620之间。当裸晶封装100堆叠于半导体元件620上时，虚设焊料凸块155可提高接合良率及可靠性。
如图7所示，底部填充物660形成在裸晶封装100与半导体元件620之间形成且封装多个接点150。模封化合物650形成在基板610上且包覆裸晶封装100、半导体元件620、金属线640及底部填充物660。在另一实施例中，裸晶封装100或半导体元件720可以是裸晶封装100～500中任一者。
图8绘示本发明另一实施例的IC封装700的示意图。
IC封装700包括基板610、半导体元件720、至少一接点630、至少一焊料凸块740、底部填充物660、底部填充物760及裸晶封装100。在另一实施例中，裸晶封装100或半导体元件720可以是裸晶封装100～500中任何一者。
半导体元件720例如是DRAM、SoC芯片等。半导体元件720设置于基板610上并透过焊料凸块740电性连接于基板610。此外，半导体元件720包括第一重布层721、至少一导电通孔722、一第二重布层723及一基板724。第一重布层721与第二重布层723形成于基板724的相对二侧，并透过导电通孔722电性连接。导电通孔722例如是TSV。第二重布层723电性连接到焊料凸块740，使半导体元件720透过第二重布层723电性连接到基板610。裸晶封装100配置在半导体元件720上并透过多个接点150电性连接于半导体元件720。底部填充物760在半导体元件720与基板610之间形成且封装多个焊料凸块740。
图9绘示本发明另一实施例的IC封装800的示意图。
IC封装800包括基板610、半导体元件620、至少一个接点630、至少一个金属线640、模封化合物650、至少一芯片附贴670、半导体元件820、间隔物890及裸晶封装100。在另一实施例中，裸晶封装100、半导体元件620及半导体元件820可由裸晶封装100～500中一者取代。
半导体元件820例如是另一裸晶封装，例如是裸晶封装100～500的一者。裸晶封装100及半导体元件820可在裸晶封装100的半导体裸晶110(未绘示)是一DRAM芯片而半导体元件820的半导体裸晶110(未绘示)是另一DRAM芯片下，加倍储存容量。
裸晶封装100透过金属接合线(metal bonding wire)640电性连接于半导体元件620(或与基板610)，且半导体元件820透过金属接合线640电性连接于基板610及/或半导体元件620。半导体元件820配置在裸晶封装100下方。裸晶封装100及半导体元件820在x-y平面中错位(shifted)且在基板610及裸晶封装100下方形成空间SP1。间隔件890配置在空间SP1内，以使用芯片附贴材料支撑裸晶封装100。如此，当金属线640接合至裸晶封装100时，可避免裸晶封装100发生位移。
图10绘示本发明另一实施例的IC封装900的示意图。
IC封装900包括基板610、半导体元件620、至少一接点630、至少一个接合线640、模封化合物650、至少一芯片附贴670、底部填充物970、裸晶封装100及半导体元件920。在另一实施例中，裸晶封装100、半导体元件620及/或半导体元件920可由裸晶封装100～500中一者取代。
裸晶封装100及/或半导体元件920可以是DRAM芯片与被动元件二合为一，如裸晶封装100至500所示。因此，裸晶封装100及半导体元件920可在裸晶封装100的半导体裸晶(未绘示)是一DRAM芯片而半导体元件920的半导体裸晶(未绘示)是另一DRAM芯片下，加倍储存容量。
裸晶封装100透过裸晶封装100的接点150配置在半导体元件920上。底部填充物970在裸晶封装100与半导体元件920之间形成并封装多个接点150。半导体元件920包括与裸晶封装100相同或相似特征，除了半导体元件920更包括至少一导电通孔921及重布层922外，其中导电通孔921可从重布层922延伸至重布层130。导电通孔921例如是TSV或TMV。裸晶封装100与半导体元件920彼此电性连接。例如，裸晶封装100的重布层130与半导体元件920的重布层922电性连接。裸晶封装100透过至少一接点150(例如是焊料凸块)直接接合至半导体元件920。此外，至少一虚设焊料凸块155位于裸晶封装100与半导体元件920之间。
图11A～11F绘示导致图2A的裸晶封装100的制造过程的示意图。在本实施例中，此制程被称为「晶面朝下(face down)的芯片先(chip-first)制程」。
如图11A所示，提供其上设置有离型层2的载体1。
如图11B所示，至少一半导体裸晶110与至少一被动元件120透过离型层2配置于载体1上。在本实施例中，半导体裸晶110以「晶面朝下(face-down)」方位耦接至离型层2。
如图11C所示，在载体上形成模封化合物140，模封化合物140封装半导体裸晶110的第一侧面及被动元件120的第二侧面。
如图11D所示，移除载体1及离型层2，以露出半导体裸晶110的第一接触垫111、被动元件120的第二接触垫121与模封化合物140的第一表面140u。
如图11E所示，形成重布层130于模封化合物140的表面140u上，其中重布层130电性连接露出的第一接触垫111与露出的第二接触垫121。然后，至少一接点150形成在重布层130上。
如图11F所示，形成多个切割道(singulation path)C1通过模封化合物140及重布层130，以建立至少一裸晶封装100。使用合适切割工具(dicing tool)形成切割道C1。
请参照图12A～12F，其绘示是图2B的裸晶封装100′的制造过程的示意图。在本实施例中，此制程被称为「晶面朝上(face up)的芯片先(chip-first)制程」。
如图12A所示，提供其上设置有离型层2的载体1。
如图12B所示，至少一半导体裸晶110及至少一被动元件120透过离型层2配置于载体1上。在本实施例中，半导体裸晶110以「晶面朝上(face-up)」方位耦接至离型层2。
如图12C所示，在载体上以模封化合物140封装半导体裸晶110的第一侧面及被动元件120的第二侧面。
如图12D所示，在模封化合物140的表面140u上形成重布层130，其中重布层130电性连接露出的第一接触垫111与露出的第二接触垫121。
如图12E所示，在重布层130上形成至少一接点150。
如图12F所示，在移除载体1后，形成多个穿过模封化合物140与重布层130的切割道C1，以形成至少一裸晶封装100′。使用合适切割工具形成切割道C1。
请参照图13A～13F，其绘示导致图2A的裸晶封装100的制造过程的示意图。在本实施例中，此制程被称为「晶面朝下(face down)的后芯片(chip-last)制程」。
如图13A所示，提供其上设置有离型层2的载体1。
如图13B所示，通过离型层2在载体1上形成重布层130。在本制程中，重布层130例如为聚酰亚胺/铜基(polyimide/copper based)RDL膜。
如图13C所示，至少一半导体裸晶110及至少一被动元件120使用例如具有底部填充物的焊料凸块接合到重布层130。在本实施例中，半导体裸晶110以「晶面朝下(face-down)」方位耦接至重布层130。
如图13D所示，在重布层130上形成模封化合物140，其中模封化合物140封装半导体裸晶110的第一侧面及被动元件120的第二侧面。
如图13E所示，移除载体1及离型层2，以露出重布层130。然后，在露出的重布层130上形成至少一接点150。
如图13F所示，形成多个穿过模封化合物140与重布层130的切割道C1，以建立至少一裸晶封装100。使用合适切割工具形成切割道C1。
裸晶封装200至500的制造过程与裸晶封装100的制造过程类似，在此不再赘述。
请参照图14A～14G，其绘示图6的半导体裸晶510及被动元件520整合成单件的制造过程示意图。
如图14A所示，提供具有至少一孔洞513a的硅基板513。硅基板513，例如晶圆。硅基板513具有第一表面513u及相对第一表面513u的第二表面513b。各孔洞513a从第一表面513u往第二表面513b延伸，但并未一直延伸至第二表面513b。各孔洞513a例如是盲孔。
如图14B所示，用导电材料填满孔洞513a，以形成导电通孔512。
如图14C所示，在硅基板513内形成FEOL层514。
如图14D所示，在硅基板513的第一表面513u上形成FEOL层514并形成BEOL层515耦接至导电通孔512，接着在BEOL层515上形成至少一第一接触垫511。然后，形成保护层516于第一表面513u上，保护层516具有至少一开口516a，其露出对应的第一接触垫511。
如图14E所示，将图14D的结构透过离型层4配置在载体3上，然后形成从第二表面513b延伸至导电通孔512的空腔510r，空腔510r露出导电通孔512。
如图14F所示，配置至少一被动元件520配置于空腔510r内，其中被动元件520的第二接触垫521电性分别连接于导电通孔512。
如图14G所示，在空腔510r内形成包覆被动元件520的封装材料530，以结合半导体裸晶510与被动元件520。接着，移除载体3与离型层4。
综上，本发明实施例提供一种裸晶封装、集成电路封装及其制造方法。在一实施例中，裸晶封装包括半导体裸晶、被动元件及重布层。半导体裸晶及被动元件在重布层制程中以重布层连接。如此，被动元件可尽可能地靠近半导体裸晶配置，从而可有效地降低杂讯，并可显著地缩小裸晶封装的尺寸(长度、宽度及厚度)。
对于本发明所属技术领域中具有通常知识者来说显而易见的是，可以对所揭露的实施例进行各种修改和变化。本文所示的说明书和范例仅用于示例，本揭露的真实范围由所附权利要求及其均等物为准。

Claims (29)

1.一种裸晶封装，其特征在于，包括：
一半导体裸晶，具有一第一接触垫；
一被动元件，具有一第二接触垫；
一模封化合物，包覆该半导体裸晶及该被动元件；以及
一重布层，位于该半导体裸晶及该被动元件上方，其中该重布层电性连接该第一接触垫与该第二接触垫；
其中，该半导体裸晶与该被动元件系垂直地重叠。
2.如权利要求1所述的裸晶封装，其特征在于，该半导体裸晶的该第一接触垫与该被动元件的该第二接触垫系垂直地重叠。
3.如权利要求1所述的裸晶封装，其特征在于，更包括位于该被动元件下方的一间隔件，该半导体裸晶的高度实质上等于该被动元件的高度与该间隔件的高度之和。
4.如权利要求1所述的裸晶封装，其特征在于，该被动元件为一分离的电容、一分离的电感或一分离的电阻。
5.如权利要求4所述的裸晶封装，其特征在于，该被动元件为该分离的电感，且一共形屏蔽材料绕该分离的电感的至少一表面。
6.如权利要求1所述的裸晶封装，其特征在于，更包括一在该半导体裸晶及该被动元件下方的散热器，且该半导体裸晶及该被动元件透过一导热芯片附贴材料附贴于该散热器。
7.一种裸晶封装，其特征在于，包括：
一半导体裸晶，具有一第一接触垫；
一被动元件，具有一第二接触垫；
一模封化合物，包覆该半导体裸晶及该被动元件；以及
一重布层，位于该半导体裸晶及该被动元件上方，其中该重布层电性连接该第一接触垫与该第二接触垫；
其中，该半导体裸晶与该被动元件系水平地重叠。
8.如权利要求7所述的裸晶封装，其特征在于，该模封化合物包括一电性连接到该第二接触垫与该重布层的模通孔。
9.如权利要求8所述的裸晶封装，其特征在于，该半导体芯片附贴在该被动元件上。
10.如权利要求7所述的裸晶封装，其特征在于，更包括另一被动元件位于该重布层上方且接合于该重布层。
11.如权利要求7所述的裸晶封装，其特征在于，该被动元件为一分离的电感，且一共形屏蔽材料环绕该分离的电感的至少一表面。
12.如权利要求7所述的裸晶封装，其特征在于，更包括一位于该半导体裸晶及该被动元件下方的散热器，且该半导体裸晶及该被动元件透过一导热芯片附贴材料附贴于该散热器。
13.一种裸晶封装，其特征在于，包括：
一半导体裸晶，具有一第一接触垫及一在该半导体裸晶中的硅通孔；
一被动元件，具有一第二接触垫；
一模封化合物，包覆该封装半导体裸晶；以及
一重布层，位于该半导体裸晶上方，其中该重布层电性连接于该第一接触垫；
其中，该半导体裸晶具有一空腔，该被动元件位于该空腔内，且该第二接触垫与该硅通孔电性连接。
14.如权利要求13所述的裸晶封装，其特征在于，该空腔位于该半导体裸晶的一背面，使该硅通孔透过该空腔露出。
15.如权利要求14所述的裸晶封装，其特征在于，更包括一填充在该空腔的多个壁与该被动元件之间的封装材料。
16.如权利要求13所述的裸晶封装，其特征在于，更包括一位于该半导体裸晶及该被动元件下方的散热器，且该半导体裸晶及该被动元件透过一导热芯片附贴材料附贴于该散热器。
17.一种IC封装，其特征在于，包括：
一如权利要求1、7或13所述的裸晶封装；以及
一半导体元件，位于该裸晶封装下方。
18.如权利要求17所述的IC封装，其特征在于，该半导体元件为一系统单芯片，该SoC芯片透过多个焊料凸块电性连接于该裸晶封装。
19.如权利要求18所述的IC封装，其特征在于，更包括一位于该SoC芯片下方的层压基板，该SoC芯片透过一打线接合或一焊料接合电性连接于该层压基板。
20.如权利要求17所述的IC封装，其特征在于，该半导体元件是一SoC芯片，且该裸晶封装的该半导体裸晶是一动态随机存取存储器芯片。
21.如权利要求17所述的IC封装，其特征在于，该半导体元件是另一如权利要求1、7或13所述的裸晶封装。
22.如权利要求21所述的IC封装，其特征在于，该裸晶封装的该半导体裸晶是一DRAM芯片，且该半导体元件的该半导体裸晶是另一DRAM芯片。
23.如权利要求21所述的IC封装，其特征在于，该另一裸晶封装包括一硅通孔或一模通孔。
24.如权利要求21所述的IC封装，其特征在于，该裸晶封装透过多个焊料凸块直接接合到该半导体元件。
25.如权利要求21所述的IC封装，其特征在于，多个虚设凸块位于该裸晶封装与半导体元件之间。
26.如权利要求21所述的IC封装，其特征在于，该裸晶封装与该半导体元件部分垂直地重叠，且一支撑间隔件位于该裸晶封装下方且邻近该半导体元件。
27.一种裸晶封装的制造方法，其特征在于，包括：
提供包括一第一接触垫的一半导体裸晶及包括一第二接触垫的一被动元件在一载体上，其中该半导体裸晶与该被动元件系垂直地重叠；
以一重布层连接该第一接触垫与该第二接触垫；以及
形成一模封化合物包覆该半导体裸晶及该被动元件。
28.一种裸晶封装的制造方法，其特征在于，包括：
提供包括一第一接触垫的一半导体裸晶及包括一第二接触垫的一被动元件在一载体上，其中该半导体裸晶与该被动元件系水平地重叠；
以一重布层连接该第一接触垫与该第二接触垫；以及
形成一模封化合物包覆该半导体裸晶及该被动元件。
29.一种裸晶封装的制造方法，其特征在于，包括：
提供包括一第一接触垫及一硅通孔的一半导体裸晶在一载体上，其中该半导体裸晶具有一空腔，该被动元件位于该空腔内，且该被动元件包括一第二接触垫电性连接于该硅通孔；
以一重布层连接该第一接触垫；以及
形成一模封化合物包覆该半导体裸晶。
CN202310300468.1A 2022-03-29 2023-03-24 裸晶封装、集成电路封装及其制造方法 Pending CN116895611A (zh)

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