CN116884978A - Array substrate, display panel and display device - Google Patents

Abstract

The invention relates to an array substrate, a display panel and a display device. The array substrate comprises a substrate and a first insulating layer positioned on one side of the substrate; the first wiring and the second wiring are both positioned on the first surface of one side of the first insulating layer, which is far away from the substrate; the second insulating layer covers the first surface of the first insulating layer, the surface of the first wiring and the surface of the second wiring, and the second insulating layer is an inorganic layer; the first wire comprises a first wire segment, the second wire comprises a second wire segment, the first wire segment and the second wire segment are overlapped in the second direction, the distance between the first wire segment and the second wire segment is smaller than or equal to a short-circuit distance threshold value, the first surface of the first insulating layer comprises at least one section of slope surface, the slope surface extends along the first direction, and the slope surface is located between the first wire segment and the second wire segment. The embodiment of the invention can avoid the short circuit of the first wiring and the second wiring by the metal oxide, and improve the display quality.

Description

Array substrate, display panel and display device

Technical field

The present invention relates to the field of display technology, and in particular, to an array substrate, a display panel and a display device.

Background technique

With the development of display technology, the requirements for display quality are getting higher and higher. Thin film transistor liquid crystal displays have become the first choice in the development of display devices due to their advantages such as high definition, true color video display, thin and light appearance, low power consumption and no radiation pollution. Mainstream trends.

The core of the manufacturing technology of the array substrate of the thin film transistor liquid crystal display is the photolithography process. The photolithography process is not only an important link in determining product quality, but also a key part that affects product costs. Reducing the photolithography process can greatly reduce production costs. Currently, in order to reduce the photolithography process, an inorganic insulating layer is prepared on the wiring during the preparation process of some array substrates. The inorganic insulating layer is usually deposited using a chemical vapor deposition process, but the chemical vapor deposition process will oxidize the wiring and produce metal oxide, causing adjacent wiring to short-circuit, resulting in poor display.

Contents of the invention

The invention provides an array substrate, a display panel and a display device to prevent adjacent lines from being short-circuited due to the chemical vapor deposition process and improve display quality.

In a first aspect, an embodiment of the present invention provides an array substrate, including:

a base substrate and a first insulating layer located on one side of the base substrate;

The first traces and the second traces are both located on the first surface of the first insulating layer away from the base substrate. A plurality of the first traces extend along the first direction and extend along the second direction. arranged, the plurality of second traces extend along the first direction and are arranged along the second direction, and the first direction intersects with the second direction;

A second insulating layer covers the first surface of the first insulating layer, the surface of the first wiring, and the surface of the second wiring, where the second insulating layer is an inorganic layer;

Wherein, the first trace includes a first trace segment, the second trace includes a second trace segment, and in the second direction, the first trace segment overlaps the second trace segment, so The distance between the first trace segment and the second trace segment is less than or equal to the short circuit distance threshold, and the first surface of the first insulating layer includes at least a slope, and the slope is along the first slope. Extends in one direction and is located between the first wiring segment and the second wiring segment.

In a second aspect, embodiments of the present invention further provide a display panel, including the array substrate described in the first aspect.

In a third aspect, an embodiment of the present invention further provides a display device, including the display panel described in the second aspect.

Compared with the existing technology, the technical solution provided by the embodiment of the present invention has the following advantages:

The technical solution provided by the embodiment of the present invention is to provide at least one section between the first trace section of the first trace and the second trace section of the second trace for the first trace and the second trace extending in the same direction. Slope, and the distance between the first trace segment and the second trace segment is less than or equal to the short distance threshold, the slope is the same as the extension direction of the first trace or the second trace, that is, the slope faces the first trace segment Or the second trace segment setting. Therefore, the metal oxide produced by the chemical vapor deposition process between the first trace segment and the second trace segment will be blocked by the slope between the first trace segment and the second trace segment, thereby preventing the first trace segment from being connected to the second trace segment. The two wire segments are short-circuited through metal oxide, which prevents the first wire and the second wire from being short-circuited by metal oxide, thereby preventing the transmission of display data from being affected and improving display quality.

Description of the drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those of ordinary skill in the art, It is said that other drawings can be obtained based on these drawings without exerting creative labor.

Figure 1 is a schematic structural diagram of an array substrate provided by related technologies;

Figure 2 is a schematic diagram of a short circuit between the data traces and the touch traces of the array substrate shown in Figure 1;

Figure 3 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention;

Figure 4 is a schematic diagram of the arrangement of the first wiring and the second wiring provided by the embodiment of the present invention;

Figure 5 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

Figure 6 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

Figure 7 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

Figure 8 is a schematic diagram of the distribution of the first wiring, the second wiring and the pad structure in the array substrate shown in Figure 7;

Figure 9 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

Figure 10 is a schematic diagram of the distribution of the first wiring, the second wiring and the pad structure in the array substrate shown in Figure 9;

Figure 11 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

Figure 12 is a schematic diagram of the distribution of the first wiring, the second wiring and the pad structure in the array substrate shown in Figure 11;

Figure 13 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

Figure 14 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

Figure 15 is a schematic diagram of the distribution of the first wiring, the second wiring and the pad structure in the array substrate shown in Figure 14;

Figure 16 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

Figure 17 is a schematic structural diagram of another array substrate provided by an embodiment of the present invention;

Figure 18 is a schematic structural diagram of a display device provided by an embodiment of the present invention.

Detailed ways

In order to understand the above objects, features and advantages of the present invention more clearly, the solution of the present invention will be further described below. It should be noted that, as long as there is no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

FIG. 1 shows a schematic structural diagram of an array substrate prepared using a 7-channel photolithography (7mask) process in the related art. FIG. 2 shows a schematic structural diagram of a data trace and a touch trace when a short circuit occurs. Referring to Figures 1 and 2, this related technology improves the 8mask process. When preparing the array substrate, the inorganic layer 1 is used to replace the source and drain metal layers (including source S, drain D, and data traces) used in the 8mask process. 2 and touch traces 3 and other traces on the same layer). The planarization layer on the surface. However, the inorganic layer 1 is deposited using a chemical vapor deposition process, and the chemical vapor deposition process will oxidize the metal used to prepare the wiring (such as titanium) to produce metal oxide 4; and, in order to increase the pixel aperture ratio, the data path is Line 2 and touch trace 3 are both arranged between two adjacent pixels. Therefore, each touch trace 3 must have a very small distance from a data trace 2. At the same time, data trace 2 and The area between the touch traces 3 is relatively flat. At this time, the metal oxide 4 formed by the chemical vapor deposition process between the data traces 2 and the touch traces 3 can easily separate the data traces 2 and the touch traces 3. Short circuit (this situation will cause the data trace 2 and the touch trace 3 to be slightly short-circuited, and the gray screen will appear purple during the lighting test), resulting in poor display.

Based on the above technical problems, the inventor proposes a technical solution according to the embodiment of the present invention. Specifically, embodiments of the present invention provide an array substrate, including: a base substrate and a first insulating layer located on one side of the base substrate; first wiring and second wiring, both located far away from the first insulating layer. On the first surface of one side of the base substrate, a plurality of first traces extend along the first direction and are arranged along the second direction, and a plurality of second traces extend along the first direction and are arranged along the second direction, and the first direction and The second direction intersects; the second insulating layer covers the first surface of the first insulating layer, the surface of the first trace and the surface of the second trace, and the second insulating layer is an inorganic layer; wherein the first trace includes The first trace segment, the second trace segment includes the second trace segment, in the second direction, the first trace segment overlaps the second trace segment, and the spacing between the first trace segment and the second trace segment is less than or equal to the short circuit Distance threshold: the first surface of the first insulation layer includes at least a slope extending along the first direction and located between the first wiring segment and the second wiring segment.

Through the above technical solution, the area between the first trace and the second trace (ie, the first surface of the first insulation layer) can be changed from flat to uneven, effectively blocking the first trace and the second trace. The continuity of the metal oxide between the lines causes this part of the metal oxide to break, preventing the first trace and the second trace from being short-circuited.

It should be noted that the related art only provides examples of short-circuiting data traces and touch traces. The first traces and second traces involved in the embodiment of the present invention are not limited to data traces and touch traces. , the first trace and the second trace may be any two traces that can be short-circuited by the metal oxide produced by the chemical vapor deposition process used in preparing the inorganic layer.

The above is the core idea of the present invention. The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

FIG. 3 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention; FIG. 4 is a schematic diagram of the arrangement of first wiring and second wiring provided by an embodiment of the present invention. As shown in Figures 3 and 4, the array substrate includes: a base substrate 10 and a first insulating layer 20 located on one side of the base substrate 10; first wiring 30 and second wiring 40, both located on the first insulation layer. On the first surface of the layer 20 on the side away from the base substrate 10, a plurality of first traces 30 extend along the first direction X and are arranged along the second direction Y, and a plurality of second traces 40 extend along the first direction X and Arranged along the second direction Y, the first direction surface, the second insulating layer 50 is an inorganic layer; wherein, the first wiring 30 includes a first wiring segment 31, and the second wiring 40 includes a second wiring segment 41. In the second direction Y, the first wiring segment 31 and The second trace segments 41 overlap, the distance between the first trace segment 31 and the second trace segment 41 is less than or equal to the short circuit distance threshold, and the first surface of the first insulating layer 20 includes at least a slope 21 along which the slope 21 extends. The first direction X extends and is located between the first wiring segment 31 and the second wiring segment 41 .

In the above array substrate, the first insulating layer 20 may be an interlayer insulating layer, including but not limited to an interlayer insulating layer between a gate metal layer and a source and drain metal layer. The second insulating layer 50 is an inorganic layer, that is, the second insulating layer 50 is made of inorganic materials. In the embodiment of the present invention, the second insulating layer 50 is deposited using a chemical vapor deposition process. In this way, since the first traces 30 and the second traces 40 are directly exposed to the preparation environment of the second insulating layer 50, Part of the metal of the first trace 30 and the second trace 40 will be oxidized by the chemical vapor deposition process to form metal oxide. The formed metal oxide diffuses to the periphery. The metal oxide of the first trace 30 and the second trace The metal oxide of the wire 40 is easily electrically connected at a small distance between the first wire 30 and the second wire 40 , resulting in a short circuit between the first wire 30 and the second wire 40 . Based on this, the embodiment of the present invention divides the first trace 30 and the second trace 40 into trace segments with the risk of short circuit according to the short-circuit distance threshold, and obtains the first trace segment 31 and the second trace segment that overlap in the second direction Y. Route segment 41. Thus, by forming a slope 21 extending along the first direction The metal oxide on this side cannot "climb" up the slope 21; when the metal oxide on the other side goes down the slope, the metal oxide on this side will break due to the action of gravity on the slope 21. Therefore, the metal oxide of the first trace 30 and the metal oxide of the second trace 40 cannot be electrically connected at the slope 21 , thereby effectively avoiding a short circuit between the first trace 30 and the second trace 40 . It can be understood that the first trace segment 31 may be part or all of the first trace 30 , corresponding to the first trace segment, and the second trace segment 41 may be part or all of the second trace 40 . In addition, the first trace 30 may include one or more first trace segments 31, and accordingly, the second trace 40 may also include one or more second trace segments 41, depending on the actual wiring conditions.

The short-circuit distance threshold may be the maximum distance at which the first wiring segment 31 and the second wiring segment 41 can be short-circuited when preparing the first insulating layer 20 . The short-circuit distance threshold is mainly limited by the process, and may be determined based on the actual situation. Detection data is set. Optionally, the short distance threshold is less than the length and width of one pixel unit. In some embodiments, the short distance threshold is 20 microns. At this time, the distance between the first wiring segment 31 and the second wiring segment 41 is less than or equal to 20 microns, and the first wiring segment 31 and the second wiring segment 41 are short-circuited due to metal oxide formed by the chemical vapor deposition process. risks of. Therefore, as long as the slope 21 is provided between the trace segments with a pitch of less than or equal to 20 microns, the short circuit between the corresponding first trace 30 and the second trace 40 can be effectively avoided.

In addition, in some embodiments, the slope 21 may be formed by preparation of the first insulation layer 20 . For example, the first insulation layer 20 can be etched to form the slope 21 between the first wiring segment 31 and the second wiring segment 41 . The slope 21 may be a slope on one side of the step shown in Figure 3 formed by etching, or it may be a slope on both sides of the protrusion shown in Figure 5 formed by etching, or it may be formed by etching. The groove shown in Figure 6 has slopes on both sides. In addition, the slope 21 located between the first wiring segment 31 and the second wiring segment 41 may be a whole segment, or may be multiple segments staggered along the first direction X.

In other embodiments, a raised structure is provided between the base substrate 10 and the first insulating layer 20 , and the slope 21 may be formed by the first insulating layer 20 following the shape of the raised structure. Among them, the pad structure can be prepared separately, or it can be prepared on the same layer as the existing film layer structure. The relevant description of the raised structure can be found below, and will not be described in detail here.

It should be noted that the structural schematic diagram of the array substrate in the embodiment of the present invention only schematically shows the structure of the array substrate that can be implemented. The present invention does not place restrictions on other unmentioned film layers and film layer positions. Specifically, depending on the It depends on the actual situation.

In the array substrate provided in this embodiment, for the first trace and the second trace extending in the same direction, at least one slope is provided between the first trace segment of the first trace and the second trace segment of the second trace. surface, and the distance between the first trace segment and the second trace segment is less than or equal to the short distance threshold, the slope is the same as the extension direction of the first trace or the second trace, that is, the slope faces the first trace segment or Second trace segment settings. Therefore, the metal oxide produced by the chemical vapor deposition process between the first trace segment and the second trace segment will be blocked by the slope between the first trace segment and the second trace segment, thereby preventing the first trace segment from being connected to the second trace segment. The two wire segments are short-circuited through metal oxide, which prevents the first wire and the second wire from being short-circuited by metal oxide, thereby preventing the transmission of display data from being affected and improving display quality.

Based on the above technical solution, in some embodiments, in the second direction, the first trace segment overlaps at least part of the slope surface.

Specifically, in the second direction, the first wiring segment overlaps part of the slope, or the first wiring segment completely overlaps the slope; correspondingly, because in the second direction, the first wiring segment and the second wiring segment overlap Overlap, therefore, in the second direction, the second trace segment overlaps a part of the slope surface, or the second trace segment completely overlaps the slope surface. Therefore, the slope can completely block the electrical connection between the metal oxide formed on the first wiring segment and the metal oxide formed on the second wiring segment, thereby preventing the first wiring and the second wiring from being connected.

Since the short-circuit distance threshold is less than the length and width of a pixel unit, the two traces arranged between the pixel units will not be short-circuited due to the metal oxide formed by the chemical vapor deposition process; instead, between two adjacent pixel units When two traces need to be laid between pixel units, because the gap between pixel units is very small, and in order to increase the aperture ratio, the two traces need to be laid very close, and the distance between the two traces is less than or equal to the short distance threshold. Trace segments, so the two traces are prone to short circuits under the influence of the chemical vapor deposition process. Therefore, we only need to consider the problem of short circuit between two adjacent pixel units. Based on this, in some embodiments, the array substrate includes a plurality of pixel units, and the first wiring line and the second wiring line are located between adjacent pixel units along the second direction. Since the first trace and the second trace are located between adjacent pixel units, based on the above analysis, there must be a first trace segment on the first trace, a second trace segment must exist on the second trace, and the first trace segment must exist on the second trace. The distance between the trace segment and the second trace segment is less than or equal to the short distance threshold. In this way, only a slope is provided between the first trace and the second trace between adjacent pixel units, which can solve the problem of short circuiting of two adjacent traces due to the chemical vapor deposition process, without the need for Considering the anti-short circuit design of other adjacent traces, the structural design is relatively simple.

As mentioned above, the above-mentioned slope is formed by setting up a raising structure to prevent the first trace and the second trace from being short-circuited. In this regard, embodiments of the present invention describe in detail the design of the elevated structure.

In this embodiment of the present invention, the array substrate further includes at least a section of a raised structure located between the base substrate and the first insulating layer. The raised structure extends along the first direction so that the first surface of the first insulating layer forms a slope. By arranging at least one section of the raised structure between the base substrate and the first insulating layer, at least one section can be formed on the first surface of the first insulating layer without changing the preparation process of the film layer above the raised structure. Slope.

Specifically, in some embodiments, as shown in FIGS. 7 and 8 , the vertical projection of the raising structure 60 on the plane of the substrate 10 is located between the adjacent first traces 30 and the second traces 40 on the substrate. between the vertical projections on the plane where the base substrate 10 is located. In this way, combined with the technical solution of the present invention, it can be seen that a protrusion extending in the first direction will be formed on the first surface of the first insulating layer 20 between the first wiring segment and the second wiring segment, and the slopes on both sides of the protrusion That is slope 21. Therefore, this embodiment can form two slopes 21, so that the metal oxide of the first trace segment and the metal oxide of the second trace segment both need to climb the slope 21, thereby effectively blocking the metal oxide of the two trace segments. The oxides diffuse toward each other, thereby preventing the first trace and the second trace from being shorted.

In some embodiments, as shown in FIGS. 9 and 10 , the vertical projection of the raising structure 60 on the plane of the base substrate 10 overlaps with the vertical projection of the first trace 30 on the plane of the base substrate 10 . In this way, combined with the technical solution of the present invention, it can be seen that a step extending along the first direction will be formed on the first surface of the first insulating layer 20 between the first wiring section and the second wiring section, and the slope of the step is the slope. twenty one. Therefore, this embodiment can form a slope facing the second trace 40 , so that the metal oxide of the first trace segment needs to go downhill at the slope 21 , so that the metal oxide of the first trace segment needs to go downhill at the slope 21 . break, and the metal oxide of the second trace segment needs to climb up the slope 21, thereby effectively blocking the metal oxide of the two trace segments from diffusing toward each other, thereby preventing the first trace and the second trace from being short-circuited.

In addition, in some embodiments, as shown in FIGS. 11 and 12 , the vertical projection of the raising structure 60 on the plane of the base substrate 10 intersects with the vertical projection of the second trace 40 on the plane of the base substrate 10 Stack. In this way, combined with the technical solution of the present invention, it can be seen that a step extending along the first direction will be formed on the first surface of the first insulating layer 20 between the first wiring section and the second wiring section, and the slope of the step is the slope. twenty one. Therefore, this embodiment can form a slope facing the first trace 30 , so that the metal oxide of the first trace segment needs to climb the slope 21 , while the metal oxide of the second trace segment needs to climb the slope 21 . downhill, causing the metal oxide of the second trace segment to break at the slope 21, effectively blocking the metal oxides of the two trace segments from diffusing toward each other, thereby preventing the first trace and the second trace from being short-circuited.

In some embodiments, the second trace is a touch trace, the pad structure is a conductor, and the second trace is electrically connected to the pad structure through at least one through hole. Referring to Figure 13, when the second trace 40 is a touch trace and the pad structure 60 is a conductor, while the pad structure 60 is used to form the slope 21, the second trace 40 is passed through the through hole and the pad structure. The 60 electrical connection can reduce the impedance of the touch trace, thereby reducing the voltage drop of the touch signal on the touch trace, reducing power consumption and improving the transmission accuracy of the touch signal.

Based on the above embodiments, in other embodiments, as shown in FIGS. 14 and 15 , the raising structure includes a first raising structure 61 and a second raising structure 62 ; the first raising structure 61 is located where the substrate 10 is located. The vertical projection on the plane overlaps with the vertical projection of the first trace 30 on the plane of the base substrate 10; the vertical projection of the second raising structure 62 on the plane of the base substrate 10 overlaps with the vertical projection of the second trace 40 on the plane of the base substrate 10. The vertical projections on the plane of the base substrate 10 overlap. In this way, combined with the technical solution of the present invention, it can be seen that due to the existence of the first raising structure 61, a line extending in the first direction will be formed on the first surface of the first insulating layer 20 between the first wiring segment and the second wiring segment. The first step, and the slope of the first step is the slope 21. At the same time, due to the existence of the second raising structure 62, a second step extending along the first direction will be formed on the first surface of the first insulation layer 20 between the first wiring segment and the second wiring segment, and the second step The slope of is also slope 21. Therefore, this embodiment can form the slope 21 facing the first trace 30 and the slope 21 facing the second trace 40, so that the metal oxide of the first trace segment and the metal oxide of the second trace segment are on the slope. All 21 locations require climbing, which effectively blocks the metal oxides of the two trace segments from diffusing to each other, thereby preventing the first trace and the second trace from being short-circuited.

In some embodiments, the second trace is a touch trace, the second pad structure is a conductor, and the second trace is electrically connected to the second pad structure through at least one through hole. Referring to FIG. 16 , when the second trace 40 is a touch trace and the second raising structure 62 is a conductor, while the second raising structure 62 is used to form the slope 21 , the second trace 40 is passed through the through hole. Being electrically connected to the second raising structure 62 can reduce the impedance of the touch trace, thereby reducing the voltage drop of the touch signal on the touch trace, reducing power consumption, and improving the transmission accuracy of the touch signal.

In each of the above embodiments, the array substrate further includes a first metal layer located between the base substrate and the first insulating layer. The first metal layer includes a plurality of scan lines extending along the second direction and arranged along the first direction and at least A dummy trace extends along the first direction, the dummy trace is electrically insulated from the scan line, and the dummy trace is a raised structure. In this way, the pad structure can be prepared in the same photolithography process as the scan line, which can avoid additional photolithography processes, thereby improving the preparation efficiency of the array substrate and saving costs.

In some embodiments, as shown in FIG. 17 , the array substrate further includes a pixel circuit layer, a first electrode layer 70 , a third insulating layer 80 and a second electrode layer 90 . The pixel circuit layer includes a first metal layer (i.e., a padding layer). The metal layer where the structure 60 is located), the first insulating layer 20 and the second metal layer. The second metal layer includes a first wiring 30 and a second wiring 40. The first wiring 30 is a data wiring, and the second wiring 40 is a touch trace, the third insulating layer 80 is an inorganic layer, the first electrode layer 70 is located on the surface of the second insulating layer 50 away from the base substrate 10, the second insulating layer 50, the first electrode layer 70, the The three insulating layers 80 and the second electrode layer 90 are stacked, and the second electrode layer 90 is connected to the second wiring 40 through via holes. Optionally, the above-mentioned array substrate can be prepared using a 7mask process, in which the second electrode layer 90 can include a touch electrode, and the touch electrode passes through a via hole and a touch trace that penetrates the third insulating layer 80 and the second insulating layer 50 Electrical connection; alternatively, the first electrode layer 70 may include a touch electrode, the second electrode layer 90 may include a cross-bridge structure, and the touch electrodes are electrically connected to the touch traces through the cross-bridge structure (the structure shown in FIG. 17 ).

In addition, an embodiment of the present invention also provides a display panel, including the array substrate provided in any of the above embodiments.

Finally, embodiments of the present invention also provide a display device, including the display panel provided in the above embodiments. As shown in FIG. 18 , the display device 200 includes the display panel 100 provided by the embodiment of the present invention. The display device may be a mobile phone, a computer, a television, a vehicle-mounted display device, or any other display device with a display function, which is not specifically limited in the embodiment of the present invention. The display device 200 provided by the embodiment of the present invention has the beneficial effects of the array substrate provided by the embodiment of the present invention. For details, reference can be made to the specific description of the array substrate in the above embodiment, and the details of the embodiment of the present invention will not be repeated here.

It should be noted that in this article, relational terms such as “first” and “second” are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these There is no such actual relationship or sequence between entities or operations. Furthermore, the terms "comprises," "comprises," or any other variations thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also those not expressly listed other elements, or elements inherent to the process, method, article or equipment. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article, or apparatus that includes the stated element.

The above descriptions are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be practiced in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (14)

1. An array substrate, characterized by comprising:

a substrate base plate and a first insulating layer positioned at one side of the substrate base plate;

the first wires and the second wires are positioned on the first surface of the first insulating layer, which is far away from one side of the substrate base plate, the first wires extend along a first direction and are arranged along a second direction, the second wires extend along the first direction and are arranged along the second direction, and the first direction is intersected with the second direction;

the second insulating layer covers the first surface of the first insulating layer, the surface of the first wiring and the surface of the second wiring, and is an inorganic layer;

the first wire comprises a first wire segment, the second wire comprises a second wire segment, in the second direction, the first wire segment and the second wire segment are overlapped, the distance between the first wire segment and the second wire segment is smaller than or equal to a short-circuit distance threshold value, the first surface of the first insulating layer comprises at least one section of slope surface, and the slope surface extends along the first direction and is located between the first wire segment and the second wire segment.

2. The array substrate of claim 1, wherein in the second direction, the first trace segment overlaps at least a portion of the ramp.

3. The array substrate of claim 1, wherein the array substrate comprises a plurality of pixel cells, and the first trace and the second trace are located between adjacent pixel cells along the second direction.

4. The array substrate of claim 1, further comprising at least one length of raised structure between the substrate and the first insulating layer, the raised structure extending in the first direction such that the first surface of the first insulating layer forms the slope.

5. The array substrate of claim 4, wherein a vertical projection of the raised structure on the plane of the substrate is located between a vertical projection of the adjacent first trace and second trace on the plane of the substrate.

6. The array substrate of claim 4, wherein a vertical projection of the raised structure on a plane of the substrate overlaps with a vertical projection of the first trace on the plane of the substrate.

7. The array substrate of claim 4, wherein a vertical projection of the raised structure on a plane of the substrate overlaps with a vertical projection of the second trace on the plane of the substrate.

8. The array substrate of claim 4, wherein the elevated structures comprise a first elevated structure and a second elevated structure; the vertical projection of the first heightening structure on the plane of the substrate is overlapped with the vertical projection of the first wire on the plane of the substrate; and the vertical projection of the second elevating structure on the plane of the substrate overlaps with the vertical projection of the second wiring on the plane of the substrate.

9. The array substrate of claim 7, wherein the second trace is a touch trace, the raised structure is a conductor, and the second trace is electrically connected to the raised structure through at least one via.

10. The array substrate of claim 4, further comprising a first metal layer between the substrate and the first insulating layer, the first metal layer including a plurality of scan lines extending in the second direction and aligned in the first direction and at least one dummy trace extending in the first direction, the dummy trace being electrically insulated from the scan lines, and the dummy trace being the raised structure.

11. The array substrate of claim 10, further comprising a pixel circuit layer, a first electrode layer, a third insulating layer, and a second electrode layer, wherein the pixel circuit layer comprises the first metal layer, the first insulating layer, and the second metal layer comprises the first trace and the second trace, the first trace is a data trace, the second trace is a touch trace, the third insulating layer is an inorganic layer, the first electrode layer is located on a surface of the second insulating layer away from one side of the substrate, the second insulating layer, the first electrode layer, the third insulating layer, and the second electrode layer are stacked, and the second electrode layer is connected with the second trace through a via.

12. The array substrate of claim 1, wherein the shorting distance threshold is 20 microns.

13. A display panel comprising an array substrate according to any one of claims 1 to 12.

14. A display device comprising the display panel according to claim 13.